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bnxt_ethdev.c
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bnxt_ethdev.c
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/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2014-2021 Broadcom
* All rights reserved.
*/
#include <inttypes.h>
#include <stdbool.h>
#include <rte_dev.h>
#include <ethdev_driver.h>
#include <ethdev_pci.h>
#include <rte_malloc.h>
#include <rte_cycles.h>
#include <rte_alarm.h>
#include <rte_kvargs.h>
#include <rte_vect.h>
#include "bnxt.h"
#include "bnxt_filter.h"
#include "bnxt_hwrm.h"
#include "bnxt_irq.h"
#include "bnxt_reps.h"
#include "bnxt_ring.h"
#include "bnxt_rxq.h"
#include "bnxt_rxr.h"
#include "bnxt_stats.h"
#include "bnxt_txq.h"
#include "bnxt_txr.h"
#include "bnxt_vnic.h"
#include "hsi_struct_def_dpdk.h"
#include "bnxt_nvm_defs.h"
#include "bnxt_tf_common.h"
#include "ulp_flow_db.h"
#include "rte_pmd_bnxt.h"
#define DRV_MODULE_NAME "bnxt"
static const char bnxt_version[] =
"Broadcom NetXtreme driver " DRV_MODULE_NAME;
/*
* The set of PCI devices this driver supports
*/
static const struct rte_pci_id bnxt_pci_id_map[] = {
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
{ .vendor_id = 0, /* sentinel */ },
};
#define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
#define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
#define BNXT_DEVARG_REPRESENTOR "representor"
#define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
#define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
#define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
#define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
#define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
#define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
#define BNXT_DEVARG_APP_ID "app-id"
static const char *const bnxt_dev_args[] = {
BNXT_DEVARG_REPRESENTOR,
BNXT_DEVARG_FLOW_XSTAT,
BNXT_DEVARG_MAX_NUM_KFLOWS,
BNXT_DEVARG_REP_BASED_PF,
BNXT_DEVARG_REP_IS_PF,
BNXT_DEVARG_REP_Q_R2F,
BNXT_DEVARG_REP_Q_F2R,
BNXT_DEVARG_REP_FC_R2F,
BNXT_DEVARG_REP_FC_F2R,
BNXT_DEVARG_APP_ID,
NULL
};
/*
* app-id = an non-negative 8-bit number
*/
#define BNXT_DEVARG_APP_ID_INVALID(val) ((val) > 255)
/*
* flow_xstat == false to disable the feature
* flow_xstat == true to enable the feature
*/
#define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
/*
* rep_is_pf == false to indicate VF representor
* rep_is_pf == true to indicate PF representor
*/
#define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
/*
* rep_based_pf == Physical index of the PF
*/
#define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
/*
* rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
*/
#define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
/*
* rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
*/
#define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
/*
* rep_fc_r2f == Flow control for the representor to endpoint direction
*/
#define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
/*
* rep_fc_f2r == Flow control for the endpoint to representor direction
*/
#define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
int bnxt_cfa_code_dynfield_offset = -1;
/*
* max_num_kflows must be >= 32
* and must be a power-of-2 supported value
* return: 1 -> invalid
* 0 -> valid
*/
static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
{
if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
return 1;
return 0;
}
static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
static void bnxt_cancel_fw_health_check(struct bnxt *bp);
static int bnxt_restore_vlan_filters(struct bnxt *bp);
static void bnxt_dev_recover(void *arg);
static void bnxt_free_error_recovery_info(struct bnxt *bp);
static void bnxt_free_rep_info(struct bnxt *bp);
static int bnxt_check_fw_ready(struct bnxt *bp);
int is_bnxt_in_error(struct bnxt *bp)
{
if (bp->flags & BNXT_FLAG_FATAL_ERROR)
return -EIO;
if (bp->flags & BNXT_FLAG_FW_RESET)
return -EBUSY;
return 0;
}
/***********************/
/*
* High level utility functions
*/
static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
{
unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
BNXT_RSS_TBL_SIZE_P5);
if (!BNXT_CHIP_P5(bp))
return 1;
return RTE_ALIGN_MUL_CEIL(num_rss_rings,
BNXT_RSS_ENTRIES_PER_CTX_P5) /
BNXT_RSS_ENTRIES_PER_CTX_P5;
}
uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
{
if (!BNXT_CHIP_P5(bp))
return HW_HASH_INDEX_SIZE;
return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
}
static void bnxt_free_parent_info(struct bnxt *bp)
{
rte_free(bp->parent);
bp->parent = NULL;
}
static void bnxt_free_pf_info(struct bnxt *bp)
{
rte_free(bp->pf);
bp->pf = NULL;
}
static void bnxt_free_link_info(struct bnxt *bp)
{
rte_free(bp->link_info);
bp->link_info = NULL;
}
static void bnxt_free_leds_info(struct bnxt *bp)
{
if (BNXT_VF(bp))
return;
rte_free(bp->leds);
bp->leds = NULL;
}
static void bnxt_free_flow_stats_info(struct bnxt *bp)
{
rte_free(bp->flow_stat);
bp->flow_stat = NULL;
}
static void bnxt_free_cos_queues(struct bnxt *bp)
{
rte_free(bp->rx_cos_queue);
bp->rx_cos_queue = NULL;
rte_free(bp->tx_cos_queue);
bp->tx_cos_queue = NULL;
}
static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
{
bnxt_free_filter_mem(bp);
bnxt_free_vnic_attributes(bp);
bnxt_free_vnic_mem(bp);
/* tx/rx rings are configured as part of *_queue_setup callbacks.
* If the number of rings change across fw update,
* we don't have much choice except to warn the user.
*/
if (!reconfig) {
bnxt_free_stats(bp);
bnxt_free_tx_rings(bp);
bnxt_free_rx_rings(bp);
}
bnxt_free_async_cp_ring(bp);
bnxt_free_rxtx_nq_ring(bp);
rte_free(bp->grp_info);
bp->grp_info = NULL;
}
static int bnxt_alloc_parent_info(struct bnxt *bp)
{
bp->parent = rte_zmalloc("bnxt_parent_info",
sizeof(struct bnxt_parent_info), 0);
if (bp->parent == NULL)
return -ENOMEM;
return 0;
}
static int bnxt_alloc_pf_info(struct bnxt *bp)
{
bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
if (bp->pf == NULL)
return -ENOMEM;
return 0;
}
static int bnxt_alloc_link_info(struct bnxt *bp)
{
bp->link_info =
rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
if (bp->link_info == NULL)
return -ENOMEM;
return 0;
}
static int bnxt_alloc_leds_info(struct bnxt *bp)
{
if (BNXT_VF(bp))
return 0;
bp->leds = rte_zmalloc("bnxt_leds",
BNXT_MAX_LED * sizeof(struct bnxt_led_info),
0);
if (bp->leds == NULL)
return -ENOMEM;
return 0;
}
static int bnxt_alloc_cos_queues(struct bnxt *bp)
{
bp->rx_cos_queue =
rte_zmalloc("bnxt_rx_cosq",
BNXT_COS_QUEUE_COUNT *
sizeof(struct bnxt_cos_queue_info),
0);
if (bp->rx_cos_queue == NULL)
return -ENOMEM;
bp->tx_cos_queue =
rte_zmalloc("bnxt_tx_cosq",
BNXT_COS_QUEUE_COUNT *
sizeof(struct bnxt_cos_queue_info),
0);
if (bp->tx_cos_queue == NULL)
return -ENOMEM;
return 0;
}
static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
{
bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
sizeof(struct bnxt_flow_stat_info), 0);
if (bp->flow_stat == NULL)
return -ENOMEM;
return 0;
}
static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
{
int rc;
rc = bnxt_alloc_ring_grps(bp);
if (rc)
goto alloc_mem_err;
rc = bnxt_alloc_async_ring_struct(bp);
if (rc)
goto alloc_mem_err;
rc = bnxt_alloc_vnic_mem(bp);
if (rc)
goto alloc_mem_err;
rc = bnxt_alloc_vnic_attributes(bp, reconfig);
if (rc)
goto alloc_mem_err;
rc = bnxt_alloc_filter_mem(bp);
if (rc)
goto alloc_mem_err;
rc = bnxt_alloc_async_cp_ring(bp);
if (rc)
goto alloc_mem_err;
rc = bnxt_alloc_rxtx_nq_ring(bp);
if (rc)
goto alloc_mem_err;
if (BNXT_FLOW_XSTATS_EN(bp)) {
rc = bnxt_alloc_flow_stats_info(bp);
if (rc)
goto alloc_mem_err;
}
return 0;
alloc_mem_err:
bnxt_free_mem(bp, reconfig);
return rc;
}
static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
{
struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
uint64_t rx_offloads = dev_conf->rxmode.offloads;
struct bnxt_rx_queue *rxq;
unsigned int j;
int rc;
rc = bnxt_vnic_grp_alloc(bp, vnic);
if (rc)
goto err_out;
PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
vnic_id, vnic, vnic->fw_grp_ids);
rc = bnxt_hwrm_vnic_alloc(bp, vnic);
if (rc)
goto err_out;
/* Alloc RSS context only if RSS mode is enabled */
if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS) {
int j, nr_ctxs = bnxt_rss_ctxts(bp);
/* RSS table size in Thor is 512.
* Cap max Rx rings to same value
*/
if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
goto err_out;
}
rc = 0;
for (j = 0; j < nr_ctxs; j++) {
rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
if (rc)
break;
}
if (rc) {
PMD_DRV_LOG(ERR,
"HWRM vnic %d ctx %d alloc failure rc: %x\n",
vnic_id, j, rc);
goto err_out;
}
vnic->num_lb_ctxts = nr_ctxs;
}
/*
* Firmware sets pf pair in default vnic cfg. If the VLAN strip
* setting is not available at this time, it will not be
* configured correctly in the CFA.
*/
if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
vnic->vlan_strip = true;
else
vnic->vlan_strip = false;
rc = bnxt_hwrm_vnic_cfg(bp, vnic);
if (rc)
goto err_out;
rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
if (rc)
goto err_out;
for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
rxq = bp->eth_dev->data->rx_queues[j];
PMD_DRV_LOG(DEBUG,
"rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
j, rxq->vnic, rxq->vnic->fw_grp_ids);
if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
else
vnic->rx_queue_cnt++;
}
PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
rc = bnxt_vnic_rss_configure(bp, vnic);
if (rc)
goto err_out;
bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
(rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) ?
true : false);
if (rc)
goto err_out;
return 0;
err_out:
PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
vnic_id, rc);
return rc;
}
static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
{
int rc = 0;
rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
&bp->flow_stat->rx_fc_in_tbl.ctx_id);
if (rc)
return rc;
PMD_DRV_LOG(DEBUG,
"rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
" rx_fc_in_tbl.ctx_id = %d\n",
bp->flow_stat->rx_fc_in_tbl.va,
(void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
bp->flow_stat->rx_fc_in_tbl.ctx_id);
rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
&bp->flow_stat->rx_fc_out_tbl.ctx_id);
if (rc)
return rc;
PMD_DRV_LOG(DEBUG,
"rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
" rx_fc_out_tbl.ctx_id = %d\n",
bp->flow_stat->rx_fc_out_tbl.va,
(void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
bp->flow_stat->rx_fc_out_tbl.ctx_id);
rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
&bp->flow_stat->tx_fc_in_tbl.ctx_id);
if (rc)
return rc;
PMD_DRV_LOG(DEBUG,
"tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
" tx_fc_in_tbl.ctx_id = %d\n",
bp->flow_stat->tx_fc_in_tbl.va,
(void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
bp->flow_stat->tx_fc_in_tbl.ctx_id);
rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
&bp->flow_stat->tx_fc_out_tbl.ctx_id);
if (rc)
return rc;
PMD_DRV_LOG(DEBUG,
"tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
" tx_fc_out_tbl.ctx_id = %d\n",
bp->flow_stat->tx_fc_out_tbl.va,
(void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
bp->flow_stat->tx_fc_out_tbl.ctx_id);
memset(bp->flow_stat->rx_fc_out_tbl.va,
0,
bp->flow_stat->rx_fc_out_tbl.size);
rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
bp->flow_stat->rx_fc_out_tbl.ctx_id,
bp->flow_stat->max_fc,
true);
if (rc)
return rc;
memset(bp->flow_stat->tx_fc_out_tbl.va,
0,
bp->flow_stat->tx_fc_out_tbl.size);
rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
bp->flow_stat->tx_fc_out_tbl.ctx_id,
bp->flow_stat->max_fc,
true);
return rc;
}
static int bnxt_alloc_ctx_mem_buf(struct bnxt *bp, char *type, size_t size,
struct bnxt_ctx_mem_buf_info *ctx)
{
if (!ctx)
return -EINVAL;
ctx->va = rte_zmalloc_socket(type, size, 0,
bp->eth_dev->device->numa_node);
if (ctx->va == NULL)
return -ENOMEM;
rte_mem_lock_page(ctx->va);
ctx->size = size;
ctx->dma = rte_mem_virt2iova(ctx->va);
if (ctx->dma == RTE_BAD_IOVA)
return -ENOMEM;
return 0;
}
static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
{
struct rte_pci_device *pdev = bp->pdev;
char type[RTE_MEMZONE_NAMESIZE];
uint16_t max_fc;
int rc = 0;
max_fc = bp->flow_stat->max_fc;
sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
/* 4 bytes for each counter-id */
rc = bnxt_alloc_ctx_mem_buf(bp, type,
max_fc * 4,
&bp->flow_stat->rx_fc_in_tbl);
if (rc)
return rc;
sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
/* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
rc = bnxt_alloc_ctx_mem_buf(bp, type,
max_fc * 16,
&bp->flow_stat->rx_fc_out_tbl);
if (rc)
return rc;
sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
/* 4 bytes for each counter-id */
rc = bnxt_alloc_ctx_mem_buf(bp, type,
max_fc * 4,
&bp->flow_stat->tx_fc_in_tbl);
if (rc)
return rc;
sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
/* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
rc = bnxt_alloc_ctx_mem_buf(bp, type,
max_fc * 16,
&bp->flow_stat->tx_fc_out_tbl);
if (rc)
return rc;
rc = bnxt_register_fc_ctx_mem(bp);
return rc;
}
static int bnxt_init_ctx_mem(struct bnxt *bp)
{
int rc = 0;
if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
!BNXT_FLOW_XSTATS_EN(bp))
return 0;
rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
if (rc)
return rc;
rc = bnxt_init_fc_ctx_mem(bp);
return rc;
}
static inline bool bnxt_force_link_config(struct bnxt *bp)
{
uint16_t subsystem_device_id = bp->pdev->id.subsystem_device_id;
switch (subsystem_device_id) {
case BROADCOM_DEV_957508_N2100:
case BROADCOM_DEV_957414_N225:
return true;
default:
return false;
}
}
static int bnxt_update_phy_setting(struct bnxt *bp)
{
struct rte_eth_link new;
int rc;
rc = bnxt_get_hwrm_link_config(bp, &new);
if (rc) {
PMD_DRV_LOG(ERR, "Failed to get link settings\n");
return rc;
}
/*
* Device is not obliged link down in certain scenarios, even
* when forced. When FW does not allow any user other than BMC
* to shutdown the port, bnxt_get_hwrm_link_config() call always
* returns link up. Force phy update always in that case.
*/
if (!new.link_status || bnxt_force_link_config(bp)) {
rc = bnxt_set_hwrm_link_config(bp, true);
if (rc) {
PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
return rc;
}
}
return rc;
}
static void bnxt_free_prev_ring_stats(struct bnxt *bp)
{
rte_free(bp->prev_rx_ring_stats);
rte_free(bp->prev_tx_ring_stats);
bp->prev_rx_ring_stats = NULL;
bp->prev_tx_ring_stats = NULL;
}
static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
{
bp->prev_rx_ring_stats = rte_zmalloc("bnxt_prev_rx_ring_stats",
sizeof(struct bnxt_ring_stats) *
bp->rx_cp_nr_rings,
0);
if (bp->prev_rx_ring_stats == NULL)
return -ENOMEM;
bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
sizeof(struct bnxt_ring_stats) *
bp->tx_cp_nr_rings,
0);
if (bp->tx_cp_nr_rings > 0 && bp->prev_tx_ring_stats == NULL)
goto error;
return 0;
error:
bnxt_free_prev_ring_stats(bp);
return -ENOMEM;
}
static int bnxt_start_nic(struct bnxt *bp)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
uint32_t intr_vector = 0;
uint32_t queue_id, base = BNXT_MISC_VEC_ID;
uint32_t vec = BNXT_MISC_VEC_ID;
unsigned int i, j;
int rc;
if (bp->eth_dev->data->mtu > RTE_ETHER_MTU)
bp->flags |= BNXT_FLAG_JUMBO;
else
bp->flags &= ~BNXT_FLAG_JUMBO;
/* THOR does not support ring groups.
* But we will use the array to save RSS context IDs.
*/
if (BNXT_CHIP_P5(bp))
bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
rc = bnxt_alloc_hwrm_rings(bp);
if (rc) {
PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
goto err_out;
}
rc = bnxt_alloc_all_hwrm_ring_grps(bp);
if (rc) {
PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
goto err_out;
}
if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
goto skip_cosq_cfg;
for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
if (bp->rx_cos_queue[i].id != 0xff) {
struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
if (!vnic) {
PMD_DRV_LOG(ERR,
"Num pools more than FW profile\n");
rc = -EINVAL;
goto err_out;
}
vnic->cos_queue_id = bp->rx_cos_queue[i].id;
bp->rx_cosq_cnt++;
}
}
skip_cosq_cfg:
rc = bnxt_mq_rx_configure(bp);
if (rc) {
PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
goto err_out;
}
for (j = 0; j < bp->rx_nr_rings; j++) {
struct bnxt_rx_queue *rxq = bp->rx_queues[j];
if (!rxq->rx_deferred_start) {
bp->eth_dev->data->rx_queue_state[j] =
RTE_ETH_QUEUE_STATE_STARTED;
rxq->rx_started = true;
}
}
/* VNIC configuration */
for (i = 0; i < bp->nr_vnics; i++) {
rc = bnxt_setup_one_vnic(bp, i);
if (rc)
goto err_out;
}
for (j = 0; j < bp->tx_nr_rings; j++) {
struct bnxt_tx_queue *txq = bp->tx_queues[j];
if (!txq->tx_deferred_start) {
bp->eth_dev->data->tx_queue_state[j] =
RTE_ETH_QUEUE_STATE_STARTED;
txq->tx_started = true;
}
}
rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
if (rc) {
PMD_DRV_LOG(ERR,
"HWRM cfa l2 rx mask failure rc: %x\n", rc);
goto err_out;
}
/* check and configure queue intr-vector mapping */
if ((rte_intr_cap_multiple(intr_handle) ||
!RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
intr_vector = bp->eth_dev->data->nb_rx_queues;
PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
if (intr_vector > bp->rx_cp_nr_rings) {
PMD_DRV_LOG(ERR, "At most %d intr queues supported",
bp->rx_cp_nr_rings);
return -ENOTSUP;
}
rc = rte_intr_efd_enable(intr_handle, intr_vector);
if (rc)
return rc;
}
if (rte_intr_dp_is_en(intr_handle)) {
if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
bp->eth_dev->data->nb_rx_queues)) {
PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
" intr_vec", bp->eth_dev->data->nb_rx_queues);
rc = -ENOMEM;
goto err_out;
}
PMD_DRV_LOG(DEBUG, "intr_handle->nb_efd = %d "
"intr_handle->max_intr = %d\n",
rte_intr_nb_efd_get(intr_handle),
rte_intr_max_intr_get(intr_handle));
for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
queue_id++) {
rte_intr_vec_list_index_set(intr_handle,
queue_id, vec + BNXT_RX_VEC_START);
if (vec < base + rte_intr_nb_efd_get(intr_handle)
- 1)
vec++;
}
}
/* enable uio/vfio intr/eventfd mapping */
rc = rte_intr_enable(intr_handle);
#ifndef RTE_EXEC_ENV_FREEBSD
/* In FreeBSD OS, nic_uio driver does not support interrupts */
if (rc)
goto err_out;
#endif
rc = bnxt_update_phy_setting(bp);
if (rc)
goto err_out;
bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
if (!bp->mark_table)
PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
return 0;
err_out:
/* Some of the error status returned by FW may not be from errno.h */
if (rc > 0)
rc = -EIO;
return rc;
}
static int bnxt_shutdown_nic(struct bnxt *bp)
{
bnxt_free_all_hwrm_resources(bp);
bnxt_free_all_filters(bp);
bnxt_free_all_vnics(bp);
return 0;
}
/*
* Device configuration and status function
*/
uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
{
uint32_t link_speed = 0;
uint32_t speed_capa = 0;
if (bp->link_info == NULL)
return 0;
link_speed = bp->link_info->support_speeds;
/* If PAM4 is configured, use PAM4 supported speed */
if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
link_speed = bp->link_info->support_pam4_speeds;
if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
speed_capa |= RTE_ETH_LINK_SPEED_100M;
if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
speed_capa |= RTE_ETH_LINK_SPEED_100M_HD;
if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
speed_capa |= RTE_ETH_LINK_SPEED_1G;
if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
speed_capa |= RTE_ETH_LINK_SPEED_2_5G;
if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
speed_capa |= RTE_ETH_LINK_SPEED_10G;
if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
speed_capa |= RTE_ETH_LINK_SPEED_20G;
if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
speed_capa |= RTE_ETH_LINK_SPEED_25G;
if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
speed_capa |= RTE_ETH_LINK_SPEED_40G;
if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
speed_capa |= RTE_ETH_LINK_SPEED_50G;
if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
speed_capa |= RTE_ETH_LINK_SPEED_100G;
if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
speed_capa |= RTE_ETH_LINK_SPEED_50G;
if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
speed_capa |= RTE_ETH_LINK_SPEED_100G;
if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
speed_capa |= RTE_ETH_LINK_SPEED_200G;
if (bp->link_info->auto_mode ==
HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
speed_capa |= RTE_ETH_LINK_SPEED_FIXED;
return speed_capa;
}
static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
struct rte_eth_dev_info *dev_info)
{
struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
struct bnxt *bp = eth_dev->data->dev_private;
uint16_t max_vnics, i, j, vpool, vrxq;
unsigned int max_rx_rings;
int rc;
rc = is_bnxt_in_error(bp);
if (rc)
return rc;
/* MAC Specifics */
dev_info->max_mac_addrs = RTE_MIN(bp->max_l2_ctx, RTE_ETH_NUM_RECEIVE_MAC_ADDR);
dev_info->max_hash_mac_addrs = 0;
/* PF/VF specifics */
if (BNXT_PF(bp))
dev_info->max_vfs = pdev->max_vfs;
max_rx_rings = bnxt_max_rings(bp);
/* For the sake of symmetry, max_rx_queues = max_tx_queues */
dev_info->max_rx_queues = max_rx_rings;
dev_info->max_tx_queues = max_rx_rings;
dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
dev_info->hash_key_size = HW_HASH_KEY_SIZE;
max_vnics = bp->max_vnics;
/* MTU specifics */
dev_info->min_mtu = RTE_ETHER_MIN_MTU;
dev_info->max_mtu = BNXT_MAX_MTU;
/* Fast path specifics */
dev_info->min_rx_bufsize = 1;
dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
dev_info->rx_offload_capa = bnxt_get_rx_port_offloads(bp);
dev_info->tx_queue_offload_capa = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
dev_info->tx_offload_capa = bnxt_get_tx_port_offloads(bp) |
dev_info->tx_queue_offload_capa;
dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
dev_info->default_rxconf = (struct rte_eth_rxconf) {