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hns3_ethdev_vf.c
2517 lines (2142 loc) · 67.4 KB
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hns3_ethdev_vf.c
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/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2018-2021 HiSilicon Limited.
*/
#include <linux/pci_regs.h>
#include <rte_alarm.h>
#include <ethdev_pci.h>
#include <rte_io.h>
#include <rte_pci.h>
#include <rte_vfio.h>
#include "hns3_ethdev.h"
#include "hns3_common.h"
#include "hns3_logs.h"
#include "hns3_rxtx.h"
#include "hns3_regs.h"
#include "hns3_intr.h"
#include "hns3_dcb.h"
#include "hns3_mp.h"
#include "hns3_flow.h"
#define HNS3VF_KEEP_ALIVE_INTERVAL 2000000 /* us */
#define HNS3VF_SERVICE_INTERVAL 1000000 /* us */
#define HNS3VF_RESET_WAIT_MS 20
#define HNS3VF_RESET_WAIT_CNT 2000
/* Reset related Registers */
#define HNS3_GLOBAL_RESET_BIT 0
#define HNS3_CORE_RESET_BIT 1
#define HNS3_IMP_RESET_BIT 2
#define HNS3_FUN_RST_ING_B 0
enum hns3vf_evt_cause {
HNS3VF_VECTOR0_EVENT_RST,
HNS3VF_VECTOR0_EVENT_MBX,
HNS3VF_VECTOR0_EVENT_OTHER,
};
static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
uint64_t *levels);
static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
struct rte_ether_addr *mac_addr);
static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
struct rte_ether_addr *mac_addr);
static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
__rte_unused int wait_to_complete);
/* set PCI bus mastering */
static int
hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
{
uint16_t reg;
int ret;
ret = rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND);
if (ret < 0) {
PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
PCI_COMMAND);
return ret;
}
if (op)
/* set the master bit */
reg |= PCI_COMMAND_MASTER;
else
reg &= ~(PCI_COMMAND_MASTER);
return rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND);
}
/**
* hns3vf_find_pci_capability - lookup a capability in the PCI capability list
* @cap: the capability
*
* Return the address of the given capability within the PCI capability list.
*/
static int
hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
{
#define MAX_PCIE_CAPABILITY 48
uint16_t status;
uint8_t pos;
uint8_t id;
int ttl;
int ret;
ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
if (ret < 0) {
PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
return 0;
}
if (!(status & PCI_STATUS_CAP_LIST))
return 0;
ttl = MAX_PCIE_CAPABILITY;
ret = rte_pci_read_config(device, &pos, sizeof(pos),
PCI_CAPABILITY_LIST);
if (ret < 0) {
PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
PCI_CAPABILITY_LIST);
return 0;
}
while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
ret = rte_pci_read_config(device, &id, sizeof(id),
(pos + PCI_CAP_LIST_ID));
if (ret < 0) {
PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
(pos + PCI_CAP_LIST_ID));
break;
}
if (id == 0xFF)
break;
if (id == cap)
return (int)pos;
ret = rte_pci_read_config(device, &pos, sizeof(pos),
(pos + PCI_CAP_LIST_NEXT));
if (ret < 0) {
PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
(pos + PCI_CAP_LIST_NEXT));
break;
}
}
return 0;
}
static int
hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
{
uint16_t control;
int pos;
int ret;
pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
if (pos) {
ret = rte_pci_read_config(device, &control, sizeof(control),
(pos + PCI_MSIX_FLAGS));
if (ret < 0) {
PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
(pos + PCI_MSIX_FLAGS));
return -ENXIO;
}
if (op)
control |= PCI_MSIX_FLAGS_ENABLE;
else
control &= ~PCI_MSIX_FLAGS_ENABLE;
ret = rte_pci_write_config(device, &control, sizeof(control),
(pos + PCI_MSIX_FLAGS));
if (ret < 0) {
PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
(pos + PCI_MSIX_FLAGS));
return -ENXIO;
}
return 0;
}
return -ENXIO;
}
static int
hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
{
/* mac address was checked by upper level interface */
char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
int ret;
ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
RTE_ETHER_ADDR_LEN, false, NULL, 0);
if (ret) {
hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
mac_addr);
hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
mac_str, ret);
}
return ret;
}
static int
hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
{
/* mac address was checked by upper level interface */
char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
int ret;
ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
HNS3_MBX_MAC_VLAN_UC_REMOVE,
mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
false, NULL, 0);
if (ret) {
hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
mac_addr);
hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
mac_str, ret);
}
return ret;
}
static int
hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
struct rte_ether_addr *mac_addr)
{
#define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_ether_addr *old_addr;
uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
int ret;
/*
* It has been guaranteed that input parameter named mac_addr is valid
* address in the rte layer of DPDK framework.
*/
old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
rte_spinlock_lock(&hw->lock);
memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
RTE_ETHER_ADDR_LEN);
ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
if (ret) {
/*
* The hns3 VF PMD depends on the hns3 PF kernel ethdev
* driver. When user has configured a MAC address for VF device
* by "ip link set ..." command based on the PF device, the hns3
* PF kernel ethdev driver does not allow VF driver to request
* reconfiguring a different default MAC address, and return
* -EPREM to VF driver through mailbox.
*/
if (ret == -EPERM) {
hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
old_addr);
hns3_warn(hw, "Has permanent mac addr(%s) for vf",
mac_str);
} else {
hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
mac_addr);
hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
mac_str, ret);
}
}
rte_ether_addr_copy(mac_addr,
(struct rte_ether_addr *)hw->mac.mac_addr);
rte_spinlock_unlock(&hw->lock);
return ret;
}
static int
hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
struct rte_ether_addr *mac_addr)
{
char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
int ret;
ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
HNS3_MBX_MAC_VLAN_MC_ADD,
mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
NULL, 0);
if (ret) {
hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
mac_addr);
hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
mac_str, ret);
}
return ret;
}
static int
hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
struct rte_ether_addr *mac_addr)
{
char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
int ret;
ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
HNS3_MBX_MAC_VLAN_MC_REMOVE,
mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
NULL, 0);
if (ret) {
hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
mac_addr);
hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
mac_str, ret);
}
return ret;
}
static int
hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
bool en_uc_pmc, bool en_mc_pmc)
{
struct hns3_mbx_vf_to_pf_cmd *req;
struct hns3_cmd_desc desc;
int ret;
req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
/*
* The hns3 VF PMD depends on the hns3 PF kernel ethdev driver,
* so there are some features for promiscuous/allmulticast mode in hns3
* VF PMD as below:
* 1. The promiscuous/allmulticast mode can be configured successfully
* only based on the trusted VF device. If based on the non trusted
* VF device, configuring promiscuous/allmulticast mode will fail.
* The hns3 VF device can be configured as trusted device by hns3 PF
* kernel ethdev driver on the host by the following command:
* "ip link set <eth num> vf <vf id> turst on"
* 2. After the promiscuous mode is configured successfully, hns3 VF PMD
* can receive the ingress and outgoing traffic. This includes
* all the ingress packets, all the packets sent from the PF and
* other VFs on the same physical port.
* 3. Note: Because of the hardware constraints, By default vlan filter
* is enabled and couldn't be turned off based on VF device, so vlan
* filter is still effective even in promiscuous mode. If upper
* applications don't call rte_eth_dev_vlan_filter API function to
* set vlan based on VF device, hns3 VF PMD will can't receive
* the packets with vlan tag in promiscuous mode.
*/
hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
req->msg[1] = en_bc_pmc ? 1 : 0;
req->msg[2] = en_uc_pmc ? 1 : 0;
req->msg[3] = en_mc_pmc ? 1 : 0;
req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
ret = hns3_cmd_send(hw, &desc, 1);
if (ret)
hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
return ret;
}
static int
hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
{
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
int ret;
ret = hns3vf_set_promisc_mode(hw, true, true, true);
if (ret)
hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
ret);
return ret;
}
static int
hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
{
bool allmulti = dev->data->all_multicast ? true : false;
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
int ret;
ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
if (ret)
hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
ret);
return ret;
}
static int
hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
{
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
int ret;
if (dev->data->promiscuous)
return 0;
ret = hns3vf_set_promisc_mode(hw, true, false, true);
if (ret)
hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
ret);
return ret;
}
static int
hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
{
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
int ret;
if (dev->data->promiscuous)
return 0;
ret = hns3vf_set_promisc_mode(hw, true, false, false);
if (ret)
hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
ret);
return ret;
}
static int
hns3vf_restore_promisc(struct hns3_adapter *hns)
{
struct hns3_hw *hw = &hns->hw;
bool allmulti = hw->data->all_multicast ? true : false;
if (hw->data->promiscuous)
return hns3vf_set_promisc_mode(hw, true, true, true);
return hns3vf_set_promisc_mode(hw, true, false, allmulti);
}
static int
hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id,
bool mmap, enum hns3_ring_type queue_type,
uint16_t queue_id)
{
struct hns3_vf_bind_vector_msg bind_msg;
const char *op_str;
uint16_t code;
int ret;
memset(&bind_msg, 0, sizeof(bind_msg));
code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
HNS3_MBX_UNMAP_RING_TO_VECTOR;
bind_msg.vector_id = (uint8_t)vector_id;
if (queue_type == HNS3_RING_TYPE_RX)
bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
else
bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
bind_msg.param[0].ring_type = queue_type;
bind_msg.ring_num = 1;
bind_msg.param[0].tqp_index = queue_id;
op_str = mmap ? "Map" : "Unmap";
ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
sizeof(bind_msg), false, NULL, 0);
if (ret)
hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
op_str, queue_id, bind_msg.vector_id, ret);
return ret;
}
static int
hns3vf_dev_configure(struct rte_eth_dev *dev)
{
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
struct rte_eth_conf *conf = &dev->data->dev_conf;
enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
uint16_t nb_rx_q = dev->data->nb_rx_queues;
uint16_t nb_tx_q = dev->data->nb_tx_queues;
struct rte_eth_rss_conf rss_conf;
bool gro_en;
int ret;
hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
/*
* Some versions of hardware network engine does not support
* individually enable/disable/reset the Tx or Rx queue. These devices
* must enable/disable/reset Tx and Rx queues at the same time. When the
* numbers of Tx queues allocated by upper applications are not equal to
* the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
* to adjust numbers of Tx/Rx queues. otherwise, network engine can not
* work as usual. But these fake queues are imperceptible, and can not
* be used by upper applications.
*/
ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
if (ret) {
hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
hw->cfg_max_queues = 0;
return ret;
}
hw->adapter_state = HNS3_NIC_CONFIGURING;
if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
hns3_err(hw, "setting link speed/duplex not supported");
ret = -EINVAL;
goto cfg_err;
}
/* When RSS is not configured, redirect the packet queue 0 */
if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
rss_conf = conf->rx_adv_conf.rss_conf;
ret = hns3_dev_rss_hash_update(dev, &rss_conf);
if (ret)
goto cfg_err;
}
ret = hns3vf_dev_mtu_set(dev, conf->rxmode.mtu);
if (ret != 0)
goto cfg_err;
ret = hns3vf_dev_configure_vlan(dev);
if (ret)
goto cfg_err;
/* config hardware GRO */
gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
ret = hns3_config_gro(hw, gro_en);
if (ret)
goto cfg_err;
hns3_init_rx_ptype_tble(dev);
hw->adapter_state = HNS3_NIC_CONFIGURED;
return 0;
cfg_err:
hw->cfg_max_queues = 0;
(void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
hw->adapter_state = HNS3_NIC_INITIALIZED;
return ret;
}
static int
hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
{
int ret;
ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
sizeof(mtu), true, NULL, 0);
if (ret)
hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
return ret;
}
static int
hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
{
struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
int ret;
/*
* The hns3 PF/VF devices on the same port share the hardware MTU
* configuration. Currently, we send mailbox to inform hns3 PF kernel
* ethdev driver to finish hardware MTU configuration in hns3 VF PMD,
* there is no need to stop the port for hns3 VF device, and the
* MTU value issued by hns3 VF PMD must be less than or equal to
* PF's MTU.
*/
if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
hns3_err(hw, "Failed to set mtu during resetting");
return -EIO;
}
/*
* when Rx of scattered packets is off, we have some possibility of
* using vector Rx process function or simple Rx functions in hns3 PMD.
* If the input MTU is increased and the maximum length of
* received packets is greater than the length of a buffer for Rx
* packet, the hardware network engine needs to use multiple BDs and
* buffers to store these packets. This will cause problems when still
* using vector Rx process function or simple Rx function to receiving
* packets. So, when Rx of scattered packets is off and device is
* started, it is not permitted to increase MTU so that the maximum
* length of Rx packets is greater than Rx buffer length.
*/
if (dev->data->dev_started && !dev->data->scattered_rx &&
frame_size > hw->rx_buf_len) {
hns3_err(hw, "failed to set mtu because current is "
"not scattered rx mode");
return -EOPNOTSUPP;
}
rte_spinlock_lock(&hw->lock);
ret = hns3vf_config_mtu(hw, mtu);
if (ret) {
rte_spinlock_unlock(&hw->lock);
return ret;
}
rte_spinlock_unlock(&hw->lock);
return 0;
}
static void
hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
{
hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
}
static void
hns3vf_disable_irq0(struct hns3_hw *hw)
{
hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
}
static void
hns3vf_enable_irq0(struct hns3_hw *hw)
{
hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
}
static enum hns3vf_evt_cause
hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
{
struct hns3_hw *hw = &hns->hw;
enum hns3vf_evt_cause ret;
uint32_t cmdq_stat_reg;
uint32_t rst_ing_reg;
uint32_t val;
/* Fetch the events from their corresponding regs */
cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
val = hns3_read_dev(hw, HNS3_VF_RST_ING);
hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
if (clearval) {
hw->reset.stats.global_cnt++;
hns3_warn(hw, "Global reset detected, clear reset status");
} else {
hns3_schedule_delayed_reset(hns);
hns3_warn(hw, "Global reset detected, don't clear reset status");
}
ret = HNS3VF_VECTOR0_EVENT_RST;
goto out;
}
/* Check for vector0 mailbox(=CMDQ RX) event source */
if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
ret = HNS3VF_VECTOR0_EVENT_MBX;
goto out;
}
val = 0;
ret = HNS3VF_VECTOR0_EVENT_OTHER;
out:
if (clearval)
*clearval = val;
return ret;
}
static void
hns3vf_interrupt_handler(void *param)
{
struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
enum hns3vf_evt_cause event_cause;
uint32_t clearval;
/* Disable interrupt */
hns3vf_disable_irq0(hw);
/* Read out interrupt causes */
event_cause = hns3vf_check_event_cause(hns, &clearval);
/* Clear interrupt causes */
hns3vf_clear_event_cause(hw, clearval);
switch (event_cause) {
case HNS3VF_VECTOR0_EVENT_RST:
hns3_schedule_reset(hns);
break;
case HNS3VF_VECTOR0_EVENT_MBX:
hns3_dev_handle_mbx_msg(hw);
break;
default:
break;
}
/* Enable interrupt */
hns3vf_enable_irq0(hw);
}
static void
hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
{
hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
hw->rss_key_size = HNS3_RSS_KEY_SIZE;
hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
}
static void
hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
{
struct hns3_dev_specs_0_cmd *req0;
req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
}
static int
hns3vf_check_dev_specifications(struct hns3_hw *hw)
{
if (hw->rss_ind_tbl_size == 0 ||
hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
hns3_warn(hw, "the size of hash lookup table configured (%u)"
" exceeds the maximum(%u)", hw->rss_ind_tbl_size,
HNS3_RSS_IND_TBL_SIZE_MAX);
return -EINVAL;
}
return 0;
}
static int
hns3vf_query_dev_specifications(struct hns3_hw *hw)
{
struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
int ret;
int i;
for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
true);
desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
}
hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
if (ret)
return ret;
hns3vf_parse_dev_specifications(hw, desc);
return hns3vf_check_dev_specifications(hw);
}
void
hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
{
uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
__atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
__ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
}
static void
hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
{
#define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS 500
struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
__atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
__ATOMIC_RELEASE);
(void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
NULL, 0);
while (remain_ms > 0) {
rte_delay_ms(HNS3_POLL_RESPONE_MS);
if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
break;
remain_ms--;
}
/*
* When exit above loop, the pf_push_lsc_cap could be one of the three
* state: unknown (means pf not ack), not_supported, supported.
* Here config it as 'not_supported' when it's 'unknown' state.
*/
__atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
__ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
hns3_info(hw, "detect PF support push link status change!");
} else {
/*
* Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
* declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
* the RTE_ETH_DEV_INTR_LSC capability.
*/
dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
}
}
static int
hns3vf_get_capability(struct hns3_hw *hw)
{
struct rte_pci_device *pci_dev;
struct rte_eth_dev *eth_dev;
uint8_t revision;
int ret;
eth_dev = &rte_eth_devices[hw->data->port_id];
pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
/* Get PCI revision id */
ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
HNS3_PCI_REVISION_ID);
if (ret != HNS3_PCI_REVISION_ID_LEN) {
PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
ret);
return -EIO;
}
hw->revision = revision;
if (revision < PCI_REVISION_ID_HIP09_A) {
hns3vf_set_default_dev_specifications(hw);
hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
hw->rss_info.ipv6_sctp_offload_supported = false;
hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
return 0;
}
ret = hns3vf_query_dev_specifications(hw);
if (ret) {
PMD_INIT_LOG(ERR,
"failed to query dev specifications, ret = %d",
ret);
return ret;
}
hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
hw->rss_info.ipv6_sctp_offload_supported = true;
hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
return 0;
}
static int
hns3vf_check_tqp_info(struct hns3_hw *hw)
{
if (hw->tqps_num == 0) {
PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
return -EINVAL;
}
if (hw->rss_size_max == 0) {
PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
return -EINVAL;
}
hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
return 0;
}
static int
hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
{
uint8_t resp_msg;
int ret;
ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
true, &resp_msg, sizeof(resp_msg));
if (ret) {
if (ret == -ETIME) {
/*
* Getting current port based VLAN state from PF driver
* will not affect VF driver's basic function. Because
* the VF driver relies on hns3 PF kernel ether driver,
* to avoid introducing compatibility issues with older
* version of PF driver, no failure will be returned
* when the return value is ETIME. This return value has
* the following scenarios:
* 1) Firmware didn't return the results in time
* 2) the result return by firmware is timeout
* 3) the older version of kernel side PF driver does
* not support this mailbox message.
* For scenarios 1 and 2, it is most likely that a
* hardware error has occurred, or a hardware reset has
* occurred. In this case, these errors will be caught
* by other functions.
*/
PMD_INIT_LOG(WARNING,
"failed to get PVID state for timeout, maybe "
"kernel side PF driver doesn't support this "
"mailbox message, or firmware didn't respond.");
resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
} else {
PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
" ret = %d", ret);
return ret;
}
}
hw->port_base_vlan_cfg.state = resp_msg ?
HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
return 0;
}
static int
hns3vf_get_queue_info(struct hns3_hw *hw)
{
#define HNS3VF_TQPS_RSS_INFO_LEN 6
uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
int ret;
ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
if (ret) {
PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
return ret;
}
memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
return hns3vf_check_tqp_info(hw);
}
static int
hns3vf_get_queue_depth(struct hns3_hw *hw)
{
#define HNS3VF_TQPS_DEPTH_INFO_LEN 4
uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
int ret;
ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
if (ret) {
PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
ret);
return ret;
}
memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
return 0;
}
static void
hns3vf_update_caps(struct hns3_hw *hw, uint32_t caps)
{
if (hns3_get_bit(caps, HNS3VF_CAPS_VLAN_FLT_MOD_B))
hns3_set_bit(hw->capability,
HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, 1);
}
static int
hns3vf_get_num_tc(struct hns3_hw *hw)
{
uint8_t num_tc = 0;
uint32_t i;
for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
if (hw->hw_tc_map & BIT(i))
num_tc++;
}
return num_tc;
}
static int
hns3vf_get_basic_info(struct hns3_hw *hw)
{
uint8_t resp_msg[HNS3_MBX_MAX_RESP_DATA_SIZE];
struct hns3_basic_info *basic_info;
int ret;
ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_BASIC_INFO, 0, NULL, 0,
true, resp_msg, sizeof(resp_msg));
if (ret) {
hns3_err(hw, "failed to get basic info from PF, ret = %d.",
ret);
return ret;
}
basic_info = (struct hns3_basic_info *)resp_msg;