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mlx5_rxq.c
3010 lines (2854 loc) · 81.5 KB
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mlx5_rxq.c
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/* SPDX-License-Identifier: BSD-3-Clause
* Copyright 2015 6WIND S.A.
* Copyright 2015 Mellanox Technologies, Ltd
*/
#include <stddef.h>
#include <errno.h>
#include <string.h>
#include <stdint.h>
#include <fcntl.h>
#include <sys/queue.h>
#include <rte_mbuf.h>
#include <rte_malloc.h>
#include <ethdev_driver.h>
#include <rte_common.h>
#include <rte_interrupts.h>
#include <rte_debug.h>
#include <rte_io.h>
#include <rte_eal_paging.h>
#include <mlx5_glue.h>
#include <mlx5_malloc.h>
#include <mlx5_common.h>
#include <mlx5_common_mr.h>
#include "mlx5_defs.h"
#include "mlx5.h"
#include "mlx5_rx.h"
#include "mlx5_utils.h"
#include "mlx5_autoconf.h"
#include "mlx5_devx.h"
/* Default RSS hash key also used for ConnectX-3. */
uint8_t rss_hash_default_key[] = {
0x2c, 0xc6, 0x81, 0xd1,
0x5b, 0xdb, 0xf4, 0xf7,
0xfc, 0xa2, 0x83, 0x19,
0xdb, 0x1a, 0x3e, 0x94,
0x6b, 0x9e, 0x38, 0xd9,
0x2c, 0x9c, 0x03, 0xd1,
0xad, 0x99, 0x44, 0xa7,
0xd9, 0x56, 0x3d, 0x59,
0x06, 0x3c, 0x25, 0xf3,
0xfc, 0x1f, 0xdc, 0x2a,
};
/* Length of the default RSS hash key. */
static_assert(MLX5_RSS_HASH_KEY_LEN ==
(unsigned int)sizeof(rss_hash_default_key),
"wrong RSS default key size.");
/**
* Calculate the number of CQEs in CQ for the Rx queue.
*
* @param rxq_data
* Pointer to receive queue structure.
*
* @return
* Number of CQEs in CQ.
*/
unsigned int
mlx5_rxq_cqe_num(struct mlx5_rxq_data *rxq_data)
{
unsigned int cqe_n;
unsigned int wqe_n = 1 << rxq_data->elts_n;
if (mlx5_rxq_mprq_enabled(rxq_data))
cqe_n = wqe_n * RTE_BIT32(rxq_data->log_strd_num) - 1;
else
cqe_n = wqe_n - 1;
return cqe_n;
}
/**
* Allocate RX queue elements for Multi-Packet RQ.
*
* @param rxq_ctrl
* Pointer to RX queue structure.
*
* @return
* 0 on success, a negative errno value otherwise and rte_errno is set.
*/
static int
rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
{
struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
unsigned int wqe_n = 1 << rxq->elts_n;
unsigned int i;
int err;
/* Iterate on segments. */
for (i = 0; i <= wqe_n; ++i) {
struct mlx5_mprq_buf *buf;
if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
rte_errno = ENOMEM;
goto error;
}
if (i < wqe_n)
(*rxq->mprq_bufs)[i] = buf;
else
rxq->mprq_repl = buf;
}
DRV_LOG(DEBUG,
"port %u MPRQ queue %u allocated and configured %u segments",
rxq->port_id, rxq->idx, wqe_n);
return 0;
error:
err = rte_errno; /* Save rte_errno before cleanup. */
wqe_n = i;
for (i = 0; (i != wqe_n); ++i) {
if ((*rxq->mprq_bufs)[i] != NULL)
rte_mempool_put(rxq->mprq_mp,
(*rxq->mprq_bufs)[i]);
(*rxq->mprq_bufs)[i] = NULL;
}
DRV_LOG(DEBUG, "port %u MPRQ queue %u failed, freed everything",
rxq->port_id, rxq->idx);
rte_errno = err; /* Restore rte_errno. */
return -rte_errno;
}
/**
* Allocate RX queue elements for Single-Packet RQ.
*
* @param rxq_ctrl
* Pointer to RX queue structure.
*
* @return
* 0 on success, negative errno value on failure.
*/
static int
rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
{
const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
unsigned int elts_n = mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
RTE_BIT32(rxq_ctrl->rxq.elts_n) *
RTE_BIT32(rxq_ctrl->rxq.log_strd_num) :
RTE_BIT32(rxq_ctrl->rxq.elts_n);
bool has_vec_support = mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0;
unsigned int i;
int err;
/* Iterate on segments. */
for (i = 0; (i != elts_n); ++i) {
struct mlx5_eth_rxseg *seg = &rxq_ctrl->rxq.rxseg[i % sges_n];
struct rte_mbuf *buf;
buf = rte_pktmbuf_alloc(seg->mp);
if (buf == NULL) {
if (rxq_ctrl->share_group == 0)
DRV_LOG(ERR, "port %u queue %u empty mbuf pool",
RXQ_PORT_ID(rxq_ctrl),
rxq_ctrl->rxq.idx);
else
DRV_LOG(ERR, "share group %u queue %u empty mbuf pool",
rxq_ctrl->share_group,
rxq_ctrl->share_qid);
rte_errno = ENOMEM;
goto error;
}
/* Only vectored Rx routines rely on headroom size. */
MLX5_ASSERT(!has_vec_support ||
DATA_OFF(buf) >= RTE_PKTMBUF_HEADROOM);
/* Buffer is supposed to be empty. */
MLX5_ASSERT(rte_pktmbuf_data_len(buf) == 0);
MLX5_ASSERT(rte_pktmbuf_pkt_len(buf) == 0);
MLX5_ASSERT(!buf->next);
SET_DATA_OFF(buf, seg->offset);
PORT(buf) = rxq_ctrl->rxq.port_id;
DATA_LEN(buf) = seg->length;
PKT_LEN(buf) = seg->length;
NB_SEGS(buf) = 1;
(*rxq_ctrl->rxq.elts)[i] = buf;
}
/* If Rx vector is activated. */
if (has_vec_support) {
struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
struct rte_pktmbuf_pool_private *priv =
(struct rte_pktmbuf_pool_private *)
rte_mempool_get_priv(rxq_ctrl->rxq.mp);
int j;
/* Initialize default rearm_data for vPMD. */
mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
rte_mbuf_refcnt_set(mbuf_init, 1);
mbuf_init->nb_segs = 1;
/* For shared queues port is provided in CQE */
mbuf_init->port = rxq->shared ? 0 : rxq->port_id;
if (priv->flags & RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF)
mbuf_init->ol_flags = RTE_MBUF_F_EXTERNAL;
/*
* prevent compiler reordering:
* rearm_data covers previous fields.
*/
rte_compiler_barrier();
rxq->mbuf_initializer =
*(rte_xmm_t *)&mbuf_init->rearm_data;
/* Padding with a fake mbuf for vectorized Rx. */
for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
(*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
}
if (rxq_ctrl->share_group == 0)
DRV_LOG(DEBUG,
"port %u SPRQ queue %u allocated and configured %u segments (max %u packets)",
RXQ_PORT_ID(rxq_ctrl), rxq_ctrl->rxq.idx, elts_n,
elts_n / (1 << rxq_ctrl->rxq.sges_n));
else
DRV_LOG(DEBUG,
"share group %u SPRQ queue %u allocated and configured %u segments (max %u packets)",
rxq_ctrl->share_group, rxq_ctrl->share_qid, elts_n,
elts_n / (1 << rxq_ctrl->rxq.sges_n));
return 0;
error:
err = rte_errno; /* Save rte_errno before cleanup. */
elts_n = i;
for (i = 0; (i != elts_n); ++i) {
if ((*rxq_ctrl->rxq.elts)[i] != NULL)
rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
(*rxq_ctrl->rxq.elts)[i] = NULL;
}
if (rxq_ctrl->share_group == 0)
DRV_LOG(DEBUG, "port %u SPRQ queue %u failed, freed everything",
RXQ_PORT_ID(rxq_ctrl), rxq_ctrl->rxq.idx);
else
DRV_LOG(DEBUG, "share group %u SPRQ queue %u failed, freed everything",
rxq_ctrl->share_group, rxq_ctrl->share_qid);
rte_errno = err; /* Restore rte_errno. */
return -rte_errno;
}
/**
* Allocate RX queue elements.
*
* @param rxq_ctrl
* Pointer to RX queue structure.
*
* @return
* 0 on success, negative errno value on failure.
*/
int
rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
{
int ret = 0;
/**
* For MPRQ we need to allocate both MPRQ buffers
* for WQEs and simple mbufs for vector processing.
*/
if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
ret = rxq_alloc_elts_mprq(rxq_ctrl);
if (ret == 0)
ret = rxq_alloc_elts_sprq(rxq_ctrl);
return ret;
}
/**
* Free RX queue elements for Multi-Packet RQ.
*
* @param rxq_ctrl
* Pointer to RX queue structure.
*/
static void
rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
{
struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
uint16_t i;
DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing %d WRs",
rxq->port_id, rxq->idx, (1u << rxq->elts_n));
if (rxq->mprq_bufs == NULL)
return;
for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
if ((*rxq->mprq_bufs)[i] != NULL)
mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
(*rxq->mprq_bufs)[i] = NULL;
}
if (rxq->mprq_repl != NULL) {
mlx5_mprq_buf_free(rxq->mprq_repl);
rxq->mprq_repl = NULL;
}
}
/**
* Free RX queue elements for Single-Packet RQ.
*
* @param rxq_ctrl
* Pointer to RX queue structure.
*/
static void
rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
{
struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
const uint16_t q_n = mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
RTE_BIT32(rxq->elts_n) * RTE_BIT32(rxq->log_strd_num) :
RTE_BIT32(rxq->elts_n);
const uint16_t q_mask = q_n - 1;
uint16_t elts_ci = mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
rxq->elts_ci : rxq->rq_ci;
uint16_t used = q_n - (elts_ci - rxq->rq_pi);
uint16_t i;
if (rxq_ctrl->share_group == 0)
DRV_LOG(DEBUG, "port %u Rx queue %u freeing %d WRs",
RXQ_PORT_ID(rxq_ctrl), rxq->idx, q_n);
else
DRV_LOG(DEBUG, "share group %u Rx queue %u freeing %d WRs",
rxq_ctrl->share_group, rxq_ctrl->share_qid, q_n);
if (rxq->elts == NULL)
return;
/**
* Some mbuf in the Ring belongs to the application.
* They cannot be freed.
*/
if (mlx5_rxq_check_vec_support(rxq) > 0) {
for (i = 0; i < used; ++i)
(*rxq->elts)[(elts_ci + i) & q_mask] = NULL;
rxq->rq_pi = elts_ci;
}
for (i = 0; i != q_n; ++i) {
if ((*rxq->elts)[i] != NULL)
rte_pktmbuf_free_seg((*rxq->elts)[i]);
(*rxq->elts)[i] = NULL;
}
}
/**
* Free RX queue elements.
*
* @param rxq_ctrl
* Pointer to RX queue structure.
*/
static void
rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
{
/*
* For MPRQ we need to allocate both MPRQ buffers
* for WQEs and simple mbufs for vector processing.
*/
if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
rxq_free_elts_mprq(rxq_ctrl);
rxq_free_elts_sprq(rxq_ctrl);
}
/**
* Returns the per-queue supported offloads.
*
* @param dev
* Pointer to Ethernet device.
*
* @return
* Supported Rx offloads.
*/
uint64_t
mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
{
struct mlx5_priv *priv = dev->data->dev_private;
struct mlx5_dev_config *config = &priv->config;
uint64_t offloads = (RTE_ETH_RX_OFFLOAD_SCATTER |
RTE_ETH_RX_OFFLOAD_TIMESTAMP |
RTE_ETH_RX_OFFLOAD_RSS_HASH);
if (!config->mprq.enabled)
offloads |= RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT;
if (config->hw_fcs_strip)
offloads |= RTE_ETH_RX_OFFLOAD_KEEP_CRC;
if (config->hw_csum)
offloads |= (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
RTE_ETH_RX_OFFLOAD_TCP_CKSUM);
if (config->hw_vlan_strip)
offloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
if (MLX5_LRO_SUPPORTED(dev))
offloads |= RTE_ETH_RX_OFFLOAD_TCP_LRO;
return offloads;
}
/**
* Returns the per-port supported offloads.
*
* @return
* Supported Rx offloads.
*/
uint64_t
mlx5_get_rx_port_offloads(void)
{
uint64_t offloads = RTE_ETH_RX_OFFLOAD_VLAN_FILTER;
return offloads;
}
/**
* Verify if the queue can be released.
*
* @param dev
* Pointer to Ethernet device.
* @param idx
* RX queue index.
*
* @return
* 1 if the queue can be released
* 0 if the queue can not be released, there are references to it.
* Negative errno and rte_errno is set if queue doesn't exist.
*/
static int
mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
{
struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx);
if (rxq == NULL) {
rte_errno = EINVAL;
return -rte_errno;
}
return (__atomic_load_n(&rxq->refcnt, __ATOMIC_RELAXED) == 1);
}
/* Fetches and drops all SW-owned and error CQEs to synchronize CQ. */
static void
rxq_sync_cq(struct mlx5_rxq_data *rxq)
{
const uint16_t cqe_n = 1 << rxq->cqe_n;
const uint16_t cqe_mask = cqe_n - 1;
volatile struct mlx5_cqe *cqe;
int ret, i;
i = cqe_n;
do {
cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask];
ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
if (ret == MLX5_CQE_STATUS_HW_OWN)
break;
if (ret == MLX5_CQE_STATUS_ERR) {
rxq->cq_ci++;
continue;
}
MLX5_ASSERT(ret == MLX5_CQE_STATUS_SW_OWN);
if (MLX5_CQE_FORMAT(cqe->op_own) != MLX5_COMPRESSED) {
rxq->cq_ci++;
continue;
}
/* Compute the next non compressed CQE. */
rxq->cq_ci += rte_be_to_cpu_32(cqe->byte_cnt);
} while (--i);
/* Move all CQEs to HW ownership, including possible MiniCQEs. */
for (i = 0; i < cqe_n; i++) {
cqe = &(*rxq->cqes)[i];
cqe->op_own = MLX5_CQE_INVALIDATE;
}
/* Resync CQE and WQE (WQ in RESET state). */
rte_io_wmb();
*rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
rte_io_wmb();
*rxq->rq_db = rte_cpu_to_be_32(0);
rte_io_wmb();
}
/**
* Rx queue stop. Device queue goes to the RESET state,
* all involved mbufs are freed from WQ.
*
* @param dev
* Pointer to Ethernet device structure.
* @param idx
* RX queue index.
*
* @return
* 0 on success, a negative errno value otherwise and rte_errno is set.
*/
int
mlx5_rx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t idx)
{
struct mlx5_priv *priv = dev->data->dev_private;
struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx);
struct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl;
int ret;
MLX5_ASSERT(rxq != NULL && rxq_ctrl != NULL);
MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
ret = priv->obj_ops.rxq_obj_modify(rxq, MLX5_RXQ_MOD_RDY2RST);
if (ret) {
DRV_LOG(ERR, "Cannot change Rx WQ state to RESET: %s",
strerror(errno));
rte_errno = errno;
return ret;
}
/* Remove all processes CQEs. */
rxq_sync_cq(&rxq_ctrl->rxq);
/* Free all involved mbufs. */
rxq_free_elts(rxq_ctrl);
/* Set the actual queue state. */
dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED;
return 0;
}
/**
* Rx queue stop. Device queue goes to the RESET state,
* all involved mbufs are freed from WQ.
*
* @param dev
* Pointer to Ethernet device structure.
* @param idx
* RX queue index.
*
* @return
* 0 on success, a negative errno value otherwise and rte_errno is set.
*/
int
mlx5_rx_queue_stop(struct rte_eth_dev *dev, uint16_t idx)
{
eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
int ret;
if (rte_eth_dev_is_rx_hairpin_queue(dev, idx)) {
DRV_LOG(ERR, "Hairpin queue can't be stopped");
rte_errno = EINVAL;
return -EINVAL;
}
if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STOPPED)
return 0;
/*
* Vectorized Rx burst requires the CQ and RQ indices
* synchronized, that might be broken on RQ restart
* and cause Rx malfunction, so queue stopping is
* not supported if vectorized Rx burst is engaged.
* The routine pointer depends on the process
* type, should perform check there.
*/
if (pkt_burst == mlx5_rx_burst_vec) {
DRV_LOG(ERR, "Rx queue stop is not supported "
"for vectorized Rx");
rte_errno = EINVAL;
return -EINVAL;
}
if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
ret = mlx5_mp_os_req_queue_control(dev, idx,
MLX5_MP_REQ_QUEUE_RX_STOP);
} else {
ret = mlx5_rx_queue_stop_primary(dev, idx);
}
return ret;
}
/**
* Rx queue start. Device queue goes to the ready state,
* all required mbufs are allocated and WQ is replenished.
*
* @param dev
* Pointer to Ethernet device structure.
* @param idx
* RX queue index.
*
* @return
* 0 on success, a negative errno value otherwise and rte_errno is set.
*/
int
mlx5_rx_queue_start_primary(struct rte_eth_dev *dev, uint16_t idx)
{
struct mlx5_priv *priv = dev->data->dev_private;
struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx);
struct mlx5_rxq_data *rxq_data = &rxq->ctrl->rxq;
int ret;
MLX5_ASSERT(rxq != NULL && rxq->ctrl != NULL);
MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
/* Allocate needed buffers. */
ret = rxq_alloc_elts(rxq->ctrl);
if (ret) {
DRV_LOG(ERR, "Cannot reallocate buffers for Rx WQ");
rte_errno = errno;
return ret;
}
rte_io_wmb();
*rxq_data->cq_db = rte_cpu_to_be_32(rxq_data->cq_ci);
rte_io_wmb();
/* Reset RQ consumer before moving queue to READY state. */
*rxq_data->rq_db = rte_cpu_to_be_32(0);
rte_io_wmb();
ret = priv->obj_ops.rxq_obj_modify(rxq, MLX5_RXQ_MOD_RST2RDY);
if (ret) {
DRV_LOG(ERR, "Cannot change Rx WQ state to READY: %s",
strerror(errno));
rte_errno = errno;
return ret;
}
/* Reinitialize RQ - set WQEs. */
mlx5_rxq_initialize(rxq_data);
rxq_data->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
/* Set actual queue state. */
dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
return 0;
}
/**
* Rx queue start. Device queue goes to the ready state,
* all required mbufs are allocated and WQ is replenished.
*
* @param dev
* Pointer to Ethernet device structure.
* @param idx
* RX queue index.
*
* @return
* 0 on success, a negative errno value otherwise and rte_errno is set.
*/
int
mlx5_rx_queue_start(struct rte_eth_dev *dev, uint16_t idx)
{
int ret;
if (rte_eth_dev_is_rx_hairpin_queue(dev, idx)) {
DRV_LOG(ERR, "Hairpin queue can't be started");
rte_errno = EINVAL;
return -EINVAL;
}
if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STARTED)
return 0;
if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
ret = mlx5_mp_os_req_queue_control(dev, idx,
MLX5_MP_REQ_QUEUE_RX_START);
} else {
ret = mlx5_rx_queue_start_primary(dev, idx);
}
return ret;
}
/**
* Rx queue presetup checks.
*
* @param dev
* Pointer to Ethernet device structure.
* @param idx
* RX queue index.
* @param desc
* Number of descriptors to configure in queue.
* @param[out] rxq_ctrl
* Address of pointer to shared Rx queue control.
*
* @return
* 0 on success, a negative errno value otherwise and rte_errno is set.
*/
static int
mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc,
struct mlx5_rxq_ctrl **rxq_ctrl)
{
struct mlx5_priv *priv = dev->data->dev_private;
struct mlx5_rxq_priv *rxq;
bool empty;
if (!rte_is_power_of_2(*desc)) {
*desc = 1 << log2above(*desc);
DRV_LOG(WARNING,
"port %u increased number of descriptors in Rx queue %u"
" to the next power of two (%d)",
dev->data->port_id, idx, *desc);
}
DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
dev->data->port_id, idx, *desc);
if (idx >= priv->rxqs_n) {
DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
dev->data->port_id, idx, priv->rxqs_n);
rte_errno = EOVERFLOW;
return -rte_errno;
}
if (rxq_ctrl == NULL || *rxq_ctrl == NULL)
return 0;
if (!(*rxq_ctrl)->rxq.shared) {
if (!mlx5_rxq_releasable(dev, idx)) {
DRV_LOG(ERR, "port %u unable to release queue index %u",
dev->data->port_id, idx);
rte_errno = EBUSY;
return -rte_errno;
}
mlx5_rxq_release(dev, idx);
} else {
if ((*rxq_ctrl)->obj != NULL)
/* Some port using shared Rx queue has been started. */
return 0;
/* Release all owner RxQ to reconfigure Shared RxQ. */
do {
rxq = LIST_FIRST(&(*rxq_ctrl)->owners);
LIST_REMOVE(rxq, owner_entry);
empty = LIST_EMPTY(&(*rxq_ctrl)->owners);
mlx5_rxq_release(ETH_DEV(rxq->priv), rxq->idx);
} while (!empty);
*rxq_ctrl = NULL;
}
return 0;
}
/**
* Get the shared Rx queue object that matches group and queue index.
*
* @param dev
* Pointer to Ethernet device structure.
* @param group
* Shared RXQ group.
* @param share_qid
* Shared RX queue index.
*
* @return
* Shared RXQ object that matching, or NULL if not found.
*/
static struct mlx5_rxq_ctrl *
mlx5_shared_rxq_get(struct rte_eth_dev *dev, uint32_t group, uint16_t share_qid)
{
struct mlx5_rxq_ctrl *rxq_ctrl;
struct mlx5_priv *priv = dev->data->dev_private;
LIST_FOREACH(rxq_ctrl, &priv->sh->shared_rxqs, share_entry) {
if (rxq_ctrl->share_group == group &&
rxq_ctrl->share_qid == share_qid)
return rxq_ctrl;
}
return NULL;
}
/**
* Check whether requested Rx queue configuration matches shared RXQ.
*
* @param rxq_ctrl
* Pointer to shared RXQ.
* @param dev
* Pointer to Ethernet device structure.
* @param idx
* Queue index.
* @param desc
* Number of descriptors to configure in queue.
* @param socket
* NUMA socket on which memory must be allocated.
* @param[in] conf
* Thresholds parameters.
* @param mp
* Memory pool for buffer allocations.
*
* @return
* 0 on success, a negative errno value otherwise and rte_errno is set.
*/
static bool
mlx5_shared_rxq_match(struct mlx5_rxq_ctrl *rxq_ctrl, struct rte_eth_dev *dev,
uint16_t idx, uint16_t desc, unsigned int socket,
const struct rte_eth_rxconf *conf,
struct rte_mempool *mp)
{
struct mlx5_priv *spriv = LIST_FIRST(&rxq_ctrl->owners)->priv;
struct mlx5_priv *priv = dev->data->dev_private;
unsigned int i;
RTE_SET_USED(conf);
if (rxq_ctrl->socket != socket) {
DRV_LOG(ERR, "port %u queue index %u failed to join shared group: socket mismatch",
dev->data->port_id, idx);
return false;
}
if (rxq_ctrl->rxq.elts_n != log2above(desc)) {
DRV_LOG(ERR, "port %u queue index %u failed to join shared group: descriptor number mismatch",
dev->data->port_id, idx);
return false;
}
if (priv->mtu != spriv->mtu) {
DRV_LOG(ERR, "port %u queue index %u failed to join shared group: mtu mismatch",
dev->data->port_id, idx);
return false;
}
if (priv->dev_data->dev_conf.intr_conf.rxq !=
spriv->dev_data->dev_conf.intr_conf.rxq) {
DRV_LOG(ERR, "port %u queue index %u failed to join shared group: interrupt mismatch",
dev->data->port_id, idx);
return false;
}
if (mp != NULL && rxq_ctrl->rxq.mp != mp) {
DRV_LOG(ERR, "port %u queue index %u failed to join shared group: mempool mismatch",
dev->data->port_id, idx);
return false;
} else if (mp == NULL) {
if (conf->rx_nseg != rxq_ctrl->rxseg_n) {
DRV_LOG(ERR, "port %u queue index %u failed to join shared group: segment number mismatch",
dev->data->port_id, idx);
return false;
}
for (i = 0; i < conf->rx_nseg; i++) {
if (memcmp(&conf->rx_seg[i].split, &rxq_ctrl->rxseg[i],
sizeof(struct rte_eth_rxseg_split))) {
DRV_LOG(ERR, "port %u queue index %u failed to join shared group: segment %u configuration mismatch",
dev->data->port_id, idx, i);
return false;
}
}
}
if (priv->config.hw_padding != spriv->config.hw_padding) {
DRV_LOG(ERR, "port %u queue index %u failed to join shared group: padding mismatch",
dev->data->port_id, idx);
return false;
}
if (priv->config.cqe_comp != spriv->config.cqe_comp ||
(priv->config.cqe_comp &&
priv->config.cqe_comp_fmt != spriv->config.cqe_comp_fmt)) {
DRV_LOG(ERR, "port %u queue index %u failed to join shared group: CQE compression mismatch",
dev->data->port_id, idx);
return false;
}
return true;
}
/**
*
* @param dev
* Pointer to Ethernet device structure.
* @param idx
* RX queue index.
* @param desc
* Number of descriptors to configure in queue.
* @param socket
* NUMA socket on which memory must be allocated.
* @param[in] conf
* Thresholds parameters.
* @param mp
* Memory pool for buffer allocations.
*
* @return
* 0 on success, a negative errno value otherwise and rte_errno is set.
*/
int
mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
unsigned int socket, const struct rte_eth_rxconf *conf,
struct rte_mempool *mp)
{
struct mlx5_priv *priv = dev->data->dev_private;
struct mlx5_rxq_priv *rxq;
struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
struct rte_eth_rxseg_split *rx_seg =
(struct rte_eth_rxseg_split *)conf->rx_seg;
struct rte_eth_rxseg_split rx_single = {.mp = mp};
uint16_t n_seg = conf->rx_nseg;
int res;
uint64_t offloads = conf->offloads |
dev->data->dev_conf.rxmode.offloads;
if ((offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) &&
!priv->config.lro.supported) {
DRV_LOG(ERR,
"Port %u queue %u LRO is configured but not supported.",
dev->data->port_id, idx);
rte_errno = EINVAL;
return -rte_errno;
}
if (mp) {
/*
* The parameters should be checked on rte_eth_dev layer.
* If mp is specified it means the compatible configuration
* without buffer split feature tuning.
*/
rx_seg = &rx_single;
n_seg = 1;
}
if (n_seg > 1) {
/* The offloads should be checked on rte_eth_dev layer. */
MLX5_ASSERT(offloads & RTE_ETH_RX_OFFLOAD_SCATTER);
if (!(offloads & RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT)) {
DRV_LOG(ERR, "port %u queue index %u split "
"offload not configured",
dev->data->port_id, idx);
rte_errno = ENOSPC;
return -rte_errno;
}
MLX5_ASSERT(n_seg < MLX5_MAX_RXQ_NSEG);
}
if (conf->share_group > 0) {
if (!priv->config.hca_attr.mem_rq_rmp) {
DRV_LOG(ERR, "port %u queue index %u shared Rx queue not supported by fw",
dev->data->port_id, idx);
rte_errno = EINVAL;
return -rte_errno;
}
if (priv->obj_ops.rxq_obj_new != devx_obj_ops.rxq_obj_new) {
DRV_LOG(ERR, "port %u queue index %u shared Rx queue needs DevX api",
dev->data->port_id, idx);
rte_errno = EINVAL;
return -rte_errno;
}
if (conf->share_qid >= priv->rxqs_n) {
DRV_LOG(ERR, "port %u shared Rx queue index %u > number of Rx queues %u",
dev->data->port_id, conf->share_qid,
priv->rxqs_n);
rte_errno = EINVAL;
return -rte_errno;
}
if (priv->config.mprq.enabled) {
DRV_LOG(ERR, "port %u shared Rx queue index %u: not supported when MPRQ enabled",
dev->data->port_id, conf->share_qid);
rte_errno = EINVAL;
return -rte_errno;
}
/* Try to reuse shared RXQ. */
rxq_ctrl = mlx5_shared_rxq_get(dev, conf->share_group,
conf->share_qid);
res = mlx5_rx_queue_pre_setup(dev, idx, &desc, &rxq_ctrl);
if (res)
return res;
if (rxq_ctrl != NULL &&
!mlx5_shared_rxq_match(rxq_ctrl, dev, idx, desc, socket,
conf, mp)) {
rte_errno = EINVAL;
return -rte_errno;
}
} else {
res = mlx5_rx_queue_pre_setup(dev, idx, &desc, &rxq_ctrl);
if (res)
return res;
}
/* Allocate RXQ. */
rxq = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*rxq), 0,
SOCKET_ID_ANY);
if (!rxq) {
DRV_LOG(ERR, "port %u unable to allocate rx queue index %u private data",
dev->data->port_id, idx);
rte_errno = ENOMEM;
return -rte_errno;
}
rxq->priv = priv;
rxq->idx = idx;
(*priv->rxq_privs)[idx] = rxq;
if (rxq_ctrl != NULL) {
/* Join owner list. */
LIST_INSERT_HEAD(&rxq_ctrl->owners, rxq, owner_entry);
rxq->ctrl = rxq_ctrl;
} else {
rxq_ctrl = mlx5_rxq_new(dev, rxq, desc, socket, conf, rx_seg,
n_seg);
if (rxq_ctrl == NULL) {
DRV_LOG(ERR, "port %u unable to allocate rx queue index %u",
dev->data->port_id, idx);
mlx5_free(rxq);
(*priv->rxq_privs)[idx] = NULL;
rte_errno = ENOMEM;
return -rte_errno;
}
}
mlx5_rxq_ref(dev, idx);
DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
dev->data->port_id, idx);
dev->data->rx_queues[idx] = &rxq_ctrl->rxq;
return 0;
}
/**
*
* @param dev
* Pointer to Ethernet device structure.
* @param idx
* RX queue index.
* @param desc
* Number of descriptors to configure in queue.
* @param hairpin_conf
* Hairpin configuration parameters.
*
* @return
* 0 on success, a negative errno value otherwise and rte_errno is set.
*/
int
mlx5_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
uint16_t desc,
const struct rte_eth_hairpin_conf *hairpin_conf)
{
struct mlx5_priv *priv = dev->data->dev_private;
struct mlx5_rxq_priv *rxq;
struct mlx5_rxq_ctrl *rxq_ctrl;
int res;
res = mlx5_rx_queue_pre_setup(dev, idx, &desc, NULL);
if (res)
return res;
if (hairpin_conf->peer_count != 1) {
rte_errno = EINVAL;
DRV_LOG(ERR, "port %u unable to setup Rx hairpin queue index %u"
" peer count is %u", dev->data->port_id,
idx, hairpin_conf->peer_count);
return -rte_errno;
}
if (hairpin_conf->peers[0].port == dev->data->port_id) {
if (hairpin_conf->peers[0].queue >= priv->txqs_n) {
rte_errno = EINVAL;
DRV_LOG(ERR, "port %u unable to setup Rx hairpin queue"
" index %u, Tx %u is larger than %u",
dev->data->port_id, idx,
hairpin_conf->peers[0].queue, priv->txqs_n);
return -rte_errno;
}
} else {
if (hairpin_conf->manual_bind == 0 ||
hairpin_conf->tx_explicit == 0) {
rte_errno = EINVAL;
DRV_LOG(ERR, "port %u unable to setup Rx hairpin queue"
" index %u peer port %u with attributes %u %u",
dev->data->port_id, idx,