/
hpi_io_intf.sv
47 lines (42 loc) · 1.79 KB
/
hpi_io_intf.sv
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//-------------------------------------------------------------------------
// hpi_io_intf.sv --
// Written by Kourosh Arasteh 05-03-2017 --
// --
//-------------------------------------------------------------------------
module hpi_io_intf( input Clk, Reset,
input [1:0] from_sw_address,
output[15:0] from_sw_data_in,
input [15:0] from_sw_data_out,
input from_sw_r,from_sw_w,from_sw_cs,
inout [15:0] OTG_DATA,
output[1:0] OTG_ADDR,
output OTG_RD_N, OTG_WR_N, OTG_CS_N, OTG_RST_N
);
// Buffer (register) for from_sw_data_out because inout bus should be driven
// by a register, not combinational logic.
logic [15:0] from_sw_data_out_buffer;
// OTG_DATA should be high Z (tristated) when NIOS is not writing to OTG_DATA inout bus.
assign OTG_DATA = ~from_sw_w ? from_sw_data_out_buffer : 16'bZ;
assign OTG_RST_N = ~Reset;
always_ff @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
from_sw_data_out_buffer <= 16'h0000;
OTG_ADDR <= 2'b00;
OTG_RD_N <= 1'b1;
OTG_WR_N <= 1'b1;
OTG_CS_N <= 1'b1;
from_sw_data_in <= 16'h0000;
end
else
begin
from_sw_data_out_buffer <= from_sw_data_out;
OTG_ADDR <= from_sw_address;
OTG_RD_N <= from_sw_r;
OTG_WR_N <= from_sw_w;
OTG_CS_N <= from_sw_cs;
from_sw_data_in <= OTG_DATA;
end
end
endmodule