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FanSpeed.v
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FanSpeed.v
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/*-- *******************************************************
-- Computer Architecture Course, Laboratory Sources
-- Amirkabir University of Technology (Tehran Polytechnic)
-- Department of Computer Engineering (CE-AUT)
-- https://ce[dot]aut[dot]ac[dot]ir
-- *******************************************************
-- All Rights reserved (C) 2019-2020
-- *******************************************************
-- Student ID :
-- Student Name:
-- Student Mail:
-- *******************************************************
-- Additional Comments:
--
--*/
/*-----------------------------------------------------------
--- Module Name: Fan Speed (PWM)
--- Description: Module3:
-----------------------------------------------------------*/
`timescale 1 ns/1 ns
module FanSpeed (
input arst , // reset [asynch]
input clk , // clock [posedge]
input [7:0] speed , // speed [duty-cycle]
output reg pwm_data // data [output]
);
reg [7:0] counter;
always @(posedge clk or negedge arst)
if(~arst)
counter<=8'b0;
else
begin
if(counter<speed) pwm_data=1'b1;
else pwm_data=1'b0;
counter<=counter+1'b1;
end
endmodule