-
Notifications
You must be signed in to change notification settings - Fork 3
/
lcd_tb.v
95 lines (82 loc) · 2.06 KB
/
lcd_tb.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
// 230419
`timescale 1ns/1ns // time-unit, precision
`default_nettype none
module LCD_tb();
parameter CLOCK_HZ = 1_000_000;
parameter HALF_PERIOD_NS = 1_000_000_000 / (2 * CLOCK_HZ);
// Clock generator
reg Clock = 1'b1;
always begin
#HALF_PERIOD_NS;
Clock = !Clock;
end
// Variables
reg Reset = 1'b0;
reg [7:0] Digit3 = 8'b00000000;
reg [7:0] Digit2 = 8'b00000000;
reg [7:0] Digit1 = 8'b00010000;
reg [7:0] Digit0 = 8'b00000000;
wire [3:0] ComPWM;
wire [7:0] SegPWM;
// Instantiate device under test
LCD #(
.CLOCK_HZ(CLOCK_HZ),
.CHANGE_COM_US(50)
) DUT(
.Clock(Clock),
.Reset(Reset),
.Digit3_i(Digit3),
.Digit2_i(Digit2),
.Digit1_i(Digit1),
.Digit0_i(Digit0),
.ComPWM_o(ComPWM),
.SegPWM_o(SegPWM)
);
// Variable dump
initial begin
$dumpfile("lcd.vcd");
$dumpvars(0, LCD_tb);
$dumpvars(2, DUT.ComAnalog[0]);
$dumpvars(2, DUT.ComAnalog[1]);
$dumpvars(2, DUT.ComAnalog[2]);
$dumpvars(2, DUT.ComAnalog[3]);
$dumpvars(2, DUT.SegAnalog[0]);
$dumpvars(2, DUT.SegAnalog[1]);
$dumpvars(2, DUT.SegAnalog[2]);
$dumpvars(2, DUT.SegAnalog[3]);
$dumpvars(2, DUT.SegAnalog[4]);
$dumpvars(2, DUT.SegAnalog[5]);
$dumpvars(2, DUT.SegAnalog[6]);
$dumpvars(2, DUT.SegAnalog[7]);
end
// Test sequence
initial begin
$timeformat(-6, 3, "us", 10);
$display("===== START =====");
$display("CLOCK_HZ = %9d", CLOCK_HZ);
#1 Reset = 1'b1;
$display(" time C0 C1 C2 C3 S0 S1 S2 S3 S4 S5 S6 S7");
$monitor("%t %d %d %d %d %d %d %d %d %d %d %d %d",
$realtime,
DUT.ComAnalog[0],
DUT.ComAnalog[1],
DUT.ComAnalog[2],
DUT.ComAnalog[3],
DUT.SegAnalog[0],
DUT.SegAnalog[1],
DUT.SegAnalog[2],
DUT.SegAnalog[3],
DUT.SegAnalog[4],
DUT.SegAnalog[5],
DUT.SegAnalog[6],
DUT.SegAnalog[7],
);
// Wait through all eight states
repeat(8) begin
@(posedge DUT.ChangeState);
end
#1 $display("===== END =====");
#1 $finish;
end
endmodule
`default_nettype wire