[fmc516] Implement synchronization between all data chains with a single clock domain

[lerwys]

The default behavior of the module is to clock the data with 2 clocks. In this way,
we have to sync the data of all 4 data chains to a single clock. By default, the first used clock will be used for this.

[lerwys]

I don't think this is really needed. Evaluate this!

[lerwys]

No need for a new VHDL module. just using a single global clock sufficed