[fmc516] Select the appropriate delays to clock and data coming from ADC

[lerwys]

There is a timing violation in that 1.4 acquisition window is not sufficient for IDDR, as reported
by timing analyzer.

Calibrate the delay from clock and data to match them.

[lerwys]

Applying both data and clock delay in an ADC channel basis is not possible to achieve timing closure. Although, the clock from ADC is half the specified in the constraint. So, we should be fine with a small setup/hold violation.

[lerwys]

The clock from the ADC is only half of the specified in the consttraint if some divider option is used in the ISLA216. By default, the divider is set to 1 and, thus, the clock from the ADCs are the same as the acquisition clock.

However, thus far, the tests show correct acquisition of data, just some delays (see .ucf and/or embedded-sw for the values) were needed to fix some inconsistencies.

[lerwys]

No problems detected so far.