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vpu_l1_cache_ctrl.h
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vpu_l1_cache_ctrl.h
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// This file was generated by the create_regs script
#define L1_BASE 0x7ee02000
#define L1_APB_ID 0x4c314343
#define L1_IC0_CONTROL HW_REGISTER_RW( 0x7ee02000 )
#define L1_IC0_CONTROL_MASK 0x0000007f
#define L1_IC0_CONTROL_WIDTH 7
#define L1_IC0_CONTROL_RESET 0000000000
#define L1_IC0_CONTROL_DISABLE_VLINE_BITS 6:5
#define L1_IC0_CONTROL_DISABLE_VLINE_SET 0x00000060
#define L1_IC0_CONTROL_DISABLE_VLINE_CLR 0xffffff9f
#define L1_IC0_CONTROL_DISABLE_VLINE_MSB 6
#define L1_IC0_CONTROL_DISABLE_VLINE_LSB 5
#define L1_IC0_CONTROL_RAS_DISABLE_BITS 4:4
#define L1_IC0_CONTROL_RAS_DISABLE_SET 0x00000010
#define L1_IC0_CONTROL_RAS_DISABLE_CLR 0xffffffef
#define L1_IC0_CONTROL_RAS_DISABLE_MSB 4
#define L1_IC0_CONTROL_RAS_DISABLE_LSB 4
#define L1_IC0_CONTROL_BP_DISABLE_BITS 3:3
#define L1_IC0_CONTROL_BP_DISABLE_SET 0x00000008
#define L1_IC0_CONTROL_BP_DISABLE_CLR 0xfffffff7
#define L1_IC0_CONTROL_BP_DISABLE_MSB 3
#define L1_IC0_CONTROL_BP_DISABLE_LSB 3
#define L1_IC0_CONTROL_ENABLE_STATS_BITS 2:2
#define L1_IC0_CONTROL_ENABLE_STATS_SET 0x00000004
#define L1_IC0_CONTROL_ENABLE_STATS_CLR 0xfffffffb
#define L1_IC0_CONTROL_ENABLE_STATS_MSB 2
#define L1_IC0_CONTROL_ENABLE_STATS_LSB 2
#define L1_IC0_CONTROL_START_FLUSH_BITS 1:1
#define L1_IC0_CONTROL_START_FLUSH_SET 0x00000002
#define L1_IC0_CONTROL_START_FLUSH_CLR 0xfffffffd
#define L1_IC0_CONTROL_START_FLUSH_MSB 1
#define L1_IC0_CONTROL_START_FLUSH_LSB 1
#define L1_IC0_CONTROL_DISABLE_BITS 0:0
#define L1_IC0_CONTROL_DISABLE_SET 0x00000001
#define L1_IC0_CONTROL_DISABLE_CLR 0xfffffffe
#define L1_IC0_CONTROL_DISABLE_MSB 0
#define L1_IC0_CONTROL_DISABLE_LSB 0
#define L1_IC0_PRIORITY HW_REGISTER_RW( 0x7ee02004 )
#define L1_IC0_PRIORITY_MASK 0x0000ffff
#define L1_IC0_PRIORITY_WIDTH 16
#define L1_IC0_PRIORITY_RESET 0x000034af
#define L1_IC0_PRIORITY_IC0_APRIORITY0_BITS 3:0
#define L1_IC0_PRIORITY_IC0_APRIORITY0_SET 0x0000000f
#define L1_IC0_PRIORITY_IC0_APRIORITY0_CLR 0xfffffff0
#define L1_IC0_PRIORITY_IC0_APRIORITY0_MSB 3
#define L1_IC0_PRIORITY_IC0_APRIORITY0_LSB 0
#define L1_IC0_PRIORITY_IC0_APRIORITY1_BITS 7:4
#define L1_IC0_PRIORITY_IC0_APRIORITY1_SET 0x000000f0
#define L1_IC0_PRIORITY_IC0_APRIORITY1_CLR 0xffffff0f
#define L1_IC0_PRIORITY_IC0_APRIORITY1_MSB 7
#define L1_IC0_PRIORITY_IC0_APRIORITY1_LSB 4
#define L1_IC0_PRIORITY_IC0_APRIORITY2_BITS 11:8
#define L1_IC0_PRIORITY_IC0_APRIORITY2_SET 0x00000f00
#define L1_IC0_PRIORITY_IC0_APRIORITY2_CLR 0xfffff0ff
#define L1_IC0_PRIORITY_IC0_APRIORITY2_MSB 11
#define L1_IC0_PRIORITY_IC0_APRIORITY2_LSB 8
#define L1_IC0_PRIORITY_IC0_APRIORITY3_BITS 15:12
#define L1_IC0_PRIORITY_IC0_APRIORITY3_SET 0x0000f000
#define L1_IC0_PRIORITY_IC0_APRIORITY3_CLR 0xffff0fff
#define L1_IC0_PRIORITY_IC0_APRIORITY3_MSB 15
#define L1_IC0_PRIORITY_IC0_APRIORITY3_LSB 12
#define L1_IC0_FLUSH_S HW_REGISTER_RW( 0x7ee02008 )
#define L1_IC0_FLUSH_S_MASK 0xffffffe0
#define L1_IC0_FLUSH_S_WIDTH 32
#define L1_IC0_FLUSH_S_RESET 0000000000
#define L1_IC0_FLUSH_E HW_REGISTER_RW( 0x7ee0200c )
#define L1_IC0_FLUSH_E_MASK 0xffffffe0
#define L1_IC0_FLUSH_E_WIDTH 32
#define L1_IC0_FLUSH_E_RESET 0xffffffff
#define L1_IC0_RD_HITS HW_REGISTER_RW( 0x7ee02040 )
#define L1_IC0_RD_HITS_MASK 0000000000
#define L1_IC0_RD_HITS_WIDTH 0
#define L1_IC0_RD_MISSES HW_REGISTER_RO( 0x7ee02044 )
#define L1_IC0_RD_MISSES_MASK 0000000000
#define L1_IC0_RD_MISSES_WIDTH 0
#define L1_IC0_BP_HITS HW_REGISTER_RO( 0x7ee02048 )
#define L1_IC0_BP_HITS_MASK 0000000000
#define L1_IC0_BP_HITS_WIDTH 0
#define L1_IC0_BP_MISSES HW_REGISTER_RO( 0x7ee0204c )
#define L1_IC0_BP_MISSES_MASK 0000000000
#define L1_IC0_BP_MISSES_WIDTH 0
#define L1_IC0_RAS_PUSHES HW_REGISTER_RO( 0x7ee02050 )
#define L1_IC0_RAS_PUSHES_MASK 0000000000
#define L1_IC0_RAS_PUSHES_WIDTH 0
#define L1_IC0_RAS_POPS HW_REGISTER_RO( 0x7ee02054 )
#define L1_IC0_RAS_POPS_MASK 0000000000
#define L1_IC0_RAS_POPS_WIDTH 0
#define L1_IC0_RAS_UNDERFLOW HW_REGISTER_RO( 0x7ee02058 )
#define L1_IC0_RAS_UNDERFLOW_MASK 0000000000
#define L1_IC0_RAS_UNDERFLOW_WIDTH 0
#define L1_IC1_CONTROL HW_REGISTER_RW( 0x7ee02080 )
#define L1_IC1_CONTROL_MASK 0x0000007f
#define L1_IC1_CONTROL_WIDTH 7
#define L1_IC1_CONTROL_RESET 0000000000
#define L1_IC1_CONTROL_DISABLE_VLINE_BITS 6:5
#define L1_IC1_CONTROL_DISABLE_VLINE_SET 0x00000060
#define L1_IC1_CONTROL_DISABLE_VLINE_CLR 0xffffff9f
#define L1_IC1_CONTROL_DISABLE_VLINE_MSB 6
#define L1_IC1_CONTROL_DISABLE_VLINE_LSB 5
#define L1_IC1_CONTROL_RAS_DISABLE_BITS 4:4
#define L1_IC1_CONTROL_RAS_DISABLE_SET 0x00000010
#define L1_IC1_CONTROL_RAS_DISABLE_CLR 0xffffffef
#define L1_IC1_CONTROL_RAS_DISABLE_MSB 4
#define L1_IC1_CONTROL_RAS_DISABLE_LSB 4
#define L1_IC1_CONTROL_BP_DISABLE_BITS 3:3
#define L1_IC1_CONTROL_BP_DISABLE_SET 0x00000008
#define L1_IC1_CONTROL_BP_DISABLE_CLR 0xfffffff7
#define L1_IC1_CONTROL_BP_DISABLE_MSB 3
#define L1_IC1_CONTROL_BP_DISABLE_LSB 3
#define L1_IC1_CONTROL_ENABLE_STATS_BITS 2:2
#define L1_IC1_CONTROL_ENABLE_STATS_SET 0x00000004
#define L1_IC1_CONTROL_ENABLE_STATS_CLR 0xfffffffb
#define L1_IC1_CONTROL_ENABLE_STATS_MSB 2
#define L1_IC1_CONTROL_ENABLE_STATS_LSB 2
#define L1_IC1_CONTROL_START_FLUSH_BITS 1:1
#define L1_IC1_CONTROL_START_FLUSH_SET 0x00000002
#define L1_IC1_CONTROL_START_FLUSH_CLR 0xfffffffd
#define L1_IC1_CONTROL_START_FLUSH_MSB 1
#define L1_IC1_CONTROL_START_FLUSH_LSB 1
#define L1_IC1_CONTROL_DISABLE_BITS 0:0
#define L1_IC1_CONTROL_DISABLE_SET 0x00000001
#define L1_IC1_CONTROL_DISABLE_CLR 0xfffffffe
#define L1_IC1_CONTROL_DISABLE_MSB 0
#define L1_IC1_CONTROL_DISABLE_LSB 0
#define L1_IC1_PRIORITY HW_REGISTER_RW( 0x7ee02084 )
#define L1_IC1_PRIORITY_MASK 0x0000ffff
#define L1_IC1_PRIORITY_WIDTH 16
#define L1_IC1_PRIORITY_RESET 0x000034af
#define L1_IC1_PRIORITY_IC1_APRIORITY0_BITS 3:0
#define L1_IC1_PRIORITY_IC1_APRIORITY0_SET 0x0000000f
#define L1_IC1_PRIORITY_IC1_APRIORITY0_CLR 0xfffffff0
#define L1_IC1_PRIORITY_IC1_APRIORITY0_MSB 3
#define L1_IC1_PRIORITY_IC1_APRIORITY0_LSB 0
#define L1_IC1_PRIORITY_IC1_APRIORITY1_BITS 7:4
#define L1_IC1_PRIORITY_IC1_APRIORITY1_SET 0x000000f0
#define L1_IC1_PRIORITY_IC1_APRIORITY1_CLR 0xffffff0f
#define L1_IC1_PRIORITY_IC1_APRIORITY1_MSB 7
#define L1_IC1_PRIORITY_IC1_APRIORITY1_LSB 4
#define L1_IC1_PRIORITY_IC1_APRIORITY2_BITS 11:8
#define L1_IC1_PRIORITY_IC1_APRIORITY2_SET 0x00000f00
#define L1_IC1_PRIORITY_IC1_APRIORITY2_CLR 0xfffff0ff
#define L1_IC1_PRIORITY_IC1_APRIORITY2_MSB 11
#define L1_IC1_PRIORITY_IC1_APRIORITY2_LSB 8
#define L1_IC1_PRIORITY_IC1_APRIORITY3_BITS 15:12
#define L1_IC1_PRIORITY_IC1_APRIORITY3_SET 0x0000f000
#define L1_IC1_PRIORITY_IC1_APRIORITY3_CLR 0xffff0fff
#define L1_IC1_PRIORITY_IC1_APRIORITY3_MSB 15
#define L1_IC1_PRIORITY_IC1_APRIORITY3_LSB 12
#define L1_IC1_FLUSH_S HW_REGISTER_RW( 0x7ee02088 )
#define L1_IC1_FLUSH_S_MASK 0xffffffe0
#define L1_IC1_FLUSH_S_WIDTH 32
#define L1_IC1_FLUSH_S_RESET 0000000000
#define L1_IC1_FLUSH_E HW_REGISTER_RW( 0x7ee0208c )
#define L1_IC1_FLUSH_E_MASK 0xffffffe0
#define L1_IC1_FLUSH_E_WIDTH 32
#define L1_IC1_FLUSH_E_RESET 0xffffffff
#define L1_IC1_RD_HITS HW_REGISTER_RW( 0x7ee020c0 )
#define L1_IC1_RD_HITS_MASK 0000000000
#define L1_IC1_RD_HITS_WIDTH 0
#define L1_IC1_RD_MISSES HW_REGISTER_RO( 0x7ee020c4 )
#define L1_IC1_RD_MISSES_MASK 0000000000
#define L1_IC1_RD_MISSES_WIDTH 0
#define L1_IC1_BP_HITS HW_REGISTER_RO( 0x7ee020c8 )
#define L1_IC1_BP_HITS_MASK 0000000000
#define L1_IC1_BP_HITS_WIDTH 0
#define L1_IC1_BP_MISSES HW_REGISTER_RO( 0x7ee020cc )
#define L1_IC1_BP_MISSES_MASK 0000000000
#define L1_IC1_BP_MISSES_WIDTH 0
#define L1_IC1_RAS_PUSHES HW_REGISTER_RO( 0x7ee020d0 )
#define L1_IC1_RAS_PUSHES_MASK 0000000000
#define L1_IC1_RAS_PUSHES_WIDTH 0
#define L1_IC1_RAS_POPS HW_REGISTER_RO( 0x7ee020d4 )
#define L1_IC1_RAS_POPS_MASK 0000000000
#define L1_IC1_RAS_POPS_WIDTH 0
#define L1_IC1_RAS_UNDERFLOW HW_REGISTER_RO( 0x7ee020d8 )
#define L1_IC1_RAS_UNDERFLOW_MASK 0000000000
#define L1_IC1_RAS_UNDERFLOW_WIDTH 0
#define L1_D_CONTROL HW_REGISTER_RW( 0x7ee02100 )
#define L1_D_CONTROL_MASK 0x0000000f
#define L1_D_CONTROL_WIDTH 4
#define L1_D_CONTROL_RESET 0000000000
#define L1_D_CONTROL_DC_EN_STATS_BITS 3:3
#define L1_D_CONTROL_DC_EN_STATS_SET 0x00000008
#define L1_D_CONTROL_DC_EN_STATS_CLR 0xfffffff7
#define L1_D_CONTROL_DC_EN_STATS_MSB 3
#define L1_D_CONTROL_DC_EN_STATS_LSB 3
#define L1_D_CONTROL_DC1_FLUSH_BITS 2:2
#define L1_D_CONTROL_DC1_FLUSH_SET 0x00000004
#define L1_D_CONTROL_DC1_FLUSH_CLR 0xfffffffb
#define L1_D_CONTROL_DC1_FLUSH_MSB 2
#define L1_D_CONTROL_DC1_FLUSH_LSB 2
#define L1_D_CONTROL_DC0_FLUSH_BITS 1:1
#define L1_D_CONTROL_DC0_FLUSH_SET 0x00000002
#define L1_D_CONTROL_DC0_FLUSH_CLR 0xfffffffd
#define L1_D_CONTROL_DC0_FLUSH_MSB 1
#define L1_D_CONTROL_DC0_FLUSH_LSB 1
#define L1_D_CONTROL_DC_DISABLE_BITS 0:0
#define L1_D_CONTROL_DC_DISABLE_SET 0x00000001
#define L1_D_CONTROL_DC_DISABLE_CLR 0xfffffffe
#define L1_D_CONTROL_DC_DISABLE_MSB 0
#define L1_D_CONTROL_DC_DISABLE_LSB 0
#define L1_D_FLUSH_S HW_REGISTER_RW( 0x7ee02104 )
#define L1_D_FLUSH_S_MASK 0x3fffffe0
#define L1_D_FLUSH_S_WIDTH 30
#define L1_D_FLUSH_S_RESET 0000000000
#define L1_D_FLUSH_E HW_REGISTER_RW( 0x7ee02108 )
#define L1_D_FLUSH_E_MASK 0x3fffffe0
#define L1_D_FLUSH_E_WIDTH 30
#define L1_D_FLUSH_E_RESET 0x3fffffff
#define L1_D_PRIORITY HW_REGISTER_RW( 0x7ee0210c )
#define L1_D_PRIORITY_MASK 0x0fff0fff
#define L1_D_PRIORITY_WIDTH 28
#define L1_D_PRIORITY_RESET 0000000000
#define L1_D_PRIORITY_c0_l2_priority_BITS 3:0
#define L1_D_PRIORITY_c0_l2_priority_SET 0x0000000f
#define L1_D_PRIORITY_c0_l2_priority_CLR 0xfffffff0
#define L1_D_PRIORITY_c0_l2_priority_MSB 3
#define L1_D_PRIORITY_c0_l2_priority_LSB 0
#define L1_D_PRIORITY_c0_uc_priority_BITS 7:4
#define L1_D_PRIORITY_c0_uc_priority_SET 0x000000f0
#define L1_D_PRIORITY_c0_uc_priority_CLR 0xffffff0f
#define L1_D_PRIORITY_c0_uc_priority_MSB 7
#define L1_D_PRIORITY_c0_uc_priority_LSB 4
#define L1_D_PRIORITY_c0_per_priority_BITS 11:8
#define L1_D_PRIORITY_c0_per_priority_SET 0x00000f00
#define L1_D_PRIORITY_c0_per_priority_CLR 0xfffff0ff
#define L1_D_PRIORITY_c0_per_priority_MSB 11
#define L1_D_PRIORITY_c0_per_priority_LSB 8
#define L1_D_PRIORITY_c1_l2_priority_BITS 19:16
#define L1_D_PRIORITY_c1_l2_priority_SET 0x000f0000
#define L1_D_PRIORITY_c1_l2_priority_CLR 0xfff0ffff
#define L1_D_PRIORITY_c1_l2_priority_MSB 19
#define L1_D_PRIORITY_c1_l2_priority_LSB 16
#define L1_D_PRIORITY_c1_uc_priority_BITS 23:20
#define L1_D_PRIORITY_c1_uc_priority_SET 0x00f00000
#define L1_D_PRIORITY_c1_uc_priority_CLR 0xff0fffff
#define L1_D_PRIORITY_c1_uc_priority_MSB 23
#define L1_D_PRIORITY_c1_uc_priority_LSB 20
#define L1_D_PRIORITY_c1_per_priority_BITS 27:24
#define L1_D_PRIORITY_c1_per_priority_SET 0x0f000000
#define L1_D_PRIORITY_c1_per_priority_CLR 0xf0ffffff
#define L1_D_PRIORITY_c1_per_priority_MSB 27
#define L1_D_PRIORITY_c1_per_priority_LSB 24
#define L1_D0_RD_HITS HW_REGISTER_RW( 0x7ee02140 )
#define L1_D0_RD_HITS_MASK 0000000000
#define L1_D0_RD_HITS_WIDTH 0
#define L1_D0_RD_SNOOPS HW_REGISTER_RO( 0x7ee02144 )
#define L1_D0_RD_SNOOPS_MASK 0000000000
#define L1_D0_RD_SNOOPS_WIDTH 0
#define L1_D0_RD_MISSES HW_REGISTER_RO( 0x7ee02148 )
#define L1_D0_RD_MISSES_MASK 0000000000
#define L1_D0_RD_MISSES_WIDTH 0
#define L1_D0_RD_THRUS HW_REGISTER_RO( 0x7ee0214c )
#define L1_D0_RD_THRUS_MASK 0000000000
#define L1_D0_RD_THRUS_WIDTH 0
#define L1_D0_WR_HITS HW_REGISTER_RO( 0x7ee02150 )
#define L1_D0_WR_HITS_MASK 0000000000
#define L1_D0_WR_HITS_WIDTH 0
#define L1_D0_WR_SNOOPS HW_REGISTER_RO( 0x7ee02154 )
#define L1_D0_WR_SNOOPS_MASK 0000000000
#define L1_D0_WR_SNOOPS_WIDTH 0
#define L1_D0_WR_MISSES HW_REGISTER_RO( 0x7ee02158 )
#define L1_D0_WR_MISSES_MASK 0000000000
#define L1_D0_WR_MISSES_WIDTH 0
#define L1_D0_WR_THRUS HW_REGISTER_RO( 0x7ee0215c )
#define L1_D0_WR_THRUS_MASK 0000000000
#define L1_D0_WR_THRUS_WIDTH 0
#define L1_D0_WBACKS HW_REGISTER_RO( 0x7ee02160 )
#define L1_D0_WBACKS_MASK 0000000000
#define L1_D0_WBACKS_WIDTH 0
#define L1_D1_RD_HITS HW_REGISTER_RW( 0x7ee02180 )
#define L1_D1_RD_HITS_MASK 0000000000
#define L1_D1_RD_HITS_WIDTH 0
#define L1_D1_RD_SNOOPS HW_REGISTER_RO( 0x7ee02184 )
#define L1_D1_RD_SNOOPS_MASK 0000000000
#define L1_D1_RD_SNOOPS_WIDTH 0
#define L1_D1_RD_MISSES HW_REGISTER_RO( 0x7ee02188 )
#define L1_D1_RD_MISSES_MASK 0000000000
#define L1_D1_RD_MISSES_WIDTH 0
#define L1_D1_RD_THRUS HW_REGISTER_RO( 0x7ee0218c )
#define L1_D1_RD_THRUS_MASK 0000000000
#define L1_D1_RD_THRUS_WIDTH 0
#define L1_D1_WR_HITS HW_REGISTER_RO( 0x7ee02190 )
#define L1_D1_WR_HITS_MASK 0000000000
#define L1_D1_WR_HITS_WIDTH 0
#define L1_D1_WR_SNOOPS HW_REGISTER_RO( 0x7ee02194 )
#define L1_D1_WR_SNOOPS_MASK 0000000000
#define L1_D1_WR_SNOOPS_WIDTH 0
#define L1_D1_WR_MISSES HW_REGISTER_RO( 0x7ee02198 )
#define L1_D1_WR_MISSES_MASK 0000000000
#define L1_D1_WR_MISSES_WIDTH 0
#define L1_D1_WR_THRUS HW_REGISTER_RO( 0x7ee0219c )
#define L1_D1_WR_THRUS_MASK 0000000000
#define L1_D1_WR_THRUS_WIDTH 0
#define L1_D1_WBACKS HW_REGISTER_RO( 0x7ee021a0 )
#define L1_D1_WBACKS_MASK 0000000000
#define L1_D1_WBACKS_WIDTH 0
#define L1_L1_SANDBOX_START0 HW_REGISTER_RW( 0x7ee02800 )
#define L1_L1_SANDBOX_START0_MASK 0x3fffffff
#define L1_L1_SANDBOX_START0_WIDTH 30
#define L1_L1_SANDBOX_START0_RESET 0x00000007
#define L1_L1_SANDBOX_START0_START_ADDR_BITS 29:5
#define L1_L1_SANDBOX_START0_START_ADDR_SET 0x3fffffe0
#define L1_L1_SANDBOX_START0_START_ADDR_CLR 0xc000001f
#define L1_L1_SANDBOX_START0_START_ADDR_MSB 29
#define L1_L1_SANDBOX_START0_START_ADDR_LSB 5
#define L1_L1_SANDBOX_START0_CTRL_BITS 0:0
#define L1_L1_SANDBOX_START0_CTRL_SET 0x00000001
#define L1_L1_SANDBOX_START0_CTRL_CLR 0xfffffffe
#define L1_L1_SANDBOX_START0_CTRL_MSB 0
#define L1_L1_SANDBOX_START0_CTRL_LSB 0
#define L1_L1_SANDBOX_END0 HW_REGISTER_RW( 0x7ee02804 )
#define L1_L1_SANDBOX_END0_MASK 0x3fffffe0
#define L1_L1_SANDBOX_END0_WIDTH 30
#define L1_L1_SANDBOX_END0_RESET 0x3fffffe0
#define L1_L1_SANDBOX_START1 HW_REGISTER_RW( 0x7ee02808 )
#define L1_L1_SANDBOX_START1_MASK 0x3fffffff
#define L1_L1_SANDBOX_START1_WIDTH 30
#define L1_L1_SANDBOX_START1_RESET 0000000000
#define L1_L1_SANDBOX_START1_START_ADDR_BITS 29:5
#define L1_L1_SANDBOX_START1_START_ADDR_SET 0x3fffffe0
#define L1_L1_SANDBOX_START1_START_ADDR_CLR 0xc000001f
#define L1_L1_SANDBOX_START1_START_ADDR_MSB 29
#define L1_L1_SANDBOX_START1_START_ADDR_LSB 5
#define L1_L1_SANDBOX_START1_CTRL_BITS 0:0
#define L1_L1_SANDBOX_START1_CTRL_SET 0x00000001
#define L1_L1_SANDBOX_START1_CTRL_CLR 0xfffffffe
#define L1_L1_SANDBOX_START1_CTRL_MSB 0
#define L1_L1_SANDBOX_START1_CTRL_LSB 0
#define L1_L1_SANDBOX_END1 HW_REGISTER_RW( 0x7ee0280c )
#define L1_L1_SANDBOX_END1_MASK 0x3fffffe0
#define L1_L1_SANDBOX_END1_WIDTH 30
#define L1_L1_SANDBOX_END1_RESET 0000000000
#define L1_L1_SANDBOX_START2 HW_REGISTER_RW( 0x7ee02810 )
#define L1_L1_SANDBOX_START2_MASK 0x3fffffff
#define L1_L1_SANDBOX_START2_WIDTH 30
#define L1_L1_SANDBOX_START2_RESET 0000000000
#define L1_L1_SANDBOX_START2_START_ADDR_BITS 29:5
#define L1_L1_SANDBOX_START2_START_ADDR_SET 0x3fffffe0
#define L1_L1_SANDBOX_START2_START_ADDR_CLR 0xc000001f
#define L1_L1_SANDBOX_START2_START_ADDR_MSB 29
#define L1_L1_SANDBOX_START2_START_ADDR_LSB 5
#define L1_L1_SANDBOX_START2_CTRL_BITS 0:0
#define L1_L1_SANDBOX_START2_CTRL_SET 0x00000001
#define L1_L1_SANDBOX_START2_CTRL_CLR 0xfffffffe
#define L1_L1_SANDBOX_START2_CTRL_MSB 0
#define L1_L1_SANDBOX_START2_CTRL_LSB 0
#define L1_L1_SANDBOX_END2 HW_REGISTER_RW( 0x7ee02814 )
#define L1_L1_SANDBOX_END2_MASK 0x3fffffe0
#define L1_L1_SANDBOX_END2_WIDTH 30
#define L1_L1_SANDBOX_END2_RESET 0000000000
#define L1_L1_SANDBOX_START3 HW_REGISTER_RW( 0x7ee02818 )
#define L1_L1_SANDBOX_START3_MASK 0x3fffffff
#define L1_L1_SANDBOX_START3_WIDTH 30
#define L1_L1_SANDBOX_START3_RESET 0000000000
#define L1_L1_SANDBOX_START3_START_ADDR_BITS 29:5
#define L1_L1_SANDBOX_START3_START_ADDR_SET 0x3fffffe0
#define L1_L1_SANDBOX_START3_START_ADDR_CLR 0xc000001f
#define L1_L1_SANDBOX_START3_START_ADDR_MSB 29
#define L1_L1_SANDBOX_START3_START_ADDR_LSB 5
#define L1_L1_SANDBOX_START3_CTRL_BITS 0:0
#define L1_L1_SANDBOX_START3_CTRL_SET 0x00000001
#define L1_L1_SANDBOX_START3_CTRL_CLR 0xfffffffe
#define L1_L1_SANDBOX_START3_CTRL_MSB 0
#define L1_L1_SANDBOX_START3_CTRL_LSB 0
#define L1_L1_SANDBOX_END3 HW_REGISTER_RW( 0x7ee0281c )
#define L1_L1_SANDBOX_END3_MASK 0x3fffffe0
#define L1_L1_SANDBOX_END3_WIDTH 30
#define L1_L1_SANDBOX_END3_RESET 0000000000
#define L1_L1_SANDBOX_START4 HW_REGISTER_RW( 0x7ee02820 )
#define L1_L1_SANDBOX_START4_MASK 0x3fffffff
#define L1_L1_SANDBOX_START4_WIDTH 30
#define L1_L1_SANDBOX_START4_RESET 0000000000
#define L1_L1_SANDBOX_START4_START_ADDR_BITS 29:5
#define L1_L1_SANDBOX_START4_START_ADDR_SET 0x3fffffe0
#define L1_L1_SANDBOX_START4_START_ADDR_CLR 0xc000001f
#define L1_L1_SANDBOX_START4_START_ADDR_MSB 29
#define L1_L1_SANDBOX_START4_START_ADDR_LSB 5
#define L1_L1_SANDBOX_START4_CTRL_BITS 0:0
#define L1_L1_SANDBOX_START4_CTRL_SET 0x00000001
#define L1_L1_SANDBOX_START4_CTRL_CLR 0xfffffffe
#define L1_L1_SANDBOX_START4_CTRL_MSB 0
#define L1_L1_SANDBOX_START4_CTRL_LSB 0
#define L1_L1_SANDBOX_END4 HW_REGISTER_RW( 0x7ee02824 )
#define L1_L1_SANDBOX_END4_MASK 0x3fffffe0
#define L1_L1_SANDBOX_END4_WIDTH 30
#define L1_L1_SANDBOX_END4_RESET 0000000000
#define L1_L1_SANDBOX_START5 HW_REGISTER_RW( 0x7ee02828 )
#define L1_L1_SANDBOX_START5_MASK 0x3fffffff
#define L1_L1_SANDBOX_START5_WIDTH 30
#define L1_L1_SANDBOX_START5_RESET 0000000000
#define L1_L1_SANDBOX_START5_START_ADDR_BITS 29:5
#define L1_L1_SANDBOX_START5_START_ADDR_SET 0x3fffffe0
#define L1_L1_SANDBOX_START5_START_ADDR_CLR 0xc000001f
#define L1_L1_SANDBOX_START5_START_ADDR_MSB 29
#define L1_L1_SANDBOX_START5_START_ADDR_LSB 5
#define L1_L1_SANDBOX_START5_CTRL_BITS 0:0
#define L1_L1_SANDBOX_START5_CTRL_SET 0x00000001
#define L1_L1_SANDBOX_START5_CTRL_CLR 0xfffffffe
#define L1_L1_SANDBOX_START5_CTRL_MSB 0
#define L1_L1_SANDBOX_START5_CTRL_LSB 0
#define L1_L1_SANDBOX_END5 HW_REGISTER_RW( 0x7ee0282c )
#define L1_L1_SANDBOX_END5_MASK 0x3fffffe0
#define L1_L1_SANDBOX_END5_WIDTH 30
#define L1_L1_SANDBOX_END5_RESET 0000000000
#define L1_L1_SANDBOX_START6 HW_REGISTER_RW( 0x7ee02830 )
#define L1_L1_SANDBOX_START6_MASK 0x3fffffff
#define L1_L1_SANDBOX_START6_WIDTH 30
#define L1_L1_SANDBOX_START6_RESET 0000000000
#define L1_L1_SANDBOX_START6_START_ADDR_BITS 29:5
#define L1_L1_SANDBOX_START6_START_ADDR_SET 0x3fffffe0
#define L1_L1_SANDBOX_START6_START_ADDR_CLR 0xc000001f
#define L1_L1_SANDBOX_START6_START_ADDR_MSB 29
#define L1_L1_SANDBOX_START6_START_ADDR_LSB 5
#define L1_L1_SANDBOX_START6_CTRL_BITS 0:0
#define L1_L1_SANDBOX_START6_CTRL_SET 0x00000001
#define L1_L1_SANDBOX_START6_CTRL_CLR 0xfffffffe
#define L1_L1_SANDBOX_START6_CTRL_MSB 0
#define L1_L1_SANDBOX_START6_CTRL_LSB 0
#define L1_L1_SANDBOX_END6 HW_REGISTER_RW( 0x7ee02834 )
#define L1_L1_SANDBOX_END6_MASK 0x3fffffe0
#define L1_L1_SANDBOX_END6_WIDTH 30
#define L1_L1_SANDBOX_END6_RESET 0000000000
#define L1_L1_SANDBOX_START7 HW_REGISTER_RW( 0x7ee02838 )
#define L1_L1_SANDBOX_START7_MASK 0x3fffffff
#define L1_L1_SANDBOX_START7_WIDTH 30
#define L1_L1_SANDBOX_START7_RESET 0000000000
#define L1_L1_SANDBOX_START7_START_ADDR_BITS 29:5
#define L1_L1_SANDBOX_START7_START_ADDR_SET 0x3fffffe0
#define L1_L1_SANDBOX_START7_START_ADDR_CLR 0xc000001f
#define L1_L1_SANDBOX_START7_START_ADDR_MSB 29
#define L1_L1_SANDBOX_START7_START_ADDR_LSB 5
#define L1_L1_SANDBOX_START7_CTRL_BITS 0:0
#define L1_L1_SANDBOX_START7_CTRL_SET 0x00000001
#define L1_L1_SANDBOX_START7_CTRL_CLR 0xfffffffe
#define L1_L1_SANDBOX_START7_CTRL_MSB 0
#define L1_L1_SANDBOX_START7_CTRL_LSB 0
#define L1_L1_SANDBOX_END7 HW_REGISTER_RW( 0x7ee0283c )
#define L1_L1_SANDBOX_END7_MASK 0x3fffffe0
#define L1_L1_SANDBOX_END7_WIDTH 30
#define L1_L1_SANDBOX_END7_RESET 0000000000
#define L1_L1_SANDBOX_PERI_BR HW_REGISTER_RW( 0x7ee02840 )
#define L1_L1_SANDBOX_PERI_BR_MASK 0x00001f1f
#define L1_L1_SANDBOX_PERI_BR_WIDTH 13
#define L1_L1_SANDBOX_PERI_BR_RESET 0x00000707
#define L1_L1_SANDBOX_PERI_BR_sandbox_peri_BITS 12:8
#define L1_L1_SANDBOX_PERI_BR_sandbox_peri_SET 0x00001f00
#define L1_L1_SANDBOX_PERI_BR_sandbox_peri_CLR 0xffffe0ff
#define L1_L1_SANDBOX_PERI_BR_sandbox_peri_MSB 12
#define L1_L1_SANDBOX_PERI_BR_sandbox_peri_LSB 8
#define L1_L1_SANDBOX_PERI_BR_sandbox_bootrom_BITS 4:0
#define L1_L1_SANDBOX_PERI_BR_sandbox_bootrom_SET 0x0000001f
#define L1_L1_SANDBOX_PERI_BR_sandbox_bootrom_CLR 0xffffffe0
#define L1_L1_SANDBOX_PERI_BR_sandbox_bootrom_MSB 4
#define L1_L1_SANDBOX_PERI_BR_sandbox_bootrom_LSB 0