fixed a bug for conditional instructions (duh!). should have skipped …

…one instruction instead of one word...
lifthrasiir · Apr 15, 2012 · a8496fb · a8496fb
1 parent c4166e2
commit a8496fb
Show file tree

Hide file tree

Showing 3 changed files with 30 additions and 11 deletions.
diff --git a/dcpu.c b/dcpu.c
@@ -51,6 +51,15 @@ word *get(word v, word *sink)
 	}
 }
 
+// the number of words in this instruction (1 to 3)
+int length(word c)
+{
+	static const uint32_t hasnext = 0x00008f00;
+	int anext = (hasnext >> ((c >> 5) & 31)) & 1;
+	int bnext = (hasnext >> (c >> 11)) & 1;
+	return 1 + anext + bnext;
+}
+
 void tick(void)
 {
 	word c = mem[pc++];
@@ -134,7 +143,7 @@ void tick(void)
 			if (*a == *b) {
 				wc += 1;
 			} else {
-				pc += 1;
+				pc += length(mem[pc]);
 				wc += 2;
 			}
 			break;
@@ -143,7 +152,7 @@ void tick(void)
 			if (*a != *b) {
 				wc += 1;
 			} else {
-				pc += 1;
+				pc += length(mem[pc]);
 				wc += 2;
 			}
 			break;
@@ -152,7 +161,7 @@ void tick(void)
 			if (*a > *b) {
 				wc += 1;
 			} else {
-				pc += 1;
+				pc += length(mem[pc]);
 				wc += 2;
 			}
 			break;
@@ -161,7 +170,7 @@ void tick(void)
 			if (*a & *b) {
 				wc += 1;
 			} else {
-				pc += 1;
+				pc += length(mem[pc]);
 				wc += 2;
 			}
 			break;
@@ -171,10 +180,13 @@ void tick(void)
 		}
 	} else if (aa) {
 		word b0;
+		word tmp;
+
 		switch (aa) {
 		case 0x01: // JSR
+			tmp = *get(bb, &b0);
 			mem[--sp] = pc;
-			pc = *get(bb, &b0);
+			pc = tmp;
 			wc += 2;
 			break;
 

diff --git a/dcpuopt-gen.py b/dcpuopt-gen.py
@@ -1,6 +1,3 @@
-# strategy:
-# we first generate (somewhat) verbose code and remove redundant "+0"s.
-
 values = {
     # value: (code, sp delta, pc delta or "next word" flag)
      0: ('mem[%(sp)s]', 1, 0),
@@ -73,11 +70,11 @@
             if not ajump: # SET PC, ... ignores all side effects on PC
                 if apc + bpc:
                     if opskip:
-                        code += 'pc+=%d+sk;' % (apc + bpc)
+                        code += 'pc+=%d;if(sk)pc+=length(mem[pc]);' % (apc + bpc)
                     else:
                         code += 'pc+=%d;' % (apc + bpc)
                 elif opskip:
-                    code += 'pc+=sk;'
+                    code += 'if(sk)pc+=length(mem[pc]);'
             if opskip:
                 code += 'wc+=%d+sk;' % (apc + bpc + opcycles)
             else:

diff --git a/dcpuopt.c b/dcpuopt.c
@@ -63,6 +63,15 @@ word *get(word v, word *sink)
 	}
 }
 
+// the number of words in this instruction (1 to 3)
+int length(word c)
+{
+	static const uint32_t hasnext = 0x00008f00;
+	int anext = (hasnext >> ((c >> 5) & 31)) & 1;
+	int bnext = (hasnext >> (c >> 11)) & 1;
+	return 1 + anext + bnext;
+}
+
 void tick(void)
 {
 	word c = mem[pc++];
@@ -82,8 +91,9 @@ void tick(void)
 			break;
 
 		case 0x01: // JSR
+			v = *get(bb, &b0);
 			mem[--sp] = pc;
-			pc = *get(bb, &b0);
+			pc = v;
 			wc += 2;
 			break;