/
hal_pnl_reg.h
2357 lines (2333 loc) · 126 KB
/
hal_pnl_reg.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/* Copyright (c) 2018-2019 Sigmastar Technology Corp.
All rights reserved.
Unless otherwise stipulated in writing, any and all information contained
herein regardless in any format shall remain the sole proprietary of
Sigmastar Technology Corp. and be kept in strict confidence
(Sigmastar Confidential Information) by the recipient.
Any unauthorized act including without limitation unauthorized disclosure,
copying, use, reproduction, sale, distribution, modification, disassembling,
reverse engineering and compiling of the contents of Sigmastar Confidential
Information is unlawful and strictly prohibited. Sigmastar hereby reserves the
rights to any and all damages, losses, costs and expenses resulting therefrom.
*/
#ifndef __HAL_PNL_REG_H__
#define __HAL_PNL_REG_H__
#define REG_LPLL_BASE 0x103300UL
#define REG_CHIPTOP_BASE 0x101E00UL
#define REG_CLKGEN_BASE 0x103800UL
#define REG_DISP_TOP_BASE 0x112800UL
#define REG_DISP_TOP_OP2_BASE 0x112900UL
#define REG_SC_CTRL_BASE 0x113300UL
#define REG_DPHY_BASE 0x152800UL
#define REG_PM_TOP_BASE 0x001E00UL
#define REG_EFUSE_BASE 0x002000UL
#ifndef REG_TABLE_END
#define REG_TABLE_END 0xFFFF
#endif
//-------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------
#define REG_CHIPTOP_00_L (REG_CHIPTOP_BASE + 0x00)
#define REG_CHIPTOP_00_H (REG_CHIPTOP_BASE + 0x01)
#define REG_CHIPTOP_01_L (REG_CHIPTOP_BASE + 0x02)
#define REG_CHIPTOP_01_H (REG_CHIPTOP_BASE + 0x03)
#define REG_CHIPTOP_02_L (REG_CHIPTOP_BASE + 0x04)
#define REG_CHIPTOP_02_H (REG_CHIPTOP_BASE + 0x05)
#define REG_CHIPTOP_03_L (REG_CHIPTOP_BASE + 0x06)
#define REG_CHIPTOP_03_H (REG_CHIPTOP_BASE + 0x07)
#define REG_CHIPTOP_04_L (REG_CHIPTOP_BASE + 0x08)
#define REG_CHIPTOP_04_H (REG_CHIPTOP_BASE + 0x09)
#define REG_CHIPTOP_05_L (REG_CHIPTOP_BASE + 0x0A)
#define REG_CHIPTOP_05_H (REG_CHIPTOP_BASE + 0x0B)
#define REG_CHIPTOP_06_L (REG_CHIPTOP_BASE + 0x0C)
#define REG_CHIPTOP_06_H (REG_CHIPTOP_BASE + 0x0D)
#define REG_CHIPTOP_07_L (REG_CHIPTOP_BASE + 0x0E)
#define REG_CHIPTOP_07_H (REG_CHIPTOP_BASE + 0x0F)
#define REG_CHIPTOP_08_L (REG_CHIPTOP_BASE + 0x10)
#define REG_CHIPTOP_08_H (REG_CHIPTOP_BASE + 0x11)
#define REG_CHIPTOP_09_L (REG_CHIPTOP_BASE + 0x12)
#define REG_CHIPTOP_09_H (REG_CHIPTOP_BASE + 0x13)
#define REG_CHIPTOP_0A_L (REG_CHIPTOP_BASE + 0x14)
#define REG_CHIPTOP_0A_H (REG_CHIPTOP_BASE + 0x15)
#define REG_CHIPTOP_0B_L (REG_CHIPTOP_BASE + 0x16)
#define REG_CHIPTOP_0B_H (REG_CHIPTOP_BASE + 0x17)
#define REG_CHIPTOP_0C_L (REG_CHIPTOP_BASE + 0x18)
#define REG_CHIPTOP_0C_H (REG_CHIPTOP_BASE + 0x19)
#define REG_CHIPTOP_0D_L (REG_CHIPTOP_BASE + 0x1A)
#define REG_CHIPTOP_0D_H (REG_CHIPTOP_BASE + 0x1B)
#define REG_CHIPTOP_0E_L (REG_CHIPTOP_BASE + 0x1C)
#define REG_CHIPTOP_0E_H (REG_CHIPTOP_BASE + 0x1D)
#define REG_CHIPTOP_0F_L (REG_CHIPTOP_BASE + 0x1E)
#define REG_CHIPTOP_0F_H (REG_CHIPTOP_BASE + 0x1F)
#define REG_CHIPTOP_10_L (REG_CHIPTOP_BASE + 0x20)
#define REG_CHIPTOP_10_H (REG_CHIPTOP_BASE + 0x21)
#define REG_CHIPTOP_11_L (REG_CHIPTOP_BASE + 0x22)
#define REG_CHIPTOP_11_H (REG_CHIPTOP_BASE + 0x23)
#define REG_CHIPTOP_12_L (REG_CHIPTOP_BASE + 0x24)
#define REG_CHIPTOP_12_H (REG_CHIPTOP_BASE + 0x25)
#define REG_CHIPTOP_13_L (REG_CHIPTOP_BASE + 0x26)
#define REG_CHIPTOP_13_H (REG_CHIPTOP_BASE + 0x27)
#define REG_CHIPTOP_14_L (REG_CHIPTOP_BASE + 0x28)
#define REG_CHIPTOP_14_H (REG_CHIPTOP_BASE + 0x29)
#define REG_CHIPTOP_15_L (REG_CHIPTOP_BASE + 0x2A)
#define REG_CHIPTOP_15_H (REG_CHIPTOP_BASE + 0x2B)
#define REG_CHIPTOP_16_L (REG_CHIPTOP_BASE + 0x2C)
#define REG_CHIPTOP_16_H (REG_CHIPTOP_BASE + 0x2D)
#define REG_CHIPTOP_17_L (REG_CHIPTOP_BASE + 0x2E)
#define REG_CHIPTOP_17_H (REG_CHIPTOP_BASE + 0x2F)
#define REG_CHIPTOP_18_L (REG_CHIPTOP_BASE + 0x30)
#define REG_CHIPTOP_18_H (REG_CHIPTOP_BASE + 0x31)
#define REG_CHIPTOP_19_L (REG_CHIPTOP_BASE + 0x32)
#define REG_CHIPTOP_19_H (REG_CHIPTOP_BASE + 0x33)
#define REG_CHIPTOP_1A_L (REG_CHIPTOP_BASE + 0x34)
#define REG_CHIPTOP_1A_H (REG_CHIPTOP_BASE + 0x35)
#define REG_CHIPTOP_1B_L (REG_CHIPTOP_BASE + 0x36)
#define REG_CHIPTOP_1B_H (REG_CHIPTOP_BASE + 0x37)
#define REG_CHIPTOP_1C_L (REG_CHIPTOP_BASE + 0x38)
#define REG_CHIPTOP_1C_H (REG_CHIPTOP_BASE + 0x39)
#define REG_CHIPTOP_1D_L (REG_CHIPTOP_BASE + 0x3A)
#define REG_CHIPTOP_1D_H (REG_CHIPTOP_BASE + 0x3B)
#define REG_CHIPTOP_1E_L (REG_CHIPTOP_BASE + 0x3C)
#define REG_CHIPTOP_1E_H (REG_CHIPTOP_BASE + 0x3D)
#define REG_CHIPTOP_1F_L (REG_CHIPTOP_BASE + 0x3E)
#define REG_CHIPTOP_1F_H (REG_CHIPTOP_BASE + 0x3F)
#define REG_CHIPTOP_20_L (REG_CHIPTOP_BASE + 0x40)
#define REG_CHIPTOP_20_H (REG_CHIPTOP_BASE + 0x41)
#define REG_CHIPTOP_21_L (REG_CHIPTOP_BASE + 0x42)
#define REG_CHIPTOP_21_H (REG_CHIPTOP_BASE + 0x43)
#define REG_CHIPTOP_22_L (REG_CHIPTOP_BASE + 0x44)
#define REG_CHIPTOP_22_H (REG_CHIPTOP_BASE + 0x45)
#define REG_CHIPTOP_23_L (REG_CHIPTOP_BASE + 0x46)
#define REG_CHIPTOP_23_H (REG_CHIPTOP_BASE + 0x47)
#define REG_CHIPTOP_24_L (REG_CHIPTOP_BASE + 0x48)
#define REG_CHIPTOP_24_H (REG_CHIPTOP_BASE + 0x49)
#define REG_CHIPTOP_25_L (REG_CHIPTOP_BASE + 0x4A)
#define REG_CHIPTOP_25_H (REG_CHIPTOP_BASE + 0x4B)
#define REG_CHIPTOP_26_L (REG_CHIPTOP_BASE + 0x4C)
#define REG_CHIPTOP_26_H (REG_CHIPTOP_BASE + 0x4D)
#define REG_CHIPTOP_27_L (REG_CHIPTOP_BASE + 0x4E)
#define REG_CHIPTOP_27_H (REG_CHIPTOP_BASE + 0x4F)
#define REG_CHIPTOP_28_L (REG_CHIPTOP_BASE + 0x50)
#define REG_CHIPTOP_28_H (REG_CHIPTOP_BASE + 0x51)
#define REG_CHIPTOP_29_L (REG_CHIPTOP_BASE + 0x52)
#define REG_CHIPTOP_29_H (REG_CHIPTOP_BASE + 0x53)
#define REG_CHIPTOP_2A_L (REG_CHIPTOP_BASE + 0x54)
#define REG_CHIPTOP_2A_H (REG_CHIPTOP_BASE + 0x55)
#define REG_CHIPTOP_2B_L (REG_CHIPTOP_BASE + 0x56)
#define REG_CHIPTOP_2B_H (REG_CHIPTOP_BASE + 0x57)
#define REG_CHIPTOP_2C_L (REG_CHIPTOP_BASE + 0x58)
#define REG_CHIPTOP_2C_H (REG_CHIPTOP_BASE + 0x59)
#define REG_CHIPTOP_2D_L (REG_CHIPTOP_BASE + 0x5A)
#define REG_CHIPTOP_2D_H (REG_CHIPTOP_BASE + 0x5B)
#define REG_CHIPTOP_2E_L (REG_CHIPTOP_BASE + 0x5C)
#define REG_CHIPTOP_2E_H (REG_CHIPTOP_BASE + 0x5D)
#define REG_CHIPTOP_2F_L (REG_CHIPTOP_BASE + 0x5E)
#define REG_CHIPTOP_2F_H (REG_CHIPTOP_BASE + 0x5F)
#define REG_CHIPTOP_30_L (REG_CHIPTOP_BASE + 0x60)
#define REG_CHIPTOP_30_H (REG_CHIPTOP_BASE + 0x61)
#define REG_CHIPTOP_31_L (REG_CHIPTOP_BASE + 0x62)
#define REG_CHIPTOP_31_H (REG_CHIPTOP_BASE + 0x63)
#define REG_CHIPTOP_32_L (REG_CHIPTOP_BASE + 0x64)
#define REG_CHIPTOP_32_H (REG_CHIPTOP_BASE + 0x65)
#define REG_CHIPTOP_33_L (REG_CHIPTOP_BASE + 0x66)
#define REG_CHIPTOP_33_H (REG_CHIPTOP_BASE + 0x67)
#define REG_CHIPTOP_34_L (REG_CHIPTOP_BASE + 0x68)
#define REG_CHIPTOP_34_H (REG_CHIPTOP_BASE + 0x69)
#define REG_CHIPTOP_35_L (REG_CHIPTOP_BASE + 0x6A)
#define REG_CHIPTOP_35_H (REG_CHIPTOP_BASE + 0x6B)
#define REG_CHIPTOP_36_L (REG_CHIPTOP_BASE + 0x6C)
#define REG_CHIPTOP_36_H (REG_CHIPTOP_BASE + 0x6D)
#define REG_CHIPTOP_37_L (REG_CHIPTOP_BASE + 0x6E)
#define REG_CHIPTOP_37_H (REG_CHIPTOP_BASE + 0x6F)
#define REG_CHIPTOP_38_L (REG_CHIPTOP_BASE + 0x70)
#define REG_CHIPTOP_38_H (REG_CHIPTOP_BASE + 0x71)
#define REG_CHIPTOP_39_L (REG_CHIPTOP_BASE + 0x72)
#define REG_CHIPTOP_39_H (REG_CHIPTOP_BASE + 0x73)
#define REG_CHIPTOP_3A_L (REG_CHIPTOP_BASE + 0x74)
#define REG_CHIPTOP_3A_H (REG_CHIPTOP_BASE + 0x75)
#define REG_CHIPTOP_3B_L (REG_CHIPTOP_BASE + 0x76)
#define REG_CHIPTOP_3B_H (REG_CHIPTOP_BASE + 0x77)
#define REG_CHIPTOP_3C_L (REG_CHIPTOP_BASE + 0x78)
#define REG_CHIPTOP_3C_H (REG_CHIPTOP_BASE + 0x79)
#define REG_CHIPTOP_3D_L (REG_CHIPTOP_BASE + 0x7A)
#define REG_CHIPTOP_3D_H (REG_CHIPTOP_BASE + 0x7B)
#define REG_CHIPTOP_3E_L (REG_CHIPTOP_BASE + 0x7C)
#define REG_CHIPTOP_3E_H (REG_CHIPTOP_BASE + 0x7D)
#define REG_CHIPTOP_3F_L (REG_CHIPTOP_BASE + 0x7E)
#define REG_CHIPTOP_3F_H (REG_CHIPTOP_BASE + 0x7F)
#define REG_CHIPTOP_40_L (REG_CHIPTOP_BASE + 0x80)
#define REG_CHIPTOP_40_H (REG_CHIPTOP_BASE + 0x81)
#define REG_CHIPTOP_41_L (REG_CHIPTOP_BASE + 0x82)
#define REG_CHIPTOP_41_H (REG_CHIPTOP_BASE + 0x83)
#define REG_CHIPTOP_42_L (REG_CHIPTOP_BASE + 0x84)
#define REG_CHIPTOP_42_H (REG_CHIPTOP_BASE + 0x85)
#define REG_CHIPTOP_43_L (REG_CHIPTOP_BASE + 0x86)
#define REG_CHIPTOP_43_H (REG_CHIPTOP_BASE + 0x87)
#define REG_CHIPTOP_44_L (REG_CHIPTOP_BASE + 0x88)
#define REG_CHIPTOP_44_H (REG_CHIPTOP_BASE + 0x89)
#define REG_CHIPTOP_45_L (REG_CHIPTOP_BASE + 0x8A)
#define REG_CHIPTOP_45_H (REG_CHIPTOP_BASE + 0x8B)
#define REG_CHIPTOP_46_L (REG_CHIPTOP_BASE + 0x8C)
#define REG_CHIPTOP_46_H (REG_CHIPTOP_BASE + 0x8D)
#define REG_CHIPTOP_47_L (REG_CHIPTOP_BASE + 0x8E)
#define REG_CHIPTOP_47_H (REG_CHIPTOP_BASE + 0x8F)
#define REG_CHIPTOP_48_L (REG_CHIPTOP_BASE + 0x90)
#define REG_CHIPTOP_48_H (REG_CHIPTOP_BASE + 0x91)
#define REG_CHIPTOP_49_L (REG_CHIPTOP_BASE + 0x92)
#define REG_CHIPTOP_49_H (REG_CHIPTOP_BASE + 0x93)
#define REG_CHIPTOP_4A_L (REG_CHIPTOP_BASE + 0x94)
#define REG_CHIPTOP_4A_H (REG_CHIPTOP_BASE + 0x95)
#define REG_CHIPTOP_4B_L (REG_CHIPTOP_BASE + 0x96)
#define REG_CHIPTOP_4B_H (REG_CHIPTOP_BASE + 0x97)
#define REG_CHIPTOP_4C_L (REG_CHIPTOP_BASE + 0x98)
#define REG_CHIPTOP_4C_H (REG_CHIPTOP_BASE + 0x99)
#define REG_CHIPTOP_4D_L (REG_CHIPTOP_BASE + 0x9A)
#define REG_CHIPTOP_4D_H (REG_CHIPTOP_BASE + 0x9B)
#define REG_CHIPTOP_4E_L (REG_CHIPTOP_BASE + 0x9C)
#define REG_CHIPTOP_4E_H (REG_CHIPTOP_BASE + 0x9D)
#define REG_CHIPTOP_4F_L (REG_CHIPTOP_BASE + 0x9E)
#define REG_CHIPTOP_4F_H (REG_CHIPTOP_BASE + 0x9F)
#define REG_CHIPTOP_50_L (REG_CHIPTOP_BASE + 0xA0)
#define REG_CHIPTOP_50_H (REG_CHIPTOP_BASE + 0xA1)
#define REG_CHIPTOP_51_L (REG_CHIPTOP_BASE + 0xA2)
#define REG_CHIPTOP_51_H (REG_CHIPTOP_BASE + 0xA3)
#define REG_CHIPTOP_52_L (REG_CHIPTOP_BASE + 0xA4)
#define REG_CHIPTOP_52_H (REG_CHIPTOP_BASE + 0xA5)
#define REG_CHIPTOP_53_L (REG_CHIPTOP_BASE + 0xA6)
#define REG_CHIPTOP_53_H (REG_CHIPTOP_BASE + 0xA7)
#define REG_CHIPTOP_54_L (REG_CHIPTOP_BASE + 0xA8)
#define REG_CHIPTOP_54_H (REG_CHIPTOP_BASE + 0xA9)
#define REG_CHIPTOP_55_L (REG_CHIPTOP_BASE + 0xAA)
#define REG_CHIPTOP_55_H (REG_CHIPTOP_BASE + 0xAB)
#define REG_CHIPTOP_56_L (REG_CHIPTOP_BASE + 0xAC)
#define REG_CHIPTOP_56_H (REG_CHIPTOP_BASE + 0xAD)
#define REG_CHIPTOP_57_L (REG_CHIPTOP_BASE + 0xAE)
#define REG_CHIPTOP_57_H (REG_CHIPTOP_BASE + 0xAF)
#define REG_CHIPTOP_58_L (REG_CHIPTOP_BASE + 0xB0)
#define REG_CHIPTOP_58_H (REG_CHIPTOP_BASE + 0xB1)
#define REG_CHIPTOP_59_L (REG_CHIPTOP_BASE + 0xB2)
#define REG_CHIPTOP_59_H (REG_CHIPTOP_BASE + 0xB3)
#define REG_CHIPTOP_5A_L (REG_CHIPTOP_BASE + 0xB4)
#define REG_CHIPTOP_5A_H (REG_CHIPTOP_BASE + 0xB5)
#define REG_CHIPTOP_5B_L (REG_CHIPTOP_BASE + 0xB6)
#define REG_CHIPTOP_5B_H (REG_CHIPTOP_BASE + 0xB7)
#define REG_CHIPTOP_5C_L (REG_CHIPTOP_BASE + 0xB8)
#define REG_CHIPTOP_5C_H (REG_CHIPTOP_BASE + 0xB9)
#define REG_CHIPTOP_5D_L (REG_CHIPTOP_BASE + 0xBA)
#define REG_CHIPTOP_5D_H (REG_CHIPTOP_BASE + 0xBB)
#define REG_CHIPTOP_5E_L (REG_CHIPTOP_BASE + 0xBC)
#define REG_CHIPTOP_5E_H (REG_CHIPTOP_BASE + 0xBD)
#define REG_CHIPTOP_5F_L (REG_CHIPTOP_BASE + 0xBE)
#define REG_CHIPTOP_5F_H (REG_CHIPTOP_BASE + 0xBF)
#define REG_CHIPTOP_60_L (REG_CHIPTOP_BASE + 0xC0)
#define REG_CHIPTOP_60_H (REG_CHIPTOP_BASE + 0xC1)
#define REG_CHIPTOP_61_L (REG_CHIPTOP_BASE + 0xC2)
#define REG_CHIPTOP_61_H (REG_CHIPTOP_BASE + 0xC3)
#define REG_CHIPTOP_62_L (REG_CHIPTOP_BASE + 0xC4)
#define REG_CHIPTOP_62_H (REG_CHIPTOP_BASE + 0xC5)
#define REG_CHIPTOP_63_L (REG_CHIPTOP_BASE + 0xC6)
#define REG_CHIPTOP_63_H (REG_CHIPTOP_BASE + 0xC7)
#define REG_CHIPTOP_64_L (REG_CHIPTOP_BASE + 0xC8)
#define REG_CHIPTOP_64_H (REG_CHIPTOP_BASE + 0xC9)
#define REG_CHIPTOP_65_L (REG_CHIPTOP_BASE + 0xCA)
#define REG_CHIPTOP_65_H (REG_CHIPTOP_BASE + 0xCB)
#define REG_CHIPTOP_66_L (REG_CHIPTOP_BASE + 0xCC)
#define REG_CHIPTOP_66_H (REG_CHIPTOP_BASE + 0xCD)
#define REG_CHIPTOP_67_L (REG_CHIPTOP_BASE + 0xCE)
#define REG_CHIPTOP_67_H (REG_CHIPTOP_BASE + 0xCF)
#define REG_CHIPTOP_68_L (REG_CHIPTOP_BASE + 0xD0)
#define REG_CHIPTOP_68_H (REG_CHIPTOP_BASE + 0xD1)
#define REG_CHIPTOP_69_L (REG_CHIPTOP_BASE + 0xD2)
#define REG_CHIPTOP_69_H (REG_CHIPTOP_BASE + 0xD3)
#define REG_CHIPTOP_6A_L (REG_CHIPTOP_BASE + 0xD4)
#define REG_CHIPTOP_6A_H (REG_CHIPTOP_BASE + 0xD5)
#define REG_CHIPTOP_6B_L (REG_CHIPTOP_BASE + 0xD6)
#define REG_CHIPTOP_6B_H (REG_CHIPTOP_BASE + 0xD7)
#define REG_CHIPTOP_6C_L (REG_CHIPTOP_BASE + 0xD8)
#define REG_CHIPTOP_6C_H (REG_CHIPTOP_BASE + 0xD9)
#define REG_CHIPTOP_6D_L (REG_CHIPTOP_BASE + 0xDA)
#define REG_CHIPTOP_6D_H (REG_CHIPTOP_BASE + 0xDB)
#define REG_CHIPTOP_6E_L (REG_CHIPTOP_BASE + 0xDC)
#define REG_CHIPTOP_6E_H (REG_CHIPTOP_BASE + 0xDD)
#define REG_CHIPTOP_6F_L (REG_CHIPTOP_BASE + 0xDE)
#define REG_CHIPTOP_6F_H (REG_CHIPTOP_BASE + 0xDF)
#define REG_CHIPTOP_70_L (REG_CHIPTOP_BASE + 0xE0)
#define REG_CHIPTOP_70_H (REG_CHIPTOP_BASE + 0xE1)
#define REG_CHIPTOP_71_L (REG_CHIPTOP_BASE + 0xE2)
#define REG_CHIPTOP_71_H (REG_CHIPTOP_BASE + 0xE3)
#define REG_CHIPTOP_72_L (REG_CHIPTOP_BASE + 0xE4)
#define REG_CHIPTOP_72_H (REG_CHIPTOP_BASE + 0xE5)
#define REG_CHIPTOP_73_L (REG_CHIPTOP_BASE + 0xE6)
#define REG_CHIPTOP_73_H (REG_CHIPTOP_BASE + 0xE7)
#define REG_CHIPTOP_74_L (REG_CHIPTOP_BASE + 0xE8)
#define REG_CHIPTOP_74_H (REG_CHIPTOP_BASE + 0xE9)
#define REG_CHIPTOP_75_L (REG_CHIPTOP_BASE + 0xEA)
#define REG_CHIPTOP_75_H (REG_CHIPTOP_BASE + 0xEB)
#define REG_CHIPTOP_76_L (REG_CHIPTOP_BASE + 0xEC)
#define REG_CHIPTOP_76_H (REG_CHIPTOP_BASE + 0xED)
#define REG_CHIPTOP_77_L (REG_CHIPTOP_BASE + 0xEE)
#define REG_CHIPTOP_77_H (REG_CHIPTOP_BASE + 0xEF)
#define REG_CHIPTOP_78_L (REG_CHIPTOP_BASE + 0xF0)
#define REG_CHIPTOP_78_H (REG_CHIPTOP_BASE + 0xF1)
#define REG_CHIPTOP_79_L (REG_CHIPTOP_BASE + 0xF2)
#define REG_CHIPTOP_79_H (REG_CHIPTOP_BASE + 0xF3)
#define REG_CHIPTOP_7A_L (REG_CHIPTOP_BASE + 0xF4)
#define REG_CHIPTOP_7A_H (REG_CHIPTOP_BASE + 0xF5)
#define REG_CHIPTOP_7B_L (REG_CHIPTOP_BASE + 0xF6)
#define REG_CHIPTOP_7B_H (REG_CHIPTOP_BASE + 0xF7)
#define REG_CHIPTOP_7C_L (REG_CHIPTOP_BASE + 0xF8)
#define REG_CHIPTOP_7C_H (REG_CHIPTOP_BASE + 0xF9)
#define REG_CHIPTOP_7D_L (REG_CHIPTOP_BASE + 0xFA)
#define REG_CHIPTOP_7D_H (REG_CHIPTOP_BASE + 0xFB)
#define REG_CHIPTOP_7E_L (REG_CHIPTOP_BASE + 0xFC)
#define REG_CHIPTOP_7E_H (REG_CHIPTOP_BASE + 0xFD)
#define REG_CHIPTOP_7F_L (REG_CHIPTOP_BASE + 0xFE)
#define REG_CHIPTOP_7F_H (REG_CHIPTOP_BASE + 0xFF)
#define REG_LPLL_00_L (REG_LPLL_BASE + 0x00)
#define REG_LPLL_00_H (REG_LPLL_BASE + 0x01)
#define REG_LPLL_01_L (REG_LPLL_BASE + 0x02)
#define REG_LPLL_01_H (REG_LPLL_BASE + 0x03)
#define REG_LPLL_02_L (REG_LPLL_BASE + 0x04)
#define REG_LPLL_02_H (REG_LPLL_BASE + 0x05)
#define REG_LPLL_03_L (REG_LPLL_BASE + 0x06)
#define REG_LPLL_03_H (REG_LPLL_BASE + 0x07)
#define REG_LPLL_04_L (REG_LPLL_BASE + 0x08)
#define REG_LPLL_04_H (REG_LPLL_BASE + 0x09)
#define REG_LPLL_05_L (REG_LPLL_BASE + 0x0A)
#define REG_LPLL_05_H (REG_LPLL_BASE + 0x0B)
#define REG_LPLL_06_L (REG_LPLL_BASE + 0x0C)
#define REG_LPLL_06_H (REG_LPLL_BASE + 0x0D)
#define REG_LPLL_07_L (REG_LPLL_BASE + 0x0E)
#define REG_LPLL_07_H (REG_LPLL_BASE + 0x0F)
#define REG_LPLL_08_L (REG_LPLL_BASE + 0x10)
#define REG_LPLL_08_H (REG_LPLL_BASE + 0x11)
#define REG_LPLL_09_L (REG_LPLL_BASE + 0x12)
#define REG_LPLL_09_H (REG_LPLL_BASE + 0x13)
#define REG_LPLL_0A_L (REG_LPLL_BASE + 0x14)
#define REG_LPLL_0A_H (REG_LPLL_BASE + 0x15)
#define REG_LPLL_0B_L (REG_LPLL_BASE + 0x16)
#define REG_LPLL_0B_H (REG_LPLL_BASE + 0x17)
#define REG_LPLL_0C_L (REG_LPLL_BASE + 0x18)
#define REG_LPLL_0C_H (REG_LPLL_BASE + 0x19)
#define REG_LPLL_0D_L (REG_LPLL_BASE + 0x1A)
#define REG_LPLL_0D_H (REG_LPLL_BASE + 0x1B)
#define REG_LPLL_0E_L (REG_LPLL_BASE + 0x1C)
#define REG_LPLL_0E_H (REG_LPLL_BASE + 0x1D)
#define REG_LPLL_0F_L (REG_LPLL_BASE + 0x1E)
#define REG_LPLL_0F_H (REG_LPLL_BASE + 0x1F)
#define REG_LPLL_10_L (REG_LPLL_BASE + 0x20)
#define REG_LPLL_10_H (REG_LPLL_BASE + 0x21)
#define REG_LPLL_11_L (REG_LPLL_BASE + 0x22)
#define REG_LPLL_11_H (REG_LPLL_BASE + 0x23)
#define REG_LPLL_12_L (REG_LPLL_BASE + 0x24)
#define REG_LPLL_12_H (REG_LPLL_BASE + 0x25)
#define REG_LPLL_13_L (REG_LPLL_BASE + 0x26)
#define REG_LPLL_13_H (REG_LPLL_BASE + 0x27)
#define REG_LPLL_14_L (REG_LPLL_BASE + 0x28)
#define REG_LPLL_14_H (REG_LPLL_BASE + 0x29)
#define REG_LPLL_15_L (REG_LPLL_BASE + 0x2A)
#define REG_LPLL_15_H (REG_LPLL_BASE + 0x2B)
#define REG_LPLL_16_L (REG_LPLL_BASE + 0x2C)
#define REG_LPLL_16_H (REG_LPLL_BASE + 0x2D)
#define REG_LPLL_17_L (REG_LPLL_BASE + 0x2E)
#define REG_LPLL_17_H (REG_LPLL_BASE + 0x2F)
#define REG_LPLL_18_L (REG_LPLL_BASE + 0x30)
#define REG_LPLL_18_H (REG_LPLL_BASE + 0x31)
#define REG_LPLL_19_L (REG_LPLL_BASE + 0x32)
#define REG_LPLL_19_H (REG_LPLL_BASE + 0x33)
#define REG_LPLL_1A_L (REG_LPLL_BASE + 0x34)
#define REG_LPLL_1A_H (REG_LPLL_BASE + 0x35)
#define REG_LPLL_1B_L (REG_LPLL_BASE + 0x36)
#define REG_LPLL_1B_H (REG_LPLL_BASE + 0x37)
#define REG_LPLL_1C_L (REG_LPLL_BASE + 0x38)
#define REG_LPLL_1C_H (REG_LPLL_BASE + 0x39)
#define REG_LPLL_1D_L (REG_LPLL_BASE + 0x3A)
#define REG_LPLL_1D_H (REG_LPLL_BASE + 0x3B)
#define REG_LPLL_1E_L (REG_LPLL_BASE + 0x3C)
#define REG_LPLL_1E_H (REG_LPLL_BASE + 0x3D)
#define REG_LPLL_1F_L (REG_LPLL_BASE + 0x3E)
#define REG_LPLL_1F_H (REG_LPLL_BASE + 0x3F)
#define REG_LPLL_20_L (REG_LPLL_BASE + 0x40)
#define REG_LPLL_20_H (REG_LPLL_BASE + 0x41)
#define REG_LPLL_21_L (REG_LPLL_BASE + 0x42)
#define REG_LPLL_21_H (REG_LPLL_BASE + 0x43)
#define REG_LPLL_22_L (REG_LPLL_BASE + 0x44)
#define REG_LPLL_22_H (REG_LPLL_BASE + 0x45)
#define REG_LPLL_23_L (REG_LPLL_BASE + 0x46)
#define REG_LPLL_23_H (REG_LPLL_BASE + 0x47)
#define REG_LPLL_24_L (REG_LPLL_BASE + 0x48)
#define REG_LPLL_24_H (REG_LPLL_BASE + 0x49)
#define REG_LPLL_25_L (REG_LPLL_BASE + 0x4A)
#define REG_LPLL_25_H (REG_LPLL_BASE + 0x4B)
#define REG_LPLL_26_L (REG_LPLL_BASE + 0x4C)
#define REG_LPLL_26_H (REG_LPLL_BASE + 0x4D)
#define REG_LPLL_27_L (REG_LPLL_BASE + 0x4E)
#define REG_LPLL_27_H (REG_LPLL_BASE + 0x4F)
#define REG_LPLL_28_L (REG_LPLL_BASE + 0x50)
#define REG_LPLL_28_H (REG_LPLL_BASE + 0x51)
#define REG_LPLL_29_L (REG_LPLL_BASE + 0x52)
#define REG_LPLL_29_H (REG_LPLL_BASE + 0x53)
#define REG_LPLL_2A_L (REG_LPLL_BASE + 0x54)
#define REG_LPLL_2A_H (REG_LPLL_BASE + 0x55)
#define REG_LPLL_2B_L (REG_LPLL_BASE + 0x56)
#define REG_LPLL_2B_H (REG_LPLL_BASE + 0x57)
#define REG_LPLL_2C_L (REG_LPLL_BASE + 0x58)
#define REG_LPLL_2C_H (REG_LPLL_BASE + 0x59)
#define REG_LPLL_2D_L (REG_LPLL_BASE + 0x5A)
#define REG_LPLL_2D_H (REG_LPLL_BASE + 0x5B)
#define REG_LPLL_2E_L (REG_LPLL_BASE + 0x5C)
#define REG_LPLL_2E_H (REG_LPLL_BASE + 0x5D)
#define REG_LPLL_2F_L (REG_LPLL_BASE + 0x5E)
#define REG_LPLL_2F_H (REG_LPLL_BASE + 0x5F)
#define REG_LPLL_30_L (REG_LPLL_BASE + 0x60)
#define REG_LPLL_30_H (REG_LPLL_BASE + 0x61)
#define REG_LPLL_31_L (REG_LPLL_BASE + 0x62)
#define REG_LPLL_31_H (REG_LPLL_BASE + 0x63)
#define REG_LPLL_32_L (REG_LPLL_BASE + 0x64)
#define REG_LPLL_32_H (REG_LPLL_BASE + 0x65)
#define REG_LPLL_33_L (REG_LPLL_BASE + 0x66)
#define REG_LPLL_33_H (REG_LPLL_BASE + 0x67)
#define REG_LPLL_34_L (REG_LPLL_BASE + 0x68)
#define REG_LPLL_34_H (REG_LPLL_BASE + 0x69)
#define REG_LPLL_35_L (REG_LPLL_BASE + 0x6A)
#define REG_LPLL_35_H (REG_LPLL_BASE + 0x6B)
#define REG_LPLL_36_L (REG_LPLL_BASE + 0x6C)
#define REG_LPLL_36_H (REG_LPLL_BASE + 0x6D)
#define REG_LPLL_37_L (REG_LPLL_BASE + 0x6E)
#define REG_LPLL_37_H (REG_LPLL_BASE + 0x6F)
#define REG_LPLL_38_L (REG_LPLL_BASE + 0x70)
#define REG_LPLL_38_H (REG_LPLL_BASE + 0x71)
#define REG_LPLL_39_L (REG_LPLL_BASE + 0x72)
#define REG_LPLL_39_H (REG_LPLL_BASE + 0x73)
#define REG_LPLL_3A_L (REG_LPLL_BASE + 0x74)
#define REG_LPLL_3A_H (REG_LPLL_BASE + 0x75)
#define REG_LPLL_3B_L (REG_LPLL_BASE + 0x76)
#define REG_LPLL_3B_H (REG_LPLL_BASE + 0x77)
#define REG_LPLL_3C_L (REG_LPLL_BASE + 0x78)
#define REG_LPLL_3C_H (REG_LPLL_BASE + 0x79)
#define REG_LPLL_3D_L (REG_LPLL_BASE + 0x7A)
#define REG_LPLL_3D_H (REG_LPLL_BASE + 0x7B)
#define REG_LPLL_3E_L (REG_LPLL_BASE + 0x7C)
#define REG_LPLL_3E_H (REG_LPLL_BASE + 0x7D)
#define REG_LPLL_3F_L (REG_LPLL_BASE + 0x7E)
#define REG_LPLL_3F_H (REG_LPLL_BASE + 0x7F)
#define REG_LPLL_40_L (REG_LPLL_BASE + 0x80)
#define REG_LPLL_40_H (REG_LPLL_BASE + 0x81)
#define REG_LPLL_41_L (REG_LPLL_BASE + 0x82)
#define REG_LPLL_41_H (REG_LPLL_BASE + 0x83)
#define REG_LPLL_42_L (REG_LPLL_BASE + 0x84)
#define REG_LPLL_42_H (REG_LPLL_BASE + 0x85)
#define REG_LPLL_43_L (REG_LPLL_BASE + 0x86)
#define REG_LPLL_43_H (REG_LPLL_BASE + 0x87)
#define REG_LPLL_44_L (REG_LPLL_BASE + 0x88)
#define REG_LPLL_44_H (REG_LPLL_BASE + 0x89)
#define REG_LPLL_45_L (REG_LPLL_BASE + 0x8A)
#define REG_LPLL_45_H (REG_LPLL_BASE + 0x8B)
#define REG_LPLL_46_L (REG_LPLL_BASE + 0x8C)
#define REG_LPLL_46_H (REG_LPLL_BASE + 0x8D)
#define REG_LPLL_47_L (REG_LPLL_BASE + 0x8E)
#define REG_LPLL_47_H (REG_LPLL_BASE + 0x8F)
#define REG_LPLL_48_L (REG_LPLL_BASE + 0x90)
#define REG_LPLL_48_H (REG_LPLL_BASE + 0x91)
#define REG_LPLL_49_L (REG_LPLL_BASE + 0x92)
#define REG_LPLL_49_H (REG_LPLL_BASE + 0x93)
#define REG_LPLL_4A_L (REG_LPLL_BASE + 0x94)
#define REG_LPLL_4A_H (REG_LPLL_BASE + 0x95)
#define REG_LPLL_4B_L (REG_LPLL_BASE + 0x96)
#define REG_LPLL_4B_H (REG_LPLL_BASE + 0x97)
#define REG_LPLL_4C_L (REG_LPLL_BASE + 0x98)
#define REG_LPLL_4C_H (REG_LPLL_BASE + 0x99)
#define REG_LPLL_4D_L (REG_LPLL_BASE + 0x9A)
#define REG_LPLL_4D_H (REG_LPLL_BASE + 0x9B)
#define REG_LPLL_4E_L (REG_LPLL_BASE + 0x9C)
#define REG_LPLL_4E_H (REG_LPLL_BASE + 0x9D)
#define REG_LPLL_4F_L (REG_LPLL_BASE + 0x9E)
#define REG_LPLL_4F_H (REG_LPLL_BASE + 0x9F)
#define REG_LPLL_50_L (REG_LPLL_BASE + 0xA0)
#define REG_LPLL_50_H (REG_LPLL_BASE + 0xA1)
#define REG_LPLL_51_L (REG_LPLL_BASE + 0xA2)
#define REG_LPLL_51_H (REG_LPLL_BASE + 0xA3)
#define REG_LPLL_52_L (REG_LPLL_BASE + 0xA4)
#define REG_LPLL_52_H (REG_LPLL_BASE + 0xA5)
#define REG_LPLL_53_L (REG_LPLL_BASE + 0xA6)
#define REG_LPLL_53_H (REG_LPLL_BASE + 0xA7)
#define REG_LPLL_54_L (REG_LPLL_BASE + 0xA8)
#define REG_LPLL_54_H (REG_LPLL_BASE + 0xA9)
#define REG_LPLL_55_L (REG_LPLL_BASE + 0xAA)
#define REG_LPLL_55_H (REG_LPLL_BASE + 0xAB)
#define REG_LPLL_56_L (REG_LPLL_BASE + 0xAC)
#define REG_LPLL_56_H (REG_LPLL_BASE + 0xAD)
#define REG_LPLL_57_L (REG_LPLL_BASE + 0xAE)
#define REG_LPLL_57_H (REG_LPLL_BASE + 0xAF)
#define REG_LPLL_58_L (REG_LPLL_BASE + 0xB0)
#define REG_LPLL_58_H (REG_LPLL_BASE + 0xB1)
#define REG_LPLL_59_L (REG_LPLL_BASE + 0xB2)
#define REG_LPLL_59_H (REG_LPLL_BASE + 0xB3)
#define REG_LPLL_5A_L (REG_LPLL_BASE + 0xB4)
#define REG_LPLL_5A_H (REG_LPLL_BASE + 0xB5)
#define REG_LPLL_5B_L (REG_LPLL_BASE + 0xB6)
#define REG_LPLL_5B_H (REG_LPLL_BASE + 0xB7)
#define REG_LPLL_5C_L (REG_LPLL_BASE + 0xB8)
#define REG_LPLL_5C_H (REG_LPLL_BASE + 0xB9)
#define REG_LPLL_5D_L (REG_LPLL_BASE + 0xBA)
#define REG_LPLL_5D_H (REG_LPLL_BASE + 0xBB)
#define REG_LPLL_5E_L (REG_LPLL_BASE + 0xBC)
#define REG_LPLL_5E_H (REG_LPLL_BASE + 0xBD)
#define REG_LPLL_5F_L (REG_LPLL_BASE + 0xBE)
#define REG_LPLL_5F_H (REG_LPLL_BASE + 0xBF)
#define REG_LPLL_60_L (REG_LPLL_BASE + 0xC0)
#define REG_LPLL_60_H (REG_LPLL_BASE + 0xC1)
#define REG_LPLL_61_L (REG_LPLL_BASE + 0xC2)
#define REG_LPLL_61_H (REG_LPLL_BASE + 0xC3)
#define REG_LPLL_62_L (REG_LPLL_BASE + 0xC4)
#define REG_LPLL_62_H (REG_LPLL_BASE + 0xC5)
#define REG_LPLL_63_L (REG_LPLL_BASE + 0xC6)
#define REG_LPLL_63_H (REG_LPLL_BASE + 0xC7)
#define REG_LPLL_64_L (REG_LPLL_BASE + 0xC8)
#define REG_LPLL_64_H (REG_LPLL_BASE + 0xC9)
#define REG_LPLL_65_L (REG_LPLL_BASE + 0xCA)
#define REG_LPLL_65_H (REG_LPLL_BASE + 0xCB)
#define REG_LPLL_66_L (REG_LPLL_BASE + 0xCC)
#define REG_LPLL_66_H (REG_LPLL_BASE + 0xCD)
#define REG_LPLL_67_L (REG_LPLL_BASE + 0xCE)
#define REG_LPLL_67_H (REG_LPLL_BASE + 0xCF)
#define REG_LPLL_68_L (REG_LPLL_BASE + 0xD0)
#define REG_LPLL_68_H (REG_LPLL_BASE + 0xD1)
#define REG_LPLL_69_L (REG_LPLL_BASE + 0xD2)
#define REG_LPLL_69_H (REG_LPLL_BASE + 0xD3)
#define REG_LPLL_6A_L (REG_LPLL_BASE + 0xD4)
#define REG_LPLL_6A_H (REG_LPLL_BASE + 0xD5)
#define REG_LPLL_6B_L (REG_LPLL_BASE + 0xD6)
#define REG_LPLL_6B_H (REG_LPLL_BASE + 0xD7)
#define REG_LPLL_6C_L (REG_LPLL_BASE + 0xD8)
#define REG_LPLL_6C_H (REG_LPLL_BASE + 0xD9)
#define REG_LPLL_6D_L (REG_LPLL_BASE + 0xDA)
#define REG_LPLL_6D_H (REG_LPLL_BASE + 0xDB)
#define REG_LPLL_6E_L (REG_LPLL_BASE + 0xDC)
#define REG_LPLL_6E_H (REG_LPLL_BASE + 0xDD)
#define REG_LPLL_6F_L (REG_LPLL_BASE + 0xDE)
#define REG_LPLL_6F_H (REG_LPLL_BASE + 0xDF)
#define REG_LPLL_70_L (REG_LPLL_BASE + 0xE0)
#define REG_LPLL_70_H (REG_LPLL_BASE + 0xE1)
#define REG_LPLL_71_L (REG_LPLL_BASE + 0xE2)
#define REG_LPLL_71_H (REG_LPLL_BASE + 0xE3)
#define REG_LPLL_72_L (REG_LPLL_BASE + 0xE4)
#define REG_LPLL_72_H (REG_LPLL_BASE + 0xE5)
#define REG_LPLL_73_L (REG_LPLL_BASE + 0xE6)
#define REG_LPLL_73_H (REG_LPLL_BASE + 0xE7)
#define REG_LPLL_74_L (REG_LPLL_BASE + 0xE8)
#define REG_LPLL_74_H (REG_LPLL_BASE + 0xE9)
#define REG_LPLL_75_L (REG_LPLL_BASE + 0xEA)
#define REG_LPLL_75_H (REG_LPLL_BASE + 0xEB)
#define REG_LPLL_76_L (REG_LPLL_BASE + 0xEC)
#define REG_LPLL_76_H (REG_LPLL_BASE + 0xED)
#define REG_LPLL_77_L (REG_LPLL_BASE + 0xEE)
#define REG_LPLL_77_H (REG_LPLL_BASE + 0xEF)
#define REG_LPLL_78_L (REG_LPLL_BASE + 0xF0)
#define REG_LPLL_78_H (REG_LPLL_BASE + 0xF1)
#define REG_LPLL_79_L (REG_LPLL_BASE + 0xF2)
#define REG_LPLL_79_H (REG_LPLL_BASE + 0xF3)
#define REG_LPLL_7A_L (REG_LPLL_BASE + 0xF4)
#define REG_LPLL_7A_H (REG_LPLL_BASE + 0xF5)
#define REG_LPLL_7B_L (REG_LPLL_BASE + 0xF6)
#define REG_LPLL_7B_H (REG_LPLL_BASE + 0xF7)
#define REG_LPLL_7C_L (REG_LPLL_BASE + 0xF8)
#define REG_LPLL_7C_H (REG_LPLL_BASE + 0xF9)
#define REG_LPLL_7D_L (REG_LPLL_BASE + 0xFA)
#define REG_LPLL_7D_H (REG_LPLL_BASE + 0xFB)
#define REG_LPLL_7E_L (REG_LPLL_BASE + 0xFC)
#define REG_LPLL_7E_H (REG_LPLL_BASE + 0xFD)
#define REG_LPLL_7F_L (REG_LPLL_BASE + 0xFE)
#define REG_LPLL_7F_H (REG_LPLL_BASE + 0xFF)
#define REG_CLKGEN_00_L (REG_CLKGEN_BASE + 0x00)
#define REG_CLKGEN_00_H (REG_CLKGEN_BASE + 0x01)
#define REG_CLKGEN_01_L (REG_CLKGEN_BASE + 0x02)
#define REG_CLKGEN_01_H (REG_CLKGEN_BASE + 0x03)
#define REG_CLKGEN_02_L (REG_CLKGEN_BASE + 0x04)
#define REG_CLKGEN_02_H (REG_CLKGEN_BASE + 0x05)
#define REG_CLKGEN_03_L (REG_CLKGEN_BASE + 0x06)
#define REG_CLKGEN_03_H (REG_CLKGEN_BASE + 0x07)
#define REG_CLKGEN_04_L (REG_CLKGEN_BASE + 0x08)
#define REG_CLKGEN_04_H (REG_CLKGEN_BASE + 0x09)
#define REG_CLKGEN_05_L (REG_CLKGEN_BASE + 0x0A)
#define REG_CLKGEN_05_H (REG_CLKGEN_BASE + 0x0B)
#define REG_CLKGEN_06_L (REG_CLKGEN_BASE + 0x0C)
#define REG_CLKGEN_06_H (REG_CLKGEN_BASE + 0x0D)
#define REG_CLKGEN_07_L (REG_CLKGEN_BASE + 0x0E)
#define REG_CLKGEN_07_H (REG_CLKGEN_BASE + 0x0F)
#define REG_CLKGEN_08_L (REG_CLKGEN_BASE + 0x10)
#define REG_CLKGEN_08_H (REG_CLKGEN_BASE + 0x11)
#define REG_CLKGEN_09_L (REG_CLKGEN_BASE + 0x12)
#define REG_CLKGEN_09_H (REG_CLKGEN_BASE + 0x13)
#define REG_CLKGEN_0A_L (REG_CLKGEN_BASE + 0x14)
#define REG_CLKGEN_0A_H (REG_CLKGEN_BASE + 0x15)
#define REG_CLKGEN_0B_L (REG_CLKGEN_BASE + 0x16)
#define REG_CLKGEN_0B_H (REG_CLKGEN_BASE + 0x17)
#define REG_CLKGEN_0C_L (REG_CLKGEN_BASE + 0x18)
#define REG_CLKGEN_0C_H (REG_CLKGEN_BASE + 0x19)
#define REG_CLKGEN_0D_L (REG_CLKGEN_BASE + 0x1A)
#define REG_CLKGEN_0D_H (REG_CLKGEN_BASE + 0x1B)
#define REG_CLKGEN_0E_L (REG_CLKGEN_BASE + 0x1C)
#define REG_CLKGEN_0E_H (REG_CLKGEN_BASE + 0x1D)
#define REG_CLKGEN_0F_L (REG_CLKGEN_BASE + 0x1E)
#define REG_CLKGEN_0F_H (REG_CLKGEN_BASE + 0x1F)
#define REG_CLKGEN_10_L (REG_CLKGEN_BASE + 0x20)
#define REG_CLKGEN_10_H (REG_CLKGEN_BASE + 0x21)
#define REG_CLKGEN_11_L (REG_CLKGEN_BASE + 0x22)
#define REG_CLKGEN_11_H (REG_CLKGEN_BASE + 0x23)
#define REG_CLKGEN_12_L (REG_CLKGEN_BASE + 0x24)
#define REG_CLKGEN_12_H (REG_CLKGEN_BASE + 0x25)
#define REG_CLKGEN_13_L (REG_CLKGEN_BASE + 0x26)
#define REG_CLKGEN_13_H (REG_CLKGEN_BASE + 0x27)
#define REG_CLKGEN_14_L (REG_CLKGEN_BASE + 0x28)
#define REG_CLKGEN_14_H (REG_CLKGEN_BASE + 0x29)
#define REG_CLKGEN_15_L (REG_CLKGEN_BASE + 0x2A)
#define REG_CLKGEN_15_H (REG_CLKGEN_BASE + 0x2B)
#define REG_CLKGEN_16_L (REG_CLKGEN_BASE + 0x2C)
#define REG_CLKGEN_16_H (REG_CLKGEN_BASE + 0x2D)
#define REG_CLKGEN_17_L (REG_CLKGEN_BASE + 0x2E)
#define REG_CLKGEN_17_H (REG_CLKGEN_BASE + 0x2F)
#define REG_CLKGEN_18_L (REG_CLKGEN_BASE + 0x30)
#define REG_CLKGEN_18_H (REG_CLKGEN_BASE + 0x31)
#define REG_CLKGEN_19_L (REG_CLKGEN_BASE + 0x32)
#define REG_CLKGEN_19_H (REG_CLKGEN_BASE + 0x33)
#define REG_CLKGEN_1A_L (REG_CLKGEN_BASE + 0x34)
#define REG_CLKGEN_1A_H (REG_CLKGEN_BASE + 0x35)
#define REG_CLKGEN_1B_L (REG_CLKGEN_BASE + 0x36)
#define REG_CLKGEN_1B_H (REG_CLKGEN_BASE + 0x37)
#define REG_CLKGEN_1C_L (REG_CLKGEN_BASE + 0x38)
#define REG_CLKGEN_1C_H (REG_CLKGEN_BASE + 0x39)
#define REG_CLKGEN_1D_L (REG_CLKGEN_BASE + 0x3A)
#define REG_CLKGEN_1D_H (REG_CLKGEN_BASE + 0x3B)
#define REG_CLKGEN_1E_L (REG_CLKGEN_BASE + 0x3C)
#define REG_CLKGEN_1E_H (REG_CLKGEN_BASE + 0x3D)
#define REG_CLKGEN_1F_L (REG_CLKGEN_BASE + 0x3E)
#define REG_CLKGEN_1F_H (REG_CLKGEN_BASE + 0x3F)
#define REG_CLKGEN_20_L (REG_CLKGEN_BASE + 0x40)
#define REG_CLKGEN_20_H (REG_CLKGEN_BASE + 0x41)
#define REG_CLKGEN_21_L (REG_CLKGEN_BASE + 0x42)
#define REG_CLKGEN_21_H (REG_CLKGEN_BASE + 0x43)
#define REG_CLKGEN_22_L (REG_CLKGEN_BASE + 0x44)
#define REG_CLKGEN_22_H (REG_CLKGEN_BASE + 0x45)
#define REG_CLKGEN_23_L (REG_CLKGEN_BASE + 0x46)
#define REG_CLKGEN_23_H (REG_CLKGEN_BASE + 0x47)
#define REG_CLKGEN_24_L (REG_CLKGEN_BASE + 0x48)
#define REG_CLKGEN_24_H (REG_CLKGEN_BASE + 0x49)
#define REG_CLKGEN_25_L (REG_CLKGEN_BASE + 0x4A)
#define REG_CLKGEN_25_H (REG_CLKGEN_BASE + 0x4B)
#define REG_CLKGEN_26_L (REG_CLKGEN_BASE + 0x4C)
#define REG_CLKGEN_26_H (REG_CLKGEN_BASE + 0x4D)
#define REG_CLKGEN_27_L (REG_CLKGEN_BASE + 0x4E)
#define REG_CLKGEN_27_H (REG_CLKGEN_BASE + 0x4F)
#define REG_CLKGEN_28_L (REG_CLKGEN_BASE + 0x50)
#define REG_CLKGEN_28_H (REG_CLKGEN_BASE + 0x51)
#define REG_CLKGEN_29_L (REG_CLKGEN_BASE + 0x52)
#define REG_CLKGEN_29_H (REG_CLKGEN_BASE + 0x53)
#define REG_CLKGEN_2A_L (REG_CLKGEN_BASE + 0x54)
#define REG_CLKGEN_2A_H (REG_CLKGEN_BASE + 0x55)
#define REG_CLKGEN_2B_L (REG_CLKGEN_BASE + 0x56)
#define REG_CLKGEN_2B_H (REG_CLKGEN_BASE + 0x57)
#define REG_CLKGEN_2C_L (REG_CLKGEN_BASE + 0x58)
#define REG_CLKGEN_2C_H (REG_CLKGEN_BASE + 0x59)
#define REG_CLKGEN_2D_L (REG_CLKGEN_BASE + 0x5A)
#define REG_CLKGEN_2D_H (REG_CLKGEN_BASE + 0x5B)
#define REG_CLKGEN_2E_L (REG_CLKGEN_BASE + 0x5C)
#define REG_CLKGEN_2E_H (REG_CLKGEN_BASE + 0x5D)
#define REG_CLKGEN_2F_L (REG_CLKGEN_BASE + 0x5E)
#define REG_CLKGEN_2F_H (REG_CLKGEN_BASE + 0x5F)
#define REG_CLKGEN_30_L (REG_CLKGEN_BASE + 0x60)
#define REG_CLKGEN_30_H (REG_CLKGEN_BASE + 0x61)
#define REG_CLKGEN_31_L (REG_CLKGEN_BASE + 0x62)
#define REG_CLKGEN_31_H (REG_CLKGEN_BASE + 0x63)
#define REG_CLKGEN_32_L (REG_CLKGEN_BASE + 0x64)
#define REG_CLKGEN_32_H (REG_CLKGEN_BASE + 0x65)
#define REG_CLKGEN_33_L (REG_CLKGEN_BASE + 0x66)
#define REG_CLKGEN_33_H (REG_CLKGEN_BASE + 0x67)
#define REG_CLKGEN_34_L (REG_CLKGEN_BASE + 0x68)
#define REG_CLKGEN_34_H (REG_CLKGEN_BASE + 0x69)
#define REG_CLKGEN_35_L (REG_CLKGEN_BASE + 0x6A)
#define REG_CLKGEN_35_H (REG_CLKGEN_BASE + 0x6B)
#define REG_CLKGEN_36_L (REG_CLKGEN_BASE + 0x6C)
#define REG_CLKGEN_36_H (REG_CLKGEN_BASE + 0x6D)
#define REG_CLKGEN_37_L (REG_CLKGEN_BASE + 0x6E)
#define REG_CLKGEN_37_H (REG_CLKGEN_BASE + 0x6F)
#define REG_CLKGEN_38_L (REG_CLKGEN_BASE + 0x70)
#define REG_CLKGEN_38_H (REG_CLKGEN_BASE + 0x71)
#define REG_CLKGEN_39_L (REG_CLKGEN_BASE + 0x72)
#define REG_CLKGEN_39_H (REG_CLKGEN_BASE + 0x73)
#define REG_CLKGEN_3A_L (REG_CLKGEN_BASE + 0x74)
#define REG_CLKGEN_3A_H (REG_CLKGEN_BASE + 0x75)
#define REG_CLKGEN_3B_L (REG_CLKGEN_BASE + 0x76)
#define REG_CLKGEN_3B_H (REG_CLKGEN_BASE + 0x77)
#define REG_CLKGEN_3C_L (REG_CLKGEN_BASE + 0x78)
#define REG_CLKGEN_3C_H (REG_CLKGEN_BASE + 0x79)
#define REG_CLKGEN_3D_L (REG_CLKGEN_BASE + 0x7A)
#define REG_CLKGEN_3D_H (REG_CLKGEN_BASE + 0x7B)
#define REG_CLKGEN_3E_L (REG_CLKGEN_BASE + 0x7C)
#define REG_CLKGEN_3E_H (REG_CLKGEN_BASE + 0x7D)
#define REG_CLKGEN_3F_L (REG_CLKGEN_BASE + 0x7E)
#define REG_CLKGEN_3F_H (REG_CLKGEN_BASE + 0x7F)
#define REG_CLKGEN_40_L (REG_CLKGEN_BASE + 0x80)
#define REG_CLKGEN_40_H (REG_CLKGEN_BASE + 0x81)
#define REG_CLKGEN_41_L (REG_CLKGEN_BASE + 0x82)
#define REG_CLKGEN_41_H (REG_CLKGEN_BASE + 0x83)
#define REG_CLKGEN_42_L (REG_CLKGEN_BASE + 0x84)
#define REG_CLKGEN_42_H (REG_CLKGEN_BASE + 0x85)
#define REG_CLKGEN_43_L (REG_CLKGEN_BASE + 0x86)
#define REG_CLKGEN_43_H (REG_CLKGEN_BASE + 0x87)
#define REG_CLKGEN_44_L (REG_CLKGEN_BASE + 0x88)
#define REG_CLKGEN_44_H (REG_CLKGEN_BASE + 0x89)
#define REG_CLKGEN_45_L (REG_CLKGEN_BASE + 0x8A)
#define REG_CLKGEN_45_H (REG_CLKGEN_BASE + 0x8B)
#define REG_CLKGEN_46_L (REG_CLKGEN_BASE + 0x8C)
#define REG_CLKGEN_46_H (REG_CLKGEN_BASE + 0x8D)
#define REG_CLKGEN_47_L (REG_CLKGEN_BASE + 0x8E)
#define REG_CLKGEN_47_H (REG_CLKGEN_BASE + 0x8F)
#define REG_CLKGEN_48_L (REG_CLKGEN_BASE + 0x90)
#define REG_CLKGEN_48_H (REG_CLKGEN_BASE + 0x91)
#define REG_CLKGEN_49_L (REG_CLKGEN_BASE + 0x92)
#define REG_CLKGEN_49_H (REG_CLKGEN_BASE + 0x93)
#define REG_CLKGEN_4A_L (REG_CLKGEN_BASE + 0x94)
#define REG_CLKGEN_4A_H (REG_CLKGEN_BASE + 0x95)
#define REG_CLKGEN_4B_L (REG_CLKGEN_BASE + 0x96)
#define REG_CLKGEN_4B_H (REG_CLKGEN_BASE + 0x97)
#define REG_CLKGEN_4C_L (REG_CLKGEN_BASE + 0x98)
#define REG_CLKGEN_4C_H (REG_CLKGEN_BASE + 0x99)
#define REG_CLKGEN_4D_L (REG_CLKGEN_BASE + 0x9A)
#define REG_CLKGEN_4D_H (REG_CLKGEN_BASE + 0x9B)
#define REG_CLKGEN_4E_L (REG_CLKGEN_BASE + 0x9C)
#define REG_CLKGEN_4E_H (REG_CLKGEN_BASE + 0x9D)
#define REG_CLKGEN_4F_L (REG_CLKGEN_BASE + 0x9E)
#define REG_CLKGEN_4F_H (REG_CLKGEN_BASE + 0x9F)
#define REG_CLKGEN_50_L (REG_CLKGEN_BASE + 0xA0)
#define REG_CLKGEN_50_H (REG_CLKGEN_BASE + 0xA1)
#define REG_CLKGEN_51_L (REG_CLKGEN_BASE + 0xA2)
#define REG_CLKGEN_51_H (REG_CLKGEN_BASE + 0xA3)
#define REG_CLKGEN_52_L (REG_CLKGEN_BASE + 0xA4)
#define REG_CLKGEN_52_H (REG_CLKGEN_BASE + 0xA5)
#define REG_CLKGEN_53_L (REG_CLKGEN_BASE + 0xA6)
#define REG_CLKGEN_53_H (REG_CLKGEN_BASE + 0xA7)
#define REG_CLKGEN_54_L (REG_CLKGEN_BASE + 0xA8)
#define REG_CLKGEN_54_H (REG_CLKGEN_BASE + 0xA9)
#define REG_CLKGEN_55_L (REG_CLKGEN_BASE + 0xAA)
#define REG_CLKGEN_55_H (REG_CLKGEN_BASE + 0xAB)
#define REG_CLKGEN_56_L (REG_CLKGEN_BASE + 0xAC)
#define REG_CLKGEN_56_H (REG_CLKGEN_BASE + 0xAD)
#define REG_CLKGEN_57_L (REG_CLKGEN_BASE + 0xAE)
#define REG_CLKGEN_57_H (REG_CLKGEN_BASE + 0xAF)
#define REG_CLKGEN_58_L (REG_CLKGEN_BASE + 0xB0)
#define REG_CLKGEN_58_H (REG_CLKGEN_BASE + 0xB1)
#define REG_CLKGEN_59_L (REG_CLKGEN_BASE + 0xB2)
#define REG_CLKGEN_59_H (REG_CLKGEN_BASE + 0xB3)
#define REG_CLKGEN_5A_L (REG_CLKGEN_BASE + 0xB4)
#define REG_CLKGEN_5A_H (REG_CLKGEN_BASE + 0xB5)
#define REG_CLKGEN_5B_L (REG_CLKGEN_BASE + 0xB6)
#define REG_CLKGEN_5B_H (REG_CLKGEN_BASE + 0xB7)
#define REG_CLKGEN_5C_L (REG_CLKGEN_BASE + 0xB8)
#define REG_CLKGEN_5C_H (REG_CLKGEN_BASE + 0xB9)
#define REG_CLKGEN_5D_L (REG_CLKGEN_BASE + 0xBA)
#define REG_CLKGEN_5D_H (REG_CLKGEN_BASE + 0xBB)
#define REG_CLKGEN_5E_L (REG_CLKGEN_BASE + 0xBC)
#define REG_CLKGEN_5E_H (REG_CLKGEN_BASE + 0xBD)
#define REG_CLKGEN_5F_L (REG_CLKGEN_BASE + 0xBE)
#define REG_CLKGEN_5F_H (REG_CLKGEN_BASE + 0xBF)
#define REG_CLKGEN_60_L (REG_CLKGEN_BASE + 0xC0)
#define REG_CLKGEN_60_H (REG_CLKGEN_BASE + 0xC1)
#define REG_CLKGEN_61_L (REG_CLKGEN_BASE + 0xC2)
#define REG_CLKGEN_61_H (REG_CLKGEN_BASE + 0xC3)
#define REG_CLKGEN_62_L (REG_CLKGEN_BASE + 0xC4)
#define REG_CLKGEN_62_H (REG_CLKGEN_BASE + 0xC5)
#define REG_CLKGEN_63_L (REG_CLKGEN_BASE + 0xC6)
#define REG_CLKGEN_63_H (REG_CLKGEN_BASE + 0xC7)
#define REG_CLKGEN_64_L (REG_CLKGEN_BASE + 0xC8)
#define REG_CLKGEN_64_H (REG_CLKGEN_BASE + 0xC9)
#define REG_CLKGEN_65_L (REG_CLKGEN_BASE + 0xCA)
#define REG_CLKGEN_65_H (REG_CLKGEN_BASE + 0xCB)
#define REG_CLKGEN_66_L (REG_CLKGEN_BASE + 0xCC)
#define REG_CLKGEN_66_H (REG_CLKGEN_BASE + 0xCD)
#define REG_CLKGEN_67_L (REG_CLKGEN_BASE + 0xCE)
#define REG_CLKGEN_67_H (REG_CLKGEN_BASE + 0xCF)
#define REG_CLKGEN_68_L (REG_CLKGEN_BASE + 0xD0)
#define REG_CLKGEN_68_H (REG_CLKGEN_BASE + 0xD1)
#define REG_CLKGEN_69_L (REG_CLKGEN_BASE + 0xD2)
#define REG_CLKGEN_69_H (REG_CLKGEN_BASE + 0xD3)
#define REG_CLKGEN_6A_L (REG_CLKGEN_BASE + 0xD4)
#define REG_CLKGEN_6A_H (REG_CLKGEN_BASE + 0xD5)
#define REG_CLKGEN_6B_L (REG_CLKGEN_BASE + 0xD6)
#define REG_CLKGEN_6B_H (REG_CLKGEN_BASE + 0xD7)
#define REG_CLKGEN_6C_L (REG_CLKGEN_BASE + 0xD8)
#define REG_CLKGEN_6C_H (REG_CLKGEN_BASE + 0xD9)
#define REG_CLKGEN_6D_L (REG_CLKGEN_BASE + 0xDA)
#define REG_CLKGEN_6D_H (REG_CLKGEN_BASE + 0xDB)
#define REG_CLKGEN_6E_L (REG_CLKGEN_BASE + 0xDC)
#define REG_CLKGEN_6E_H (REG_CLKGEN_BASE + 0xDD)
#define REG_CLKGEN_6F_L (REG_CLKGEN_BASE + 0xDE)
#define REG_CLKGEN_6F_H (REG_CLKGEN_BASE + 0xDF)
#define REG_CLKGEN_70_L (REG_CLKGEN_BASE + 0xE0)
#define REG_CLKGEN_70_H (REG_CLKGEN_BASE + 0xE1)
#define REG_CLKGEN_71_L (REG_CLKGEN_BASE + 0xE2)
#define REG_CLKGEN_71_H (REG_CLKGEN_BASE + 0xE3)
#define REG_CLKGEN_72_L (REG_CLKGEN_BASE + 0xE4)
#define REG_CLKGEN_72_H (REG_CLKGEN_BASE + 0xE5)
#define REG_CLKGEN_73_L (REG_CLKGEN_BASE + 0xE6)
#define REG_CLKGEN_73_H (REG_CLKGEN_BASE + 0xE7)
#define REG_CLKGEN_74_L (REG_CLKGEN_BASE + 0xE8)
#define REG_CLKGEN_74_H (REG_CLKGEN_BASE + 0xE9)
#define REG_CLKGEN_75_L (REG_CLKGEN_BASE + 0xEA)
#define REG_CLKGEN_75_H (REG_CLKGEN_BASE + 0xEB)
#define REG_CLKGEN_76_L (REG_CLKGEN_BASE + 0xEC)
#define REG_CLKGEN_76_H (REG_CLKGEN_BASE + 0xED)
#define REG_CLKGEN_77_L (REG_CLKGEN_BASE + 0xEE)
#define REG_CLKGEN_77_H (REG_CLKGEN_BASE + 0xEF)
#define REG_CLKGEN_78_L (REG_CLKGEN_BASE + 0xF0)
#define REG_CLKGEN_78_H (REG_CLKGEN_BASE + 0xF1)
#define REG_CLKGEN_79_L (REG_CLKGEN_BASE + 0xF2)
#define REG_CLKGEN_79_H (REG_CLKGEN_BASE + 0xF3)
#define REG_CLKGEN_7A_L (REG_CLKGEN_BASE + 0xF4)
#define REG_CLKGEN_7A_H (REG_CLKGEN_BASE + 0xF5)
#define REG_CLKGEN_7B_L (REG_CLKGEN_BASE + 0xF6)
#define REG_CLKGEN_7B_H (REG_CLKGEN_BASE + 0xF7)
#define REG_CLKGEN_7C_L (REG_CLKGEN_BASE + 0xF8)
#define REG_CLKGEN_7C_H (REG_CLKGEN_BASE + 0xF9)
#define REG_CLKGEN_7D_L (REG_CLKGEN_BASE + 0xFA)
#define REG_CLKGEN_7D_H (REG_CLKGEN_BASE + 0xFB)
#define REG_CLKGEN_7E_L (REG_CLKGEN_BASE + 0xFC)
#define REG_CLKGEN_7E_H (REG_CLKGEN_BASE + 0xFD)
#define REG_CLKGEN_7F_L (REG_CLKGEN_BASE + 0xFE)
#define REG_CLKGEN_7F_H (REG_CLKGEN_BASE + 0xFF)
#define REG_SC_CTRL_00_L (REG_SC_CTRL_BASE + 0x00)
#define REG_SC_CTRL_00_H (REG_SC_CTRL_BASE + 0x01)
#define REG_SC_CTRL_01_L (REG_SC_CTRL_BASE + 0x02)
#define REG_SC_CTRL_01_H (REG_SC_CTRL_BASE + 0x03)
#define REG_SC_CTRL_02_L (REG_SC_CTRL_BASE + 0x04)
#define REG_SC_CTRL_02_H (REG_SC_CTRL_BASE + 0x05)
#define REG_SC_CTRL_03_L (REG_SC_CTRL_BASE + 0x06)
#define REG_SC_CTRL_03_H (REG_SC_CTRL_BASE + 0x07)
#define REG_SC_CTRL_04_L (REG_SC_CTRL_BASE + 0x08)
#define REG_SC_CTRL_04_H (REG_SC_CTRL_BASE + 0x09)
#define REG_SC_CTRL_05_L (REG_SC_CTRL_BASE + 0x0A)
#define REG_SC_CTRL_05_H (REG_SC_CTRL_BASE + 0x0B)
#define REG_SC_CTRL_06_L (REG_SC_CTRL_BASE + 0x0C)
#define REG_SC_CTRL_06_H (REG_SC_CTRL_BASE + 0x0D)
#define REG_SC_CTRL_07_L (REG_SC_CTRL_BASE + 0x0E)
#define REG_SC_CTRL_07_H (REG_SC_CTRL_BASE + 0x0F)
#define REG_SC_CTRL_08_L (REG_SC_CTRL_BASE + 0x10)
#define REG_SC_CTRL_08_H (REG_SC_CTRL_BASE + 0x11)
#define REG_SC_CTRL_09_L (REG_SC_CTRL_BASE + 0x12)
#define REG_SC_CTRL_09_H (REG_SC_CTRL_BASE + 0x13)
#define REG_SC_CTRL_0A_L (REG_SC_CTRL_BASE + 0x14)
#define REG_SC_CTRL_0A_H (REG_SC_CTRL_BASE + 0x15)
#define REG_SC_CTRL_0B_L (REG_SC_CTRL_BASE + 0x16)
#define REG_SC_CTRL_0B_H (REG_SC_CTRL_BASE + 0x17)
#define REG_SC_CTRL_0C_L (REG_SC_CTRL_BASE + 0x18)
#define REG_SC_CTRL_0C_H (REG_SC_CTRL_BASE + 0x19)
#define REG_SC_CTRL_0D_L (REG_SC_CTRL_BASE + 0x1A)
#define REG_SC_CTRL_0D_H (REG_SC_CTRL_BASE + 0x1B)
#define REG_SC_CTRL_0E_L (REG_SC_CTRL_BASE + 0x1C)
#define REG_SC_CTRL_0E_H (REG_SC_CTRL_BASE + 0x1D)
#define REG_SC_CTRL_0F_L (REG_SC_CTRL_BASE + 0x1E)
#define REG_SC_CTRL_0F_H (REG_SC_CTRL_BASE + 0x1F)
#define REG_SC_CTRL_10_L (REG_SC_CTRL_BASE + 0x20)
#define REG_SC_CTRL_10_H (REG_SC_CTRL_BASE + 0x21)
#define REG_SC_CTRL_11_L (REG_SC_CTRL_BASE + 0x22)
#define REG_SC_CTRL_11_H (REG_SC_CTRL_BASE + 0x23)
#define REG_SC_CTRL_12_L (REG_SC_CTRL_BASE + 0x24)
#define REG_SC_CTRL_12_H (REG_SC_CTRL_BASE + 0x25)
#define REG_SC_CTRL_13_L (REG_SC_CTRL_BASE + 0x26)
#define REG_SC_CTRL_13_H (REG_SC_CTRL_BASE + 0x27)
#define REG_SC_CTRL_14_L (REG_SC_CTRL_BASE + 0x28)
#define REG_SC_CTRL_14_H (REG_SC_CTRL_BASE + 0x29)
#define REG_SC_CTRL_15_L (REG_SC_CTRL_BASE + 0x2A)
#define REG_SC_CTRL_15_H (REG_SC_CTRL_BASE + 0x2B)
#define REG_SC_CTRL_16_L (REG_SC_CTRL_BASE + 0x2C)
#define REG_SC_CTRL_16_H (REG_SC_CTRL_BASE + 0x2D)
#define REG_SC_CTRL_17_L (REG_SC_CTRL_BASE + 0x2E)
#define REG_SC_CTRL_17_H (REG_SC_CTRL_BASE + 0x2F)
#define REG_SC_CTRL_18_L (REG_SC_CTRL_BASE + 0x30)
#define REG_SC_CTRL_18_H (REG_SC_CTRL_BASE + 0x31)
#define REG_SC_CTRL_19_L (REG_SC_CTRL_BASE + 0x32)
#define REG_SC_CTRL_19_H (REG_SC_CTRL_BASE + 0x33)
#define REG_SC_CTRL_1A_L (REG_SC_CTRL_BASE + 0x34)
#define REG_SC_CTRL_1A_H (REG_SC_CTRL_BASE + 0x35)
#define REG_SC_CTRL_1B_L (REG_SC_CTRL_BASE + 0x36)
#define REG_SC_CTRL_1B_H (REG_SC_CTRL_BASE + 0x37)
#define REG_SC_CTRL_1C_L (REG_SC_CTRL_BASE + 0x38)
#define REG_SC_CTRL_1C_H (REG_SC_CTRL_BASE + 0x39)
#define REG_SC_CTRL_1D_L (REG_SC_CTRL_BASE + 0x3A)
#define REG_SC_CTRL_1D_H (REG_SC_CTRL_BASE + 0x3B)
#define REG_SC_CTRL_1E_L (REG_SC_CTRL_BASE + 0x3C)
#define REG_SC_CTRL_1E_H (REG_SC_CTRL_BASE + 0x3D)
#define REG_SC_CTRL_1F_L (REG_SC_CTRL_BASE + 0x3E)
#define REG_SC_CTRL_1F_H (REG_SC_CTRL_BASE + 0x3F)
#define REG_SC_CTRL_20_L (REG_SC_CTRL_BASE + 0x40)
#define REG_SC_CTRL_20_H (REG_SC_CTRL_BASE + 0x41)
#define REG_SC_CTRL_21_L (REG_SC_CTRL_BASE + 0x42)
#define REG_SC_CTRL_21_H (REG_SC_CTRL_BASE + 0x43)
#define REG_SC_CTRL_22_L (REG_SC_CTRL_BASE + 0x44)
#define REG_SC_CTRL_22_H (REG_SC_CTRL_BASE + 0x45)
#define REG_SC_CTRL_23_L (REG_SC_CTRL_BASE + 0x46)
#define REG_SC_CTRL_23_H (REG_SC_CTRL_BASE + 0x47)
#define REG_SC_CTRL_24_L (REG_SC_CTRL_BASE + 0x48)
#define REG_SC_CTRL_24_H (REG_SC_CTRL_BASE + 0x49)
#define REG_SC_CTRL_25_L (REG_SC_CTRL_BASE + 0x4A)
#define REG_SC_CTRL_25_H (REG_SC_CTRL_BASE + 0x4B)
#define REG_SC_CTRL_26_L (REG_SC_CTRL_BASE + 0x4C)
#define REG_SC_CTRL_26_H (REG_SC_CTRL_BASE + 0x4D)
#define REG_SC_CTRL_27_L (REG_SC_CTRL_BASE + 0x4E)
#define REG_SC_CTRL_27_H (REG_SC_CTRL_BASE + 0x4F)
#define REG_SC_CTRL_28_L (REG_SC_CTRL_BASE + 0x50)
#define REG_SC_CTRL_28_H (REG_SC_CTRL_BASE + 0x51)
#define REG_SC_CTRL_29_L (REG_SC_CTRL_BASE + 0x52)
#define REG_SC_CTRL_29_H (REG_SC_CTRL_BASE + 0x53)
#define REG_SC_CTRL_2A_L (REG_SC_CTRL_BASE + 0x54)
#define REG_SC_CTRL_2A_H (REG_SC_CTRL_BASE + 0x55)
#define REG_SC_CTRL_2B_L (REG_SC_CTRL_BASE + 0x56)
#define REG_SC_CTRL_2B_H (REG_SC_CTRL_BASE + 0x57)
#define REG_SC_CTRL_2C_L (REG_SC_CTRL_BASE + 0x58)
#define REG_SC_CTRL_2C_H (REG_SC_CTRL_BASE + 0x59)
#define REG_SC_CTRL_2D_L (REG_SC_CTRL_BASE + 0x5A)
#define REG_SC_CTRL_2D_H (REG_SC_CTRL_BASE + 0x5B)
#define REG_SC_CTRL_2E_L (REG_SC_CTRL_BASE + 0x5C)
#define REG_SC_CTRL_2E_H (REG_SC_CTRL_BASE + 0x5D)
#define REG_SC_CTRL_2F_L (REG_SC_CTRL_BASE + 0x5E)
#define REG_SC_CTRL_2F_H (REG_SC_CTRL_BASE + 0x5F)
#define REG_SC_CTRL_30_L (REG_SC_CTRL_BASE + 0x60)
#define REG_SC_CTRL_30_H (REG_SC_CTRL_BASE + 0x61)
#define REG_SC_CTRL_31_L (REG_SC_CTRL_BASE + 0x62)
#define REG_SC_CTRL_31_H (REG_SC_CTRL_BASE + 0x63)
#define REG_SC_CTRL_32_L (REG_SC_CTRL_BASE + 0x64)
#define REG_SC_CTRL_32_H (REG_SC_CTRL_BASE + 0x65)
#define REG_SC_CTRL_33_L (REG_SC_CTRL_BASE + 0x66)
#define REG_SC_CTRL_33_H (REG_SC_CTRL_BASE + 0x67)
#define REG_SC_CTRL_34_L (REG_SC_CTRL_BASE + 0x68)
#define REG_SC_CTRL_34_H (REG_SC_CTRL_BASE + 0x69)
#define REG_SC_CTRL_35_L (REG_SC_CTRL_BASE + 0x6A)
#define REG_SC_CTRL_35_H (REG_SC_CTRL_BASE + 0x6B)
#define REG_SC_CTRL_36_L (REG_SC_CTRL_BASE + 0x6C)
#define REG_SC_CTRL_36_H (REG_SC_CTRL_BASE + 0x6D)
#define REG_SC_CTRL_37_L (REG_SC_CTRL_BASE + 0x6E)
#define REG_SC_CTRL_37_H (REG_SC_CTRL_BASE + 0x6F)
#define REG_SC_CTRL_38_L (REG_SC_CTRL_BASE + 0x70)
#define REG_SC_CTRL_38_H (REG_SC_CTRL_BASE + 0x71)
#define REG_SC_CTRL_39_L (REG_SC_CTRL_BASE + 0x72)
#define REG_SC_CTRL_39_H (REG_SC_CTRL_BASE + 0x73)
#define REG_SC_CTRL_3A_L (REG_SC_CTRL_BASE + 0x74)
#define REG_SC_CTRL_3A_H (REG_SC_CTRL_BASE + 0x75)
#define REG_SC_CTRL_3B_L (REG_SC_CTRL_BASE + 0x76)
#define REG_SC_CTRL_3B_H (REG_SC_CTRL_BASE + 0x77)
#define REG_SC_CTRL_3C_L (REG_SC_CTRL_BASE + 0x78)
#define REG_SC_CTRL_3C_H (REG_SC_CTRL_BASE + 0x79)
#define REG_SC_CTRL_3D_L (REG_SC_CTRL_BASE + 0x7A)
#define REG_SC_CTRL_3D_H (REG_SC_CTRL_BASE + 0x7B)
#define REG_SC_CTRL_3E_L (REG_SC_CTRL_BASE + 0x7C)
#define REG_SC_CTRL_3E_H (REG_SC_CTRL_BASE + 0x7D)
#define REG_SC_CTRL_3F_L (REG_SC_CTRL_BASE + 0x7E)
#define REG_SC_CTRL_3F_H (REG_SC_CTRL_BASE + 0x7F)
#define REG_SC_CTRL_40_L (REG_SC_CTRL_BASE + 0x80)
#define REG_SC_CTRL_40_H (REG_SC_CTRL_BASE + 0x81)
#define REG_SC_CTRL_41_L (REG_SC_CTRL_BASE + 0x82)
#define REG_SC_CTRL_41_H (REG_SC_CTRL_BASE + 0x83)
#define REG_SC_CTRL_42_L (REG_SC_CTRL_BASE + 0x84)
#define REG_SC_CTRL_42_H (REG_SC_CTRL_BASE + 0x85)
#define REG_SC_CTRL_43_L (REG_SC_CTRL_BASE + 0x86)
#define REG_SC_CTRL_43_H (REG_SC_CTRL_BASE + 0x87)
#define REG_SC_CTRL_44_L (REG_SC_CTRL_BASE + 0x88)
#define REG_SC_CTRL_44_H (REG_SC_CTRL_BASE + 0x89)
#define REG_SC_CTRL_45_L (REG_SC_CTRL_BASE + 0x8A)
#define REG_SC_CTRL_45_H (REG_SC_CTRL_BASE + 0x8B)
#define REG_SC_CTRL_46_L (REG_SC_CTRL_BASE + 0x8C)
#define REG_SC_CTRL_46_H (REG_SC_CTRL_BASE + 0x8D)
#define REG_SC_CTRL_47_L (REG_SC_CTRL_BASE + 0x8E)
#define REG_SC_CTRL_47_H (REG_SC_CTRL_BASE + 0x8F)
#define REG_SC_CTRL_48_L (REG_SC_CTRL_BASE + 0x90)
#define REG_SC_CTRL_48_H (REG_SC_CTRL_BASE + 0x91)
#define REG_SC_CTRL_49_L (REG_SC_CTRL_BASE + 0x92)
#define REG_SC_CTRL_49_H (REG_SC_CTRL_BASE + 0x93)
#define REG_SC_CTRL_4A_L (REG_SC_CTRL_BASE + 0x94)
#define REG_SC_CTRL_4A_H (REG_SC_CTRL_BASE + 0x95)
#define REG_SC_CTRL_4B_L (REG_SC_CTRL_BASE + 0x96)
#define REG_SC_CTRL_4B_H (REG_SC_CTRL_BASE + 0x97)
#define REG_SC_CTRL_4C_L (REG_SC_CTRL_BASE + 0x98)
#define REG_SC_CTRL_4C_H (REG_SC_CTRL_BASE + 0x99)
#define REG_SC_CTRL_4D_L (REG_SC_CTRL_BASE + 0x9A)
#define REG_SC_CTRL_4D_H (REG_SC_CTRL_BASE + 0x9B)
#define REG_SC_CTRL_4E_L (REG_SC_CTRL_BASE + 0x9C)
#define REG_SC_CTRL_4E_H (REG_SC_CTRL_BASE + 0x9D)
#define REG_SC_CTRL_4F_L (REG_SC_CTRL_BASE + 0x9E)
#define REG_SC_CTRL_4F_H (REG_SC_CTRL_BASE + 0x9F)
#define REG_SC_CTRL_50_L (REG_SC_CTRL_BASE + 0xA0)
#define REG_SC_CTRL_50_H (REG_SC_CTRL_BASE + 0xA1)
#define REG_SC_CTRL_51_L (REG_SC_CTRL_BASE + 0xA2)
#define REG_SC_CTRL_51_H (REG_SC_CTRL_BASE + 0xA3)
#define REG_SC_CTRL_52_L (REG_SC_CTRL_BASE + 0xA4)
#define REG_SC_CTRL_52_H (REG_SC_CTRL_BASE + 0xA5)
#define REG_SC_CTRL_53_L (REG_SC_CTRL_BASE + 0xA6)
#define REG_SC_CTRL_53_H (REG_SC_CTRL_BASE + 0xA7)
#define REG_SC_CTRL_54_L (REG_SC_CTRL_BASE + 0xA8)
#define REG_SC_CTRL_54_H (REG_SC_CTRL_BASE + 0xA9)
#define REG_SC_CTRL_55_L (REG_SC_CTRL_BASE + 0xAA)
#define REG_SC_CTRL_55_H (REG_SC_CTRL_BASE + 0xAB)
#define REG_SC_CTRL_56_L (REG_SC_CTRL_BASE + 0xAC)
#define REG_SC_CTRL_56_H (REG_SC_CTRL_BASE + 0xAD)
#define REG_SC_CTRL_57_L (REG_SC_CTRL_BASE + 0xAE)
#define REG_SC_CTRL_57_H (REG_SC_CTRL_BASE + 0xAF)
#define REG_SC_CTRL_58_L (REG_SC_CTRL_BASE + 0xB0)
#define REG_SC_CTRL_58_H (REG_SC_CTRL_BASE + 0xB1)
#define REG_SC_CTRL_59_L (REG_SC_CTRL_BASE + 0xB2)
#define REG_SC_CTRL_59_H (REG_SC_CTRL_BASE + 0xB3)
#define REG_SC_CTRL_5A_L (REG_SC_CTRL_BASE + 0xB4)
#define REG_SC_CTRL_5A_H (REG_SC_CTRL_BASE + 0xB5)
#define REG_SC_CTRL_5B_L (REG_SC_CTRL_BASE + 0xB6)
#define REG_SC_CTRL_5B_H (REG_SC_CTRL_BASE + 0xB7)
#define REG_SC_CTRL_5C_L (REG_SC_CTRL_BASE + 0xB8)
#define REG_SC_CTRL_5C_H (REG_SC_CTRL_BASE + 0xB9)
#define REG_SC_CTRL_5D_L (REG_SC_CTRL_BASE + 0xBA)
#define REG_SC_CTRL_5D_H (REG_SC_CTRL_BASE + 0xBB)
#define REG_SC_CTRL_5E_L (REG_SC_CTRL_BASE + 0xBC)
#define REG_SC_CTRL_5E_H (REG_SC_CTRL_BASE + 0xBD)
#define REG_SC_CTRL_5F_L (REG_SC_CTRL_BASE + 0xBE)