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types.h
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/
types.h
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// SPDX-License-Identifier: LGPL-2.1-or-later
/*
* This file is part of libnvme.
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
*
* Authors: Keith Busch <keith.busch@wdc.com>
* Chaitanya Kulkarni <chaitanya.kulkarni@wdc.com>
*/
#ifndef _LIBNVME_TYPES_H
#define _LIBNVME_TYPES_H
#include <stdbool.h>
#include <stdint.h>
#include <linux/types.h>
/**
* DOC: types.h
*
* NVMe standard definitions
*/
/**
* NVME_GET() - extract field from complex value
* @value: The original value of a complex field
* @name: The name of the sub-field within an nvme value
*
* By convention, this library defines _SHIFT and _MASK such that mask can be
* applied after the shift to isolate a specific set of bits that decode to a
* sub-field.
*
* Returns: The 'name' field from 'value'
*/
#define NVME_GET(value, name) \
(((value) >> NVME_##name##_SHIFT) & NVME_##name##_MASK)
/**
* NVME_SET() - set field into complex value
* @value: The value to be set in its completed position
* @name: The name of the sub-field within an nvme value
*
* Returns: The 'name' field from 'value'
*/
#define NVME_SET(value, name) \
(((value) & NVME_##name##_MASK) << NVME_##name##_SHIFT)
/**
* enum nvme_constants - A place to stash various constant nvme values
* @NVME_NSID_ALL: A broadcast value that is used to specify all
* namespaces
* @NVME_NSID_NONE: The invalid namespace id, for when the nsid
* parameter is not used in a command
* @NVME_UUID_NONE: Use to omit a uuid command parameter
* @NVME_CNTLID_NONE: Use to omit a cntlid command parameter
* @NVME_CNSSPECID_NONE: Use to omit a cns_specific_id command parameter
* @NVME_LOG_LSP_NONE: Use to omit a log lsp command parameter
* @NVME_LOG_LSI_NONE: Use to omit a log lsi command parameter
* @NVME_LOG_LPO_NONE: Use to omit a log lpo command parameter
* @NVME_IDENTIFY_DATA_SIZE: The transfer size for nvme identify commands
* @NVME_LOG_SUPPORTED_LOG_PAGES_MAX: The largest possible index in the supported
* log pages log.
* @NVME_ID_NVMSET_LIST_MAX: The largest possible nvmset index in identify
* nvmeset
* @NVME_ID_UUID_LIST_MAX: The largest possible uuid index in identify
* uuid list
* @NVME_ID_CTRL_LIST_MAX: The largest possible controller index in
* identify controller list
* @NVME_ID_NS_LIST_MAX: The largest possible namespace index in
* identify namespace list
* @NVME_ID_SECONDARY_CTRL_MAX: The largest possible secondary controller index
* in identify secondary controller
* @NVME_ID_DOMAIN_LIST_MAX: The largest possible domain index in the
* in domain list
* @NVME_ID_ENDURANCE_GROUP_LIST_MAX: The largest possible endurance group
* index in the endurance group list
* @NVME_ID_ND_DESCRIPTOR_MAX: The largest possible namespace granularity
* index in the namespace granularity descriptor
* list
* @NVME_FEAT_LBA_RANGE_MAX: The largest possible LBA range index in feature
* lba range type
* @NVME_LOG_ST_MAX_RESULTS: The largest possible self test result index in the
* device self test log
* @NVME_LOG_FID_SUPPORTED_EFFECTS_MAX: The largest possible FID index in the
* feature identifiers effects log.
* @NVME_LOG_MI_CMD_SUPPORTED_EFFECTS_MAX: The largest possible MI Command index
* in the MI Command effects log.
* @NVME_LOG_MI_CMD_SUPPORTED_EFFECTS_RESERVED: The reserved space in the MI Command
* effects log.
* @NVME_LOG_TELEM_BLOCK_SIZE: Specification defined size of Telemetry Data Blocks
* @NVME_DSM_MAX_RANGES: The largest possible range index in a data-set
* management command
* @NVME_NQN_LENGTH: Max length for NVMe Qualified Name
* @NVMF_TRADDR_SIZE: Max Transport Address size
* @NVMF_TSAS_SIZE: Max Transport Specific Address Subtype size
* @NVME_ZNS_CHANGED_ZONES_MAX: Max number of zones in the changed zones log
* page
*/
enum nvme_constants {
NVME_NSID_ALL = 0xffffffff,
NVME_NSID_NONE = 0,
NVME_UUID_NONE = 0,
NVME_CNTLID_NONE = 0,
NVME_CNSSPECID_NONE = 0,
NVME_LOG_LSP_NONE = 0,
NVME_LOG_LSI_NONE = 0,
NVME_LOG_LPO_NONE = 0,
NVME_IDENTIFY_DATA_SIZE = 4096,
NVME_LOG_SUPPORTED_LOG_PAGES_MAX = 256,
NVME_ID_NVMSET_LIST_MAX = 31,
NVME_ID_UUID_LIST_MAX = 127,
NVME_ID_CTRL_LIST_MAX = 2047,
NVME_ID_NS_LIST_MAX = 1024,
NVME_ID_SECONDARY_CTRL_MAX = 127,
NVME_ID_DOMAIN_LIST_MAX = 31,
NVME_ID_ENDURANCE_GROUP_LIST_MAX = 2047,
NVME_ID_ND_DESCRIPTOR_MAX = 16,
NVME_FEAT_LBA_RANGE_MAX = 64,
NVME_LOG_ST_MAX_RESULTS = 20,
NVME_LOG_TELEM_BLOCK_SIZE = 512,
NVME_LOG_FID_SUPPORTED_EFFECTS_MAX = 256,
NVME_LOG_MI_CMD_SUPPORTED_EFFECTS_MAX = 256,
NVME_LOG_MI_CMD_SUPPORTED_EFFECTS_RESERVED = 768,
NVME_DSM_MAX_RANGES = 256,
NVME_NQN_LENGTH = 256,
NVMF_TRADDR_SIZE = 256,
NVMF_TSAS_SIZE = 256,
NVME_ZNS_CHANGED_ZONES_MAX = 511,
};
/**
* enum nvme_csi - Defined command set indicators
* @NVME_CSI_NVM: NVM Command Set Indicator
* @NVME_CSI_KV: Key Value Command Set
* @NVME_CSI_ZNS: Zoned Namespace Command Set
*/
enum nvme_csi {
NVME_CSI_NVM = 0,
NVME_CSI_KV = 1,
NVME_CSI_ZNS = 2,
};
/**
* enum nvme_register_offsets - controller registers for all transports. This
* is the layout of BAR0/1 for PCIe, and
* properties for fabrics.
* @NVME_REG_CAP: Controller Capabilities
* @NVME_REG_VS: Version
* @NVME_REG_INTMS: Interrupt Mask Set
* @NVME_REG_INTMC: Interrupt Mask Clear
* @NVME_REG_CC: Controller Configuration
* @NVME_REG_CSTS: Controller Status
* @NVME_REG_NSSR: NVM Subsystem Reset
* @NVME_REG_AQA: Admin Queue Attributes
* @NVME_REG_ASQ: Admin SQ Base Address
* @NVME_REG_ACQ: Admin CQ Base Address
* @NVME_REG_CMBLOC: Controller Memory Buffer Location
* @NVME_REG_CMBSZ: Controller Memory Buffer Size
* @NVME_REG_BPINFO: Boot Partition Information
* @NVME_REG_BPRSEL: Boot Partition Read Select
* @NVME_REG_BPMBL: Boot Partition Memory Buffer Location
* @NVME_REG_CMBMSC: Controller Memory Buffer Memory Space Control
* @NVME_REG_CMBSTS: Controller Memory Buffer Status
* @NVME_REG_CRTO: Controller Ready Timeouts
* @NVME_REG_PMRCAP: Persistent Memory Capabilities
* @NVME_REG_PMRCTL: Persistent Memory Region Control
* @NVME_REG_PMRSTS: Persistent Memory Region Status
* @NVME_REG_PMREBS: Persistent Memory Region Elasticity Buffer Size
* @NVME_REG_PMRSWTP: Memory Region Sustained Write Throughput
* @NVME_REG_PMRMSCL: Persistent Memory Region Controller Memory Space Control Lower
* @NVME_REG_PMRMSCU: Persistent Memory Region Controller Memory Space Control Upper
*/
enum nvme_register_offsets {
NVME_REG_CAP = 0x0000,
NVME_REG_VS = 0x0008,
NVME_REG_INTMS = 0x000c,
NVME_REG_INTMC = 0x0010,
NVME_REG_CC = 0x0014,
NVME_REG_CSTS = 0x001c,
NVME_REG_NSSR = 0x0020,
NVME_REG_AQA = 0x0024,
NVME_REG_ASQ = 0x0028,
NVME_REG_ACQ = 0x0030,
NVME_REG_CMBLOC = 0x0038,
NVME_REG_CMBSZ = 0x003c,
NVME_REG_BPINFO = 0x0040,
NVME_REG_BPRSEL = 0x0044,
NVME_REG_BPMBL = 0x0048,
NVME_REG_CMBMSC = 0x0050,
NVME_REG_CMBSTS = 0x0058,
NVME_REG_CRTO = 0x0068,
NVME_REG_PMRCAP = 0x0e00,
NVME_REG_PMRCTL = 0x0e04,
NVME_REG_PMRSTS = 0x0e08,
NVME_REG_PMREBS = 0x0e0c,
NVME_REG_PMRSWTP = 0x0e10,
NVME_REG_PMRMSCL = 0x0e14,
NVME_REG_PMRMSCU = 0x0e18,
};
/**
* nvme_is_64bit_reg() - Checks if offset of the controller register is a know
* 64bit value.
* @offset: Offset of controller register field in bytes
*
* This function does not care about transport so that the offset is not going
* to be checked inside of this function for the unsupported fields in a
* specific transport. For example, BPMBL(Boot Partition Memory Buffer
* Location) register is not supported by fabrics, but it can be checked here.
*
* Returns: true if given offset is 64bit register, otherwise it returns false.
*/
static inline bool nvme_is_64bit_reg(__u32 offset)
{
switch (offset) {
case NVME_REG_CAP:
case NVME_REG_ASQ:
case NVME_REG_ACQ:
case NVME_REG_BPMBL:
case NVME_REG_CMBMSC:
return true;
default:
return false;
}
}
enum nvme_cap {
NVME_CAP_MQES_SHIFT = 0,
NVME_CAP_CQR_SHIFT = 16,
NVME_CAP_AMS_SHIFT = 17,
NVME_CAP_TO_SHIFT = 24,
NVME_CAP_DSTRD_SHIFT = 32,
NVME_CAP_NSSRC_SHIFT = 36,
NVME_CAP_CSS_SHIFT = 37,
NVME_CAP_BPS_SHIFT = 45,
NVME_CAP_MPSMIN_SHIFT = 48,
NVME_CAP_MPSMAX_SHIFT = 52,
NVME_CAP_PMRS_SHIFT = 56,
NVME_CAP_CMBS_SHIFT = 57,
NVME_CAP_CRMS_SHIFT = 59,
NVME_CAP_MQES_MASK = 0xffff,
NVME_CAP_CQR_MASK = 0x1,
NVME_CAP_AMS_MASK = 0x3,
NVME_CAP_TO_MASK = 0xff,
NVME_CAP_DSTRD_MASK = 0xf,
NVME_CAP_NSSRC_MASK = 0x1,
NVME_CAP_CSS_MASK = 0xff,
NVME_CAP_BPS_MASK = 0x1,
NVME_CAP_MPSMIN_MASK = 0xf,
NVME_CAP_MPSMAX_MASK = 0xf,
NVME_CAP_PMRS_MASK = 0x1,
NVME_CAP_CMBS_MASK = 0x1,
NVME_CAP_CRMS_MASK = 0x3,
NVME_CAP_AMS_WRR = 1 << 0,
NVME_CAP_AMS_VS = 1 << 1,
NVME_CAP_CSS_NVM = 1 << 0,
NVME_CAP_CSS_CSI = 1 << 6,
NVME_CAP_CSS_ADMIN = 1 << 7,
NVME_CAP_CRWMS = 1 << 0,
NVME_CAP_CRIMS = 1 << 1,
};
#define NVME_CAP_MQES(cap) NVME_GET(cap, CAP_MQES)
#define NVME_CAP_CQR(cap) NVME_GET(cap, CAP_CQR)
#define NVME_CAP_AMS(cap) NVME_GET(cap, CAP_AMS)
#define NVME_CAP_TO(cap) NVME_GET(cap, CAP_TO)
#define NVME_CAP_DSTRD(cap) NVME_GET(cap, CAP_DSTRD)
#define NVME_CAP_NSSRC(cap) NVME_GET(cap, CAP_NSSRC)
#define NVME_CAP_CSS(cap) NVME_GET(cap, CAP_CSS)
#define NVME_CAP_BPS(cap) NVME_GET(cap, CAP_BPS)
#define NVME_CAP_MPSMIN(cap) NVME_GET(cap, CAP_MPSMIN)
#define NVME_CAP_MPSMAX(cap) NVME_GET(cap, CAP_MPSMAX)
#define NVME_CAP_PMRS(cap) NVME_GET(cap, CAP_PMRS)
#define NVME_CAP_CMBS(cap) NVME_GET(cap, CAP_CMBS)
#define NVME_CAP_CRMS(cap) NVME_GET(cap, CAP_CRMS)
enum nvme_vs {
NVME_VS_TER_SHIFT = 0,
NVME_VS_MNR_SHIFT = 8,
NVME_VS_MJR_SHIFT = 16,
NVME_VS_TER_MASK = 0xff,
NVME_VS_MNR_MASK = 0xff,
NVME_VS_MJR_MASK = 0xffff,
};
#define NVME_VS_TER(vs) NVME_GET(vs, VS_TER)
#define NVME_VS_MNR(vs) NVME_GET(vs, VS_MNR)
#define NVME_VS_MJR(vs) NVME_GET(vs, VS_MJR)
#define NVME_MAJOR(ver) NVME_VS_MJR(ver)
#define NVME_MINOR(ver) NVME_VS_MNR(ver)
#define NVME_TERTIARY(ver) NVME_VS_TER(ver)
enum nvme_cc {
NVME_CC_EN_SHIFT = 0,
NVME_CC_CSS_SHIFT = 4,
NVME_CC_MPS_SHIFT = 7,
NVME_CC_AMS_SHIFT = 11,
NVME_CC_SHN_SHIFT = 14,
NVME_CC_IOSQES_SHIFT = 16,
NVME_CC_IOCQES_SHIFT = 20,
NVME_CC_CRIME_SHIFT = 24,
NVME_CC_EN_MASK = 0x1,
NVME_CC_CSS_MASK = 0x7,
NVME_CC_MPS_MASK = 0xf,
NVME_CC_AMS_MASK = 0x7,
NVME_CC_SHN_MASK = 0x3,
NVME_CC_CRIME_MASK = 0x1,
NVME_CC_IOSQES_MASK = 0xf,
NVME_CC_IOCQES_MASK = 0xf,
NVME_CC_CSS_NVM = 0,
NVME_CC_CSS_CSI = 6,
NVME_CC_CSS_ADMIN = 7,
NVME_CC_AMS_RR = 0,
NVME_CC_AMS_WRRU = 1,
NVME_CC_AMS_VS = 7,
NVME_CC_SHN_NONE = 0,
NVME_CC_SHN_NORMAL = 1,
NVME_CC_SHN_ABRUPT = 2,
NVME_CC_CRWME = 0,
NVME_CC_CRIME = 1,
};
#define NVME_CC_EN(cc) NVME_GET(cc, CC_EN)
#define NVME_CC_CSS(cc) NVME_GET(cc, CC_CSS)
#define NVME_CC_MPS(cc) NVME_GET(cc, CC_MPS)
#define NVME_CC_AMS(cc) NVME_GET(cc, CC_AMS)
#define NVME_CC_SHN(cc) NVME_GET(cc, CC_SHN)
#define NVME_CC_IOSQES(cc) NVME_GET(cc, CC_IOSQES)
#define NVME_CC_IOCQES(cc) NVME_GET(cc, CC_IOCQES)
#define NVME_CC_CRIME(cc) NVME_GET(cc, CC_CRIME)
enum nvme_csts {
NVME_CSTS_RDY_SHIFT = 0,
NVME_CSTS_CFS_SHIFT = 1,
NVME_CSTS_SHST_SHIFT = 2,
NVME_CSTS_NSSRO_SHIFT = 4,
NVME_CSTS_PP_SHIFT = 5,
NVME_CSTS_RDY_MASK = 0x1,
NVME_CSTS_CFS_MASK = 0x1,
NVME_CSTS_SHN_MASK = 0x3,
NVME_CSTS_NSSRO_MASK = 0x1,
NVME_CSTS_PP_MASK = 0x1,
NVME_CSTS_SHST_NORMAL = 0,
NVME_CSTS_SHST_OCCUR = 1,
NVME_CSTS_SHST_CMPLT = 2,
NVME_CSTS_SHST_MASK = 3,
};
#define NVME_CSTS_RDY(csts) NVME_GET(csts, CSTS_RDY)
#define NVME_CSTS_CFS(csts) NVME_GET(csts, CSTS_CFS)
#define NVME_CSTS_SHST(csts) NVME_GET(csts, CSTS_SHST)
#define NVME_CSTS_NSSRO(csts) NVME_GET(csts, CSTS_NSSRO)
#define NVME_CSTS_PP(csts) NVME_GET(csts, CSTS_PP)
enum nvme_aqa {
NVME_AQA_ASQS_SHIFT = 0,
NVME_AQA_ACQS_SHIFT = 16,
NVME_AQA_ASQS_MASK = 0xfff,
NVME_AQA_ACQS_MASK = 0xfff,
};
#define NVME_AQA_ASQS(aqa) NVME_GET(aqa, AQA_ASQS)
#define NVME_AQA_ACQS(aqa) NVME_GET(aqa, AQA_ACQS)
enum nvme_cmbloc {
NVME_CMBLOC_BIR_SHIFT = 0,
NVME_CMBLOC_CQMMS_SHIFT = 3,
NVME_CMBLOC_CQPDS_SHIFT = 4,
NVME_CMBLOC_CDPLMS_SHIFT = 5,
NVME_CMBLOC_CDPCILS_SHIFT = 6,
NVME_CMBLOC_CDMMMS_SHIFT = 7,
NVME_CMBLOC_CQDA_SHIFT = 8,
NVME_CMBLOC_OFST_SHIFT = 12,
NVME_CMBLOC_BIR_MASK = 0x7,
NVME_CMBLOC_CQMMS_MASK = 0x1,
NVME_CMBLOC_CQPDS_MASK = 0x1,
NVME_CMBLOC_CDPLMS_MASK = 0x1,
NVME_CMBLOC_CDPCILS_MASK = 0x1,
NVME_CMBLOC_CDMMMS_MASK = 0x1,
NVME_CMBLOC_CQDA_MASK = 0x1,
NVME_CMBLOC_OFST_MASK = 0xfffff,
};
#define NVME_CMBLOC_BIR(cmbloc) NVME_GET(cmbloc, CMBLOC_BIR)
#define NVME_CMBLOC_CQMMS(cmbloc) NVME_GET(cmbloc, CMBLOC_CQMMS)
#define NVME_CMBLOC_CQPDS(cmbloc) NVME_GET(cmbloc, CMBLOC_CQPDS)
#define NVME_CMBLOC_CDPLMS(cmbloc) NVME_GET(cmbloc, CMBLOC_CDPLMS)
#define NVME_CMBLOC_CDPCILS(cmbloc) NVME_GET(cmbloc, CMBLOC_CDPCILS)
#define NVME_CMBLOC_CDMMMS(cmbloc) NVME_GET(cmbloc, CMBLOC_CDMMMS)
#define NVME_CMBLOC_CQDA(cmbloc) NVME_GET(cmbloc, CMBLOC_CQDA)
#define NVME_CMBLOC_OFST(cmbloc) NVME_GET(cmbloc, CMBLOC_OFST)
enum nvme_cmbsz {
NVME_CMBSZ_SQS_SHIFT = 0,
NVME_CMBSZ_CQS_SHIFT = 1,
NVME_CMBSZ_LISTS_SHIFT = 2,
NVME_CMBSZ_RDS_SHIFT = 3,
NVME_CMBSZ_WDS_SHIFT = 4,
NVME_CMBSZ_SZU_SHIFT = 8,
NVME_CMBSZ_SZ_SHIFT = 12,
NVME_CMBSZ_SQS_MASK = 0x1,
NVME_CMBSZ_CQS_MASK = 0x1,
NVME_CMBSZ_LISTS_MASK = 0x1,
NVME_CMBSZ_RDS_MASK = 0x1,
NVME_CMBSZ_WDS_MASK = 0x1,
NVME_CMBSZ_SZU_MASK = 0xf,
NVME_CMBSZ_SZ_MASK = 0xfffff,
NVME_CMBSZ_SZU_4K = 0,
NVME_CMBSZ_SZU_64K = 1,
NVME_CMBSZ_SZU_1M = 2,
NVME_CMBSZ_SZU_16M = 3,
NVME_CMBSZ_SZU_256M = 4,
NVME_CMBSZ_SZU_4G = 5,
NVME_CMBSZ_SZU_64G = 6,
};
#define NVME_CMBSZ_SQS(cmbsz) NVME_GET(cmbsz, CMBSZ_SQS)
#define NVME_CMBSZ_CQS(cmbsz) NVME_GET(cmbsz, CMBSZ_CQS)
#define NVME_CMBSZ_LISTS(cmbsz) NVME_GET(cmbsz, CMBSZ_LISTS)
#define NVME_CMBSZ_RDS(cmbsz) NVME_GET(cmbsz, CMBSZ_RDS)
#define NVME_CMBSZ_WDS(cmbsz) NVME_GET(cmbsz, CMBSZ_WDS)
#define NVME_CMBSZ_SZU(cmbsz) NVME_GET(cmbsz, CMBSZ_SZU)
#define NVME_CMBSZ_SZ(cmbsz) NVME_GET(cmbsz, CMBSZ_SZ)
/**
* nvme_cmb_size() - Calculate size of the controller memory buffer
* @cmbsz: Value from controller register %NVME_REG_CMBSZ
*
* Returns: size of controller memory buffer in bytes
*/
static inline __u64 nvme_cmb_size(__u32 cmbsz)
{
return ((__u64)NVME_CMBSZ_SZ(cmbsz)) *
(1ULL << (12 + 4 * NVME_CMBSZ_SZU(cmbsz)));
}
enum nvme_bpinfo {
NVME_BPINFO_BPSZ_SHIFT = 0,
NVME_BPINFO_BRS_SHIFT = 24,
NVME_BPINFO_ABPID_SHIFT = 31,
NVME_BPINFO_BPSZ_MASK = 0x7fff,
NVME_BPINFO_BRS_MASK = 0x3,
NVME_BPINFO_ABPID_MASK = 0x1,
NVME_BPINFO_BRS_NONE = 0,
NVME_BPINFO_BRS_READ_IN_PROGRESS = 1,
NVME_BPINFO_BRS_READ_SUCCESS = 2,
NVME_BPINFO_BRS_READ_ERROR = 3,
};
#define NVME_BPINFO_BPSZ(bpinfo) NVME_GET(bpinfo, BPINFO_BPSZ)
#define NVME_BPINFO_BRS(bpinfo) NVME_GET(bpinfo, BPINFO_BRS)
#define NVME_BPINFO_ABPID(bpinfo) NVME_GET(bpinfo, BPINFO_ABPID)
enum nvme_bprsel {
NVME_BPRSEL_BPRSZ_SHIFT = 0,
NVME_BPRSEL_BPROF_SHIFT = 10,
NVME_BPRSEL_BPID_SHIFT = 31,
NVME_BPRSEL_BPRSZ_MASK = 0x3ff,
NVME_BPRSEL_BPROF_MASK = 0xfff,
NVME_BPRSEL_BPID_MASK = 0x1,
};
#define NVME_BPRSEL_BPRSZ(bprsel) NVME_GET(bprsel, BPRSEL_BPRSZ)
#define NVME_BPRSEL_BPROF(bprsel) NVME_GET(bprsel, BPRSEL_BPROF)
#define NVME_BPRSEL_BPID(bprsel) NVME_GET(bprsel, BPRSEL_BPID)
enum nvme_cmbmsc {
NVME_CMBMSC_CRE_SHIFT = 0,
NVME_CMBMSC_CMSE_SHIFT = 1,
NVME_CMBMSC_CBA_SHIFT = 12,
NVME_CMBMSC_CRE_MASK = 0x1,
NVME_CMBMSC_CMSE_MASK = 0x1,
};
static const __u64 NVME_CMBMSC_CBA_MASK = 0xfffffffffffffull;
#define NVME_CMBMSC_CRE(cmbmsc) NVME_GET(cmbmsc, CMBMSC_CRE)
#define NVME_CMBMSC_CMSE(cmbmsc) NVME_GET(cmbmsc, CMBMSC_CMSE)
#define NVME_CMBMSC_CBA(cmbmsc) NVME_GET(cmbmsc, CMBMSC_CBA)
enum nvme_cmbsts {
NVME_CMBSTS_CBAI_SHIFT = 0,
NVME_CMBSTS_CBAI_MASK = 0x1,
};
#define NVME_CMBSTS_CBAI(cmbsts) NVME_GET(cmbsts, CMBSTS_CBAI)
enum nvme_crto {
NVME_CRTO_CRIMT_SHIFT = 16,
NVME_CRTO_CRIMT_MASK = 0xffff0000,
NVME_CRTO_CRWMT_SHIFT = 0,
NVME_CRTO_CRWMT_MASK = 0x0000ffff,
};
#define NVME_CRTO_CRIMT(crto) NVME_GET(crto, CRTO_CRIMT)
#define NVME_CRTO_CRWMT(crto) NVME_GET(crto, CRTO_CRWMT)
enum nvme_pmrcap {
NVME_PMRCAP_RDS_SHIFT = 3,
NVME_PMRCAP_WDS_SHIFT = 4,
NVME_PMRCAP_BIR_SHIFT = 5,
NVME_PMRCAP_PMRTU_SHIFT = 8,
NVME_PMRCAP_PMRWMB_SHIFT = 10,
NVME_PMRCAP_PMRTO_SHIFT = 16,
NVME_PMRCAP_CMSS_SHIFT = 24,
NVME_PMRCAP_RDS_MASK = 0x1,
NVME_PMRCAP_WDS_MASK = 0x1,
NVME_PMRCAP_BIR_MASK = 0x7,
NVME_PMRCAP_PMRTU_MASK = 0x3,
NVME_PMRCAP_PMRWMB_MASK = 0xf,
NVME_PMRCAP_PMRTO_MASK = 0xff,
NVME_PMRCAP_CMSS_MASK = 0x1,
NVME_PMRCAP_PMRTU_500MS = 0,
NVME_PMRCAP_PMRTU_60S = 1,
};
#define NVME_PMRCAP_RDS(pmrcap) NVME_GET(pmrcap, PMRCAP_RDS)
#define NVME_PMRCAP_WDS(pmrcap) NVME_GET(pmrcap, PMRCAP_WDS)
#define NVME_PMRCAP_BIR(pmrcap) NVME_GET(pmrcap, PMRCAP_BIR)
#define NVME_PMRCAP_PMRTU(pmrcap) NVME_GET(pmrcap, PMRCAP_PMRTU)
#define NVME_PMRCAP_PMRWMB(pmrcap) NVME_GET(pmrcap, PMRCAP_PMRWMB)
#define NVME_PMRCAP_PMRTO(pmrcap) NVME_GET(pmrcap, PMRCAP_PMRTO)
#define NVME_PMRCAP_CMSS(pmrcap) NVME_GET(pmrcap, PMRCAP_CMSS)
enum nvme_pmrctl {
NVME_PMRCTL_EN_SHIFT = 0,
NVME_PMRCTL_EN_MASK = 0x1,
};
#define NVME_PMRCTL_EN(pmrctl) NVME_GET(pmrctl, PMRCTL_EN)
enum nvme_pmrsts {
NVME_PMRSTS_ERR_SHIFT = 0,
NVME_PMRSTS_NRDY_SHIFT = 8,
NVME_PMRSTS_HSTS_SHIFT = 9,
NVME_PMRSTS_CBAI_SHIFT = 12,
NVME_PMRSTS_ERR_MASK = 0xff,
NVME_PMRSTS_NRDY_MASK = 0x1,
NVME_PMRSTS_HSTS_MASK = 0x7,
NVME_PMRSTS_CBAI_MASK = 0x1,
};
#define NVME_PMRSTS_ERR(pmrsts) NVME_GET(pmrsts, PMRSTS_ERR)
#define NVME_PMRSTS_NRDY(pmrsts) NVME_GET(pmrsts, PMRSTS_NRDY)
#define NVME_PMRSTS_HSTS(pmrsts) NVME_GET(pmrsts, PMRSTS_HSTS)
#define NVME_PMRSTS_CBAI(pmrsts) NVME_GET(pmrsts, PMRSTS_CBAI)
enum nvme_pmrebs {
NVME_PMREBS_PMRSZU_SHIFT = 0,
NVME_PMREBS_RBB_SHIFT = 4,
NVME_PMREBS_PMRWBZ_SHIFT = 8,
NVME_PMREBS_PMRSZU_MASK = 0xf,
NVME_PMREBS_RBB_MASK = 0x1,
NVME_PMREBS_PMRWBZ_MASK = 0xffffff,
NVME_PMREBS_PMRSZU_B = 0,
NVME_PMREBS_PMRSZU_1K = 1,
NVME_PMREBS_PMRSZU_1M = 2,
NVME_PMREBS_PMRSZU_1G = 3,
};
#define NVME_PMREBS_PMRSZU(pmrebs) NVME_GET(pmrebs, PMREBS_PMRSZU)
#define NVME_PMREBS_RBB(pmrebs) NVME_GET(pmrebs, PMREBS_RBB)
#define NVME_PMREBS_PMRWBZ(pmrebs) NVME_GET(pmrebs, PMREBS_PMRWBZ)
/**
* nvme_pmr_size() - Calculate size of persistent memory region elasticity
* buffer
* @pmrebs: Value from controller register %NVME_REG_PMREBS
*
* Returns: size of controller persistent memory buffer in bytes
*/
static inline __u64 nvme_pmr_size(__u32 pmrebs)
{
return ((__u64)NVME_PMREBS_PMRWBZ(pmrebs)) *
(1ULL << (10 * NVME_PMREBS_PMRSZU(pmrebs)));
}
enum nvme_pmrswtp {
NVME_PMRSWTP_PMRSWTU_SHIFT = 0,
NVME_PMRSWTP_PMRSWTV_SHIFT = 8,
NVME_PMRSWTP_PMRSWTU_MASK = 0xf,
NVME_PMRSWTP_PMRSWTV_MASK = 0xffffff,
NVME_PMRSWTP_PMRSWTU_BPS = 0,
NVME_PMRSWTP_PMRSWTU_KBPS = 1,
NVME_PMRSWTP_PMRSWTU_MBPS = 2,
NVME_PMRSWTP_PMRSWTU_GBPS = 3,
};
#define NVME_PMRSWTP_PMRSWTU(pmrswtp) NVME_GET(pmrswtp, PMRSWTP_PMRSWTU)
#define NVME_PMRSWTP_PMRSWTV(pmrswtp) NVME_GET(pmrswtp, PMRSWTP_PMRSWTU)
/**
* nvme_pmr_throughput() - Calculate throughput of persistent memory buffer
* @pmrswtp: Value from controller register %NVME_REG_PMRSWTP
*
* Returns: throughput of controller persistent memory buffer in bytes/second
*/
static inline __u64 nvme_pmr_throughput(__u32 pmrswtp)
{
return ((__u64)NVME_PMRSWTP_PMRSWTV(pmrswtp)) *
(1ULL << (10 * NVME_PMRSWTP_PMRSWTU(pmrswtp)));
}
enum nvme_pmrmsc {
NVME_PMRMSC_CMSE_SHIFT = 1,
NVME_PMRMSC_CBA_SHIFT = 12,
NVME_PMRMSC_CMSE_MASK = 0x1,
};
static const __u64 NVME_PMRMSC_CBA_MASK = 0xfffffffffffffull;
#define NVME_PMRMSC_CMSE(pmrmsc) NVME_GET(pmrmsc, PMRMSC_CMSE)
#define NVME_PMRMSC_CBA(pmrmsc) NVME_GET(pmrmsc, PMRMSC_CBA)
/**
* enum nvme_psd_flags - Possible flag values in nvme power state descriptor
* @NVME_PSD_FLAGS_MXPS: Indicates the scale for the Maximum Power
* field. If this bit is cleared, then the scale of the
* Maximum Power field is in 0.01 Watts. If this bit is
* set, then the scale of the Maximum Power field is in
* 0.0001 Watts.
* @NVME_PSD_FLAGS_NOPS: Indicates whether the controller processes I/O
* commands in this power state. If this bit is cleared,
* then the controller processes I/O commands in this
* power state. If this bit is set, then the controller
* does not process I/O commands in this power state.
*/
enum nvme_psd_flags {
NVME_PSD_FLAGS_MXPS = 1 << 0,
NVME_PSD_FLAGS_NOPS = 1 << 1,
};
/**
* enum nvme_psd_ps - Known values for &struct nvme_psd %ips and %aps. Use with
* nvme_psd_power_scale() to extract the power scale field
* to match this enum.
* @NVME_PSD_PS_NOT_REPORTED: Not reported
* @NVME_PSD_PS_100_MICRO_WATT: 0.0001 watt scale
* @NVME_PSD_PS_10_MILLI_WATT: 0.01 watt scale
*/
enum nvme_psd_ps {
NVME_PSD_PS_NOT_REPORTED = 0,
NVME_PSD_PS_100_MICRO_WATT = 1,
NVME_PSD_PS_10_MILLI_WATT = 2,
};
/**
* nvme_psd_power_scale() - power scale occupies the upper 3 bits
* @ps: power scale value
*
* Returns: power scale value
*/
static inline unsigned int nvme_psd_power_scale(__u8 ps)
{
return ps >> 6;
}
/**
* enum nvme_psd_workload - Specifies a workload hint in the Power Management
* Feature (see &struct nvme_psd.apw) to inform the
* NVM subsystem or indicate the conditions for the
* active power level.
* @NVME_PSD_WORKLOAD_NP: The workload is unknown or not provided.
* @NVME_PSD_WORKLOAD_1: Extended Idle Period with a Burst of Random Write
* consists of five minutes of idle followed by
* thirty-two random write commands of size 1 MiB
* submitted to a single controller while all other
* controllers in the NVM subsystem are idle, and then
* thirty (30) seconds of idle.
* @NVME_PSD_WORKLOAD_2: Heavy Sequential Writes consists of 80,000
* sequential write commands of size 128 KiB submitted to
* a single controller while all other controllers in the
* NVM subsystem are idle. The submission queue(s)
* should be sufficiently large allowing the host to
* ensure there are multiple commands pending at all
* times during the workload.
*/
enum nvme_psd_workload {
NVME_PSD_WORKLOAD_NP = 0,
NVME_PSD_WORKLOAD_1 = 1,
NVME_PSD_WORKLOAD_2 = 2,
};
/**
* struct nvme_id_psd - Power Management data structure
* @mp: Maximum Power indicates the sustained maximum power consumed by the
* NVM subsystem in this power state. The power in Watts is equal to
* the value in this field multiplied by the scale specified in the Max
* Power Scale bit (see &enum nvme_psd_flags). A value of 0 indicates
* Maximum Power is not reported.
* @rsvd2: Reserved
* @flags: Additional decoding flags, see &enum nvme_psd_flags.
* @enlat: Entry Latency indicates the maximum latency in microseconds
* associated with entering this power state. A value of 0 indicates
* Entry Latency is not reported.
* @exlat: Exit Latency indicates the maximum latency in microseconds
* associated with exiting this power state. A value of 0 indicates
* Exit Latency is not reported.
* @rrt: Relative Read Throughput indicates the read throughput rank
* associated with this power state relative to others. The value in
* this is less than the number of supported power states.
* @rrl: Relative Read Latency indicates the read latency rank associated
* with this power state relative to others. The value in this field is
* less than the number of supported power states.
* @rwt: Relative Write Throughput indicates write throughput rank associated
* with this power state relative to others. The value in this field is
* less than the number of supported power states
* @rwl: Relative Write Latency indicates the write latency rank associated
* with this power state relative to others. The value in this field is
* less than the number of supported power states
* @idlp: Idle Power indicates the typical power consumed by the NVM
* subsystem over 30 seconds in this power state when idle.
* @ips: Idle Power Scale indicates the scale for &struct nvme_id_psd.idlp,
* see &enum nvme_psd_ps for decoding this field.
* @rsvd19: Reserved
* @actp: Active Power indicates the largest average power consumed by the
* NVM subsystem over a 10 second period in this power state with
* the workload indicated in the Active Power Workload field.
* @apws: Bits 7-6: Active Power Scale(APS) indicates the scale for the &struct
* nvme_id_psd.actp, see &enum nvme_psd_ps for decoding this value.
* Bits 2-0: Active Power Workload(APW) indicates the workload
* used to calculate maximum power for this power state.
* See &enum nvme_psd_workload for decoding this field.
* @rsvd23: Reserved
*/
struct nvme_id_psd {
__le16 mp;
__u8 rsvd2;
__u8 flags;
__le32 enlat;
__le32 exlat;
__u8 rrt;
__u8 rrl;
__u8 rwt;
__u8 rwl;
__le16 idlp;
__u8 ips;
__u8 rsvd19;
__le16 actp;
__u8 apws;
__u8 rsvd23[9];
};
/**
* struct nvme_id_ctrl - Identify Controller data structure
* @vid: PCI Vendor ID, the company vendor identifier that is assigned by
* the PCI SIG.
* @ssvid: PCI Subsystem Vendor ID, the company vendor identifier that is
* assigned by the PCI SIG for the subsystem.
* @sn: Serial Number in ASCII
* @mn: Model Number in ASCII
* @fr: Firmware Revision in ASCII, the currently active firmware
* revision for the NVM subsystem
* @rab: Recommended Arbitration Burst, reported as a power of two
* @ieee: IEEE assigned Organization Unique Identifier
* @cmic: Controller Multipath IO and Namespace Sharing Capabilities of
* the controller and NVM subsystem. See &enum nvme_id_ctrl_cmic.
* @mdts: Max Data Transfer Size is the largest data transfer size. The
* host should not submit a command that exceeds this maximum data
* transfer size. The value is in units of the minimum memory page
* size (CAP.MPSMIN) and is reported as a power of two
* @cntlid: Controller ID, the NVM subsystem unique controller identifier
* associated with the controller.
* @ver: Version, this field contains the value reported in the Version
* register, or property (see &enum nvme_registers %NVME_REG_VS).
* @rtd3r: RTD3 Resume Latency, the expected latency in microseconds to resume
* from Runtime D3
* @rtd3e: RTD3 Exit Latency, the typical latency in microseconds to enter
* Runtime D3.
* @oaes: Optional Async Events Supported, see @enum nvme_id_ctrl_oaes.
* @ctratt: Controller Attributes, see @enum nvme_id_ctrl_ctratt.
* @rrls: Read Recovery Levels. If a bit is set, then the corresponding
* Read Recovery Level is supported. If a bit is cleared, then the
* corresponding Read Recovery Level is not supported.
* @rsvd102: Reserved
* @cntrltype: Controller Type, see &enum nvme_id_ctrl_cntrltype
* @fguid: FRU GUID, a 128-bit value that is globally unique for a given
* Field Replaceable Unit
* @crdt1: Controller Retry Delay time in 100 millisecond units if CQE CRD
* field is 1
* @crdt2: Controller Retry Delay time in 100 millisecond units if CQE CRD
* field is 2
* @crdt3: Controller Retry Delay time in 100 millisecond units if CQE CRD
* field is 3
* @rsvd134: Reserved
* @nvmsr: NVM Subsystem Report, see &enum nvme_id_ctrl_nvmsr
* @vwci: VPD Write Cycle Information, see &enum nvme_id_ctrl_vwci
* @mec: Management Endpoint Capabilities, see &enum nvme_id_ctrl_mec
* @oacs: Optional Admin Command Support,the optional Admin commands and
* features supported by the controller, see &enum nvme_id_ctrl_oacs.
* @acl: Abort Command Limit, the maximum number of concurrently
* executing Abort commands supported by the controller. This is a
* 0's based value.
* @aerl: Async Event Request Limit, the maximum number of concurrently
* outstanding Asynchronous Event Request commands supported by the
* controller This is a 0's based value.
* @frmw: Firmware Updates indicates capabilities regarding firmware
* updates. See &enum nvme_id_ctrl_frmw.
* @lpa: Log Page Attributes, see &enum nvme_id_ctrl_lpa.
* @elpe: Error Log Page Entries, the maximum number of Error Information
* log entries that are stored by the controller. This field is a
* 0's based value.
* @npss: Number of Power States Supported, the number of NVM Express
* power states supported by the controller, indicating the number
* of valid entries in &struct nvme_id_ctrl.psd. This is a 0's
* based value.
* @avscc: Admin Vendor Specific Command Configuration, see
* &enum nvme_id_ctrl_avscc.
* @apsta: Autonomous Power State Transition Attributes, see
* &enum nvme_id_ctrl_apsta.
* @wctemp: Warning Composite Temperature Threshold indicates
* the minimum Composite Temperature field value (see &struct
* nvme_smart_log.critical_comp_time) that indicates an overheating
* condition during which controller operation continues.
* @cctemp: Critical Composite Temperature Threshold, field indicates the
* minimum Composite Temperature field value (see &struct
* nvme_smart_log.critical_comp_time) that indicates a critical
* overheating condition.
* @mtfa: Maximum Time for Firmware Activation indicates the maximum time
* the controller temporarily stops processing commands to activate
* the firmware image, specified in 100 millisecond units. This
* field is always valid if the controller supports firmware
* activation without a reset.
* @hmpre: Host Memory Buffer Preferred Size indicates the preferred size
* that the host is requested to allocate for the Host Memory
* Buffer feature in 4 KiB units.
* @hmmin: Host Memory Buffer Minimum Size indicates the minimum size that
* the host is requested to allocate for the Host Memory Buffer
* feature in 4 KiB units.
* @tnvmcap: Total NVM Capacity, the total NVM capacity in the NVM subsystem.
* The value is in bytes.
* @unvmcap: Unallocated NVM Capacity, the unallocated NVM capacity in the
* NVM subsystem. The value is in bytes.
* @rpmbs: Replay Protected Memory Block Support, see
* &enum nvme_id_ctrl_rpmbs.
* @edstt: Extended Device Self-test Time, if Device Self-test command is
* supported (see &struct nvme_id_ctrl.oacs, %NVME_CTRL_OACS_SELF_TEST),
* then this field indicates the nominal amount of time in one
* minute units that the controller takes to complete an extended
* device self-test operation when in power state 0.
* @dsto: Device Self-test Options, see &enum nvme_id_ctrl_dsto.
* @fwug: Firmware Update Granularity indicates the granularity and
* alignment requirement of the firmware image being updated by the
* Firmware Image Download command. The value is reported in 4 KiB
* units. A value of 0h indicates no information on granularity is
* provided. A value of FFh indicates no restriction
* @kas: Keep Alive Support indicates the granularity of the Keep Alive
* Timer in 100 millisecond units.
* @hctma: Host Controlled Thermal Management Attributes, see
* &enum nvme_id_ctrl_hctm.
* @mntmt: Minimum Thermal Management Temperature indicates the minimum
* temperature, in degrees Kelvin, that the host may request in the
* Thermal Management Temperature 1 field and Thermal Management
* Temperature 2 field of a Set Features command with the Feature
* Identifier field set to %NVME_FEAT_FID_HCTM.
* @mxtmt: Maximum Thermal Management Temperature indicates the maximum
* temperature, in degrees Kelvin, that the host may request in the
* Thermal Management Temperature 1 field and Thermal Management
* Temperature 2 field of the Set Features command with the Feature
* Identifier set to %NVME_FEAT_FID_HCTM.
* @sanicap: Sanitize Capabilities, see &enum nvme_id_ctrl_sanicap
* @hmminds: Host Memory Buffer Minimum Descriptor Entry Size indicates the
* minimum usable size of a Host Memory Buffer Descriptor Entry in
* 4 KiB units.
* @hmmaxd: Host Memory Maximum Descriptors Entries indicates the number of
* usable Host Memory Buffer Descriptor Entries.
* @nsetidmax: NVM Set Identifier Maximum, defines the maximum value of a valid
* NVM Set Identifier for any controller in the NVM subsystem.
* @endgidmax: Endurance Group Identifier Maximum, defines the maximum value of
* a valid Endurance Group Identifier for any controller in the NVM
* subsystem.
* @anatt: ANA Transition Time indicates the maximum amount of time, in
* seconds, for a transition between ANA states or the maximum
* amount of time, in seconds, that the controller reports the ANA
* change state.
* @anacap: Asymmetric Namespace Access Capabilities, see
* &enum nvme_id_ctrl_anacap.
* @anagrpmax: ANA Group Identifier Maximum indicates the maximum value of a
* valid ANA Group Identifier for any controller in the NVM
* subsystem.
* @nanagrpid: Number of ANA Group Identifiers indicates the number of ANA
* groups supported by this controller.
* @pels: Persistent Event Log Size indicates the maximum reportable size
* for the Persistent Event Log.
* @domainid: Domain Identifier indicates the identifier of the domain
* that contains this controller.
* @rsvd358: Reserved
* @megcap: Max Endurance Group Capacity indicates the maximum capacity
* of a single Endurance Group.
* @rsvd384: Reserved
* @sqes: Submission Queue Entry Size, see &enum nvme_id_ctrl_sqes.
* @cqes: Completion Queue Entry Size, see &enum nvme_id_ctrl_cqes.
* @maxcmd: Maximum Outstanding Commands indicates the maximum number of
* commands that the controller processes at one time for a
* particular queue.
* @nn: Number of Namespaces indicates the maximum value of a valid
* nsid for the NVM subsystem. If the MNAN (&struct nvme_id_ctrl.mnan
* field is cleared to 0h, then this field also indicates the
* maximum number of namespaces supported by the NVM subsystem.
* @oncs: Optional NVM Command Support, see &enum nvme_id_ctrl_oncs.
* @fuses: Fused Operation Support, see &enum nvme_id_ctrl_fuses.
* @fna: Format NVM Attributes, see &enum nvme_id_ctrl_fna.
* @vwc: Volatile Write Cache, see &enum nvme_id_ctrl_vwc.
* @awun: Atomic Write Unit Normal indicates the size of the write
* operation guaranteed to be written atomically to the NVM across
* all namespaces with any supported namespace format during normal
* operation. This field is specified in logical blocks and is a
* 0's based value.
* @awupf: Atomic Write Unit Power Fail indicates the size of the write
* operation guaranteed to be written atomically to the NVM across
* all namespaces with any supported namespace format during a
* power fail or error condition. This field is specified in
* logical blocks and is a 0’s based value.
* @icsvscc: NVM Vendor Specific Command Configuration, see
* &enum nvme_id_ctrl_nvscc.
* @nwpc: Namespace Write Protection Capabilities, see
* &enum nvme_id_ctrl_nwpc.
* @acwu: Atomic Compare & Write Unit indicates the size of the write
* operation guaranteed to be written atomically to the NVM across
* all namespaces with any supported namespace format for a Compare
* and Write fused operation. This field is specified in logical
* blocks and is a 0’s based value.
* @ocfs: Optional Copy Formats Supported, each bit n means controller
* supports Copy Format n.
* @sgls: SGL Support, see &enum nvme_id_ctrl_sgls
* @mnan: Maximum Number of Allowed Namespaces indicates the maximum
* number of namespaces supported by the NVM subsystem.
* @maxdna: Maximum Domain Namespace Attachments indicates the maximum
* of the sum of the number of namespaces attached to each I/O
* controller in the Domain.
* @maxcna: Maximum I/O Controller Namespace Attachments indicates the
* maximum number of namespaces that are allowed to be attached to
* this I/O controller.
* @rsvd564: Reserved
* @subnqn: NVM Subsystem NVMe Qualified Name, UTF-8 null terminated string
* @rsvd1024: Reserved
* @ioccsz: I/O Queue Command Capsule Supported Size, defines the maximum
* I/O command capsule size in 16 byte units.
* @iorcsz: I/O Queue Response Capsule Supported Size, defines the maximum
* I/O response capsule size in 16 byte units.
* @icdoff: In Capsule Data Offset, defines the offset where data starts
* within a capsule. This value is applicable to I/O Queues only.
* @fcatt: Fabrics Controller Attributes, see &enum nvme_id_ctrl_fcatt.
* @msdbd: Maximum SGL Data Block Descriptors indicates the maximum
* number of SGL Data Block or Keyed SGL Data Block descriptors
* that a host is allowed to place in a capsule. A value of 0h
* indicates no limit.
* @ofcs: Optional Fabric Commands Support, see &enum nvme_id_ctrl_ofcs.
* @dctype: Discovery Controller Type (DCTYPE). This field indicates what
* type of Discovery controller the controller is (see enum
* nvme_id_ctrl_dctype)
* @rsvd1807: Reserved
* @psd: Power State Descriptors, see &struct nvme_id_psd.
* @vs: Vendor Specific
*/
struct nvme_id_ctrl {
__le16 vid;
__le16 ssvid;
char sn[20];
char mn[40];
char fr[8];
__u8 rab;
__u8 ieee[3];
__u8 cmic;
__u8 mdts;
__le16 cntlid;
__le32 ver;
__le32 rtd3r;
__le32 rtd3e;
__le32 oaes;
__le32 ctratt;
__le16 rrls;
__u8 rsvd102[9];
__u8 cntrltype;
__u8 fguid[16];
__le16 crdt1;
__le16 crdt2;
__le16 crdt3;
__u8 rsvd134[119];
__u8 nvmsr;
__u8 vwci;
__u8 mec;
__le16 oacs;
__u8 acl;
__u8 aerl;
__u8 frmw;
__u8 lpa;
__u8 elpe;
__u8 npss;
__u8 avscc;
__u8 apsta;
__le16 wctemp;
__le16 cctemp;
__le16 mtfa;
__le32 hmpre;
__le32 hmmin;
__u8 tnvmcap[16];
__u8 unvmcap[16];
__le32 rpmbs;
__le16 edstt;
__u8 dsto;