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sam9x60.dtsi
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sam9x60.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC
*
* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
*
* Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
*/
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/mfd/atmel-flexcom.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Microchip SAM9X60 SoC";
compatible = "microchip,sam9x60";
interrupt-parent = <&aic>;
aliases {
serial0 = &dbgu;
gpio0 = &pioA;
gpio1 = &pioB;
gpio2 = &pioC;
gpio3 = &pioD;
tcb0 = &tcb0;
tcb1 = &tcb1;
};
cpus {
#address-cells = <0>;
#size-cells = <0>;
cpu {
compatible = "arm,arm926ej-s";
device_type = "cpu";
};
};
memory {
device_type = "memory";
reg = <0x20000000 0x10000000>;
};
clocks {
slow_xtal: slow_xtal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
main_xtal: main_xtal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
usb0: ohci@600000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00600000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
usb1: ehci@700000 {
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00700000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&upll>, <&uhphs_clk>;
clock-names = "usb_clk", "ehci_clk";
assigned-clocks = <&upll>;
assigned-clock-rates = <480000000>;
status = "disabled";
};
ebi: ebi@10000000 {
compatible = "microchip,sam9x60-ebi";
#address-cells = <2>;
#size-cells = <1>;
atmel,smc = <&smc>;
atmel,sfr = <&sfr>;
reg = <0x10000000 0x60000000>;
ranges = <0x0 0x0 0x10000000 0x10000000
0x1 0x0 0x20000000 0x10000000
0x2 0x0 0x30000000 0x10000000
0x3 0x0 0x40000000 0x10000000
0x4 0x0 0x50000000 0x10000000
0x5 0x0 0x60000000 0x10000000>;
clocks = <&mck>;
nand_controller: nand-controller {
compatible = "atmel,at91sam9g45-nand-controller";
ecc-engine = <&pmecc>;
#address-cells = <2>;
#size-cells = <1>;
ranges;
};
};
sdmmc0: sdio-host@80000000 {
compatible = "atmel,sama5d2-sdhci";
reg = <0x80000000 0x300>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&sdmmc0_clk>, <&sdmmc0_gclk>;
clock-names = "hclock", "multclk";
assigned-clocks = <&sdmmc0_gclk>;
assigned-clock-rates = <100000000>;
};
sdmmc1: sdio-host@90000000 {
compatible = "atmel,sama5d2-sdhci";
reg = <0x90000000 0x300>;
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&sdmmc1_clk>, <&sdmmc1_gclk>;
clock-names = "hclock", "multclk";
status = "disabled";
};
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
flx4: flexcom@f0000000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf0000000 0x200>;
clocks = <&flex4_clk>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf0000000 0x800>;
status = "disabled";
};
flx5: flexcom@f0004000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf0004000 0x200>;
clocks = <&flex5_clk>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf0004000 0x800>;
status = "disabled";
};
dma0: dma-controller@f0008000 {
compatible = "atmel,sama5d4-dma";
reg = <0xf0008000 0x1000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <1>;
clocks = <&dma0_clk>;
clock-names = "dma_clk";
};
ssc: ssc@f0010000 {
compatible = "atmel,at91sam9g45-ssc";
reg = <0xf0010000 0x4000>;
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(38))>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(39))>;
dma-names = "tx", "rx";
clocks = <&ssc_clk>;
clock-names = "pclk";
status = "disabled";
};
qspi: qspi@f0014000 {
compatible = "atmel,sama5d2-qspi";
reg = <0xf0014000 0x100>, <0x70000000 0x08000000>;
reg-names = "qspi_base", "qspi_mmap";
interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(26))>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(27))>;
dma-names = "tx", "rx";
clocks = <&qspi_ck>, <&qspi_clk>;
clock-names = "qspiclk", "pclk";
atmel,pmc = <&pmc>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2s: i2s@f001c000 {
compatible = "atmel,sama5d2-i2s";
reg = <0xf001c000 0x100>;
interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(36))>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(37))>;
dma-names = "tx", "rx";
clocks = <&i2s_clk>, <&i2s_gclk>;
clock-names = "pclk", "gclk";
assigned-clocks = <&i2smuxck>;
assigned-clock-parents = <&i2s_gclk>;
status = "disabled";
};
flx11: flexcom@f0020000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf0020000 0x200>;
clocks = <&flex11_clk>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf0020000 0x800>;
status = "disabled";
};
flx12: flexcom@f0024000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf0024000 0x200>;
clocks = <&flex12_clk>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf0024000 0x800>;
status = "disabled";
};
pit64b: timer@f0028000 {
compatible = "microchip,sam9x60-pit64";
reg = <0xf0028000 0x100>;
interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&pit64b_clk>;
};
sha@f002c000 {
compatible = "atmel,at91sam9g46-sha";
reg = <0xf002c000 0x100>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(34))>;
dma-names = "tx";
clocks = <&sha_clk>;
clock-names = "sha_clk";
status = "disabled";
};
trng@f0030000 {
compatible = "atmel,at91sam9g45-trng";
reg = <0xf0030000 0x100>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&trng_clk>;
status = "disabled";
};
aes@f0034000 {
compatible = "atmel,at91sam9g46-aes";
reg = <0xf0034000 0x100>;
interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(32))>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(33))>;
dma-names = "tx", "rx";
clocks = <&aes_clk>;
clock-names = "aes_clk";
status = "disabled";
};
tdes@f0038000 {
compatible = "atmel,at91sam9g46-tdes";
reg = <0xf0038000 0x100>;
interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(30))>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(31))>;
dma-names = "tx", "rx";
clocks = <&tdes_clk>;
clock-names = "tdes_clk";
status = "disabled";
};
classd: classd@f003c000 {
compatible = "atmel,sama5d2-classd";
reg = <0xf003c000 0x100>;
interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(35))>;
dma-names = "tx";
clocks = <&classd_clk>, <&classd_gclk>;
clock-names = "pclk", "gclk";
};
can0: can@f8000000 {
compatible = "atmel,at91sam9x5-can";
reg = <0xf8000000 0x300>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
clocks = <&mck>;
clock-names = "can_clk";
status = "disabled";
};
can1: can@f8004000 {
compatible = "atmel,at91sam9x5-can";
reg = <0xf8004000 0x300>;
interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
clocks = <&mck>;
clock-names = "can_clk";
status = "disabled";
};
tcb0: timer@f8008000 {
compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb0_clk>, <&slow_xtal>;
clock-names = "t0_clk", "slow_clk";
};
tcb1: timer@f800c000 {
compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
reg = <0xf800c000 0x100>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb1_clk>, <&slow_xtal>;
clock-names = "t0_clk", "slow_clk";
};
flx6: flexcom@f8010000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf8010000 0x200>;
clocks = <&flex6_clk>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf8010000 0x800>;
status = "disabled";
};
flx7: flexcom@f8014000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf8014000 0x200>;
clocks = <&flex7_clk>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf8014000 0x800>;
status = "disabled";
};
flx8: flexcom@f8018000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf8018000 0x200>;
clocks = <&flex8_clk>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf8018000 0x800>;
status = "disabled";
};
flx0: flexcom@f801c000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf801c000 0x200>;
clocks = <&flex0_clk>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf801c000 0x800>;
status = "disabled";
};
flx1: flexcom@f8020000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf8020000 0x200>;
clocks = <&flex1_clk>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf8020000 0x800>;
status = "disabled";
};
flx2: flexcom@f8024000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf8024000 0x200>;
clocks = <&flex2_clk>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf8024000 0x800>;
status = "disabled";
};
flx3: flexcom@f8028000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf8028000 0x200>;
clocks = <&flex3_clk>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf8028000 0x800>;
status = "disabled";
};
macb0: ethernet@f802c000 {
compatible = "cdns,sam9x60-macb", "cdns,macb";
reg = <0xf802c000 0x100>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
clocks = <&macb0_clk>, <&macb0_clk>;
clock-names = "hclk", "pclk";
};
macb1: ethernet@f8030000 {
compatible = "cdns,sam9x60-macb", "cdns,macb";
reg = <0xf8030000 0x100>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
clocks = <&macb1_clk>, <&macb1_clk>;
clock-names = "hclk", "pclk";
status = "disabled";
};
pwm0: pwm@f8034000 {
compatible = "atmel,at91sam9rl-pwm";
reg = <0xf8034000 0x300>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
clocks = <&pwm_clk>;
#pwm-cells = <3>;
};
hlcdc: hlcdc@f8038000 {
compatible = "microchip,sam9x60-hlcdc";
reg = <0xf8038000 0x4000>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&lcd_clk>, <&lcd_gclk>, <&td_slck>;
clock-names = "periph_clk","sys_clk", "slow_clk";
assigned-clocks = <&lcd_gclk>;
assigned-clock-parents = <&mck>;
hlcdc-display-controller {
compatible = "atmel,hlcdc-display-controller";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
};
hlcdc_pwm: hlcdc-pwm {
compatible = "atmel,hlcdc-pwm";
#pwm-cells = <3>;
};
};
usb2: gadget@f803c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "atmel,at91sam9g45-udc";
reg = <0x00500000 0x80000
0xf803c000 0x400>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&upll>, <&udphs_clk>;
clock-names = "hclk", "pclk";
status = "disabled";
ep@0 {
reg = <0>;
atmel,fifo-size = <64>;
atmel,nb-banks = <1>;
};
ep@1 {
reg = <1>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-dma;
atmel,can-isoc;
};
ep@2 {
reg = <2>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
atmel,can-dma;
atmel,can-isoc;
};
ep@3 {
reg = <3>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
ep@4 {
reg = <4>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
ep@5 {
reg = <5>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
atmel,can-isoc;
};
ep@6 {
reg = <6>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
atmel,can-isoc;
};
};
flx9: flexcom@f8040000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf8040000 0x200>;
clocks = <&flex9_clk>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf8040000 0x800>;
status = "disabled";
};
flx10: flexcom@f8044000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf8044000 0x200>;
clocks = <&flex10_clk>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf8044000 0x800>;
status = "disabled";
};
isi: isi@f8048000 {
compatible = "atmel,at91sam9g45-isi";
reg = <0xf8048000 0x4000>;
interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>;
clocks = <&mck>;
clock-names = "isi_clk";
status = "disabled";
port {
#address-cells = <1>;
#size-cells = <0>;
};
};
adc: adc@f804c000 {
compatible = "atmel,sama5d2-adc";
reg = <0xf804c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&adc_clk>;
clock-names = "adc_clk";
dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
dma-names = "rx";
atmel,min-sample-rate-hz = <200000>;
atmel,max-sample-rate-hz = <20000000>;
atmel,startup-time-ms = <4>;
atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
#io-channel-cells = <1>;
status = "disabled";
};
sfr: sfr@f8050000 {
compatible = "microchip,sam9x60-sfr", "syscon";
reg = <0xf8050000 0x60>;
};
matrix: matrix@ffffde00 {
compatible = "atmel,at91sam9x5-matrix", "syscon";
reg = <0xffffde00 0x100>;
};
pmecc: ecc-engine@ffffe000 {
compatible = "atmel,at91sam9g45-pmecc";
reg = <0xffffe000 0x600>,
<0xffffe600 0x200>,
<0x100000 0x100000>;
};
mpddrc: mpddrc@ffffe800 {
compatible = "atmel,sama5d3-ddramc";
reg = <0xffffe800 0x200>;
clocks = <&ddrck>, <&mck>;
clock-names = "ddrck", "mpddr";
};
smc: smc@ffffea00 {
compatible = "atmel,at91sam9260-smc", "syscon";
reg = <0xffffea00 0x200>;
};
aic: interrupt-controller@fffff100 {
compatible = "microchip,sam9x60-aic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0xfffff100 0x100>;
atmel,external-irqs = <31>;
};
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(28))>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(29))>;
dma-names = "tx", "rx";
clocks = <&dbgu_clk>;
clock-names = "usart";
};
pinctrl: pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x800>;
pioA: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
#gpio-lines = <26>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
};
pioD: gpio@fffffa00 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
#gpio-lines = <22>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioD_clk>;
};
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91sam9x5-pmc", "syscon";
reg = <0xfffffc00 0x200>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-controller;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
main_rc_osc: main_rc_osc {
compatible = "atmel,at91sam9x5-clk-main-rc-osc";
#clock-cells = <0>;
interrupt-parent = <&pmc>;
interrupts = <AT91_PMC_MOSCRCS>;
clock-frequency = <24000000>;
};
main_osc: main_osc {
compatible = "atmel,at91rm9200-clk-main-osc";
#clock-cells = <0>;
interrupt-parent = <&pmc>;
interrupts = <AT91_PMC_MOSCS>;
clocks = <&main_xtal>;
};
main: mainck {
compatible = "atmel,at91sam9x5-clk-main";
#clock-cells = <0>;
interrupt-parent = <&pmc>;
interrupts = <AT91_PMC_MOSCSELS>;
clocks = <&main_rc_osc>, <&main_osc>;
};
upll: upllck {
compatible = "microchip,sam9x60-clk-upll";
#clock-cells = <0>;
interrupt-parent = <&pmc>;
interrupts = <2>;
clocks = <&main_osc>;
reg = <1>;
atmel,clk-input-range = <8000000 48000000>;
#atmel,pll-clk-output-range-cells = <2>;
atmel,pll-clk-output-ranges = <300000000 500000000>;
};
plla: pllack {
compatible = "microchip,sam9x60-clk-pll";
#clock-cells = <0>;
interrupt-parent = <&pmc>;
interrupts = <1>;
clocks = <&main>;
reg = <0>;
atmel,clk-input-range = <8000000 24000000>;
#atmel,pll-clk-output-range-cells = <2>;
atmel,pll-clk-output-ranges = <31250 600000000>;
};
mck: masterck {
compatible = "atmel,at91sam9x5-clk-master";
#clock-cells = <0>;
interrupt-parent = <&pmc>;
interrupts = <AT91_PMC_MCKRDY>;
clocks = <&md_slck>, <&main>, <&plla>;
atmel,clk-output-range = <140000000 200000000>;
atmel,clk-divisors = <1 2 4 3>;
};
usb: usbck {
compatible = "atmel,at91sam9x5-clk-usb";
#clock-cells = <0>;
clocks = <&plla>, <&upll>;
};
prog: progck {
compatible = "microchip,sam9x60-clk-programmable";
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&pmc>;
clocks = <&md_slck>, <&td_slck>, <&main>, <&mck>;
prog0: prog0 {
#clock-cells = <0>;
reg = <0>;
interrupts = <AT91_PMC_PCKRDY(0)>;
};
prog1: prog1 {
#clock-cells = <0>;
reg = <1>;
interrupts = <AT91_PMC_PCKRDY(1)>;
};
prog2: prog2 {
#clock-cells = <0>;
reg = <2>;
interrupts = <AT91_PMC_PCKRDY(2)>;
};
prog3: prog3 {
#clock-cells = <0>;
reg = <3>;
interrupts = <AT91_PMC_PCKRDY(3)>;
};
prog4: prog4 {
#clock-cells = <0>;
reg = <4>;
interrupts = <AT91_PMC_PCKRDY(4)>;
};
prog5: prog5 {
#clock-cells = <0>;
reg = <5>;
interrupts = <AT91_PMC_PCKRDY(5)>;
};
prog6: prog6 {
#clock-cells = <0>;
reg = <6>;
interrupts = <AT91_PMC_PCKRDY(6)>;
};
prog7: prog7 {
#clock-cells = <0>;
reg = <7>;
interrupts = <AT91_PMC_PCKRDY(7)>;
};
};
systemck {
compatible = "atmel,at91rm9200-clk-system";
#address-cells = <1>;
#size-cells = <0>;
ddrck: ddrck {
#clock-cells = <0>;
reg = <3>;
clocks = <&mck>;
};
lcdck: lcdck {
#clock-cells = <0>;
reg = <4>;
clocks = <&mck>;
};
uhpck: uhpck {
#clock-cells = <0>;
reg = <6>;
clocks = <&usb>;
};
pck0: pck0 {
#clock-cells = <0>;
reg = <8>;
clocks = <&prog0>;
};
pck1: pck1 {
#clock-cells = <0>;
reg = <9>;
clocks = <&prog1>;
};
pck2: pck2 {
#clock-cells = <0>;
reg = <10>;
clocks = <&prog2>;
};
pck3: pck3 {
#clock-cells = <0>;
reg = <11>;
clocks = <&prog3>;
};
pck4: pck4 {
#clock-cells = <0>;
reg = <12>;
clocks = <&prog4>;
};
pck5: pck5 {
#clock-cells = <0>;
reg = <13>;
clocks = <&prog5>;
};
pck6: pck6 {
#clock-cells = <0>;
reg = <14>;
clocks = <&prog6>;
};
pck7: pck7 {
#clock-cells = <0>;
reg = <15>;
clocks = <&prog7>;
};
qspi_ck: qspi_ck {
#clock-cells = <0>;
reg = <19>;
clocks = <&mck>;
};
};
periphck {
compatible = "atmel,at91sam9x5-clk-peripheral";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mck>;
pioA_clk: pioA_clk {
#clock-cells = <0>;
reg = <2>;
};
pioB_clk: pioB_clk {
#clock-cells = <0>;
reg = <3>;
};
pioC_clk: pioC_clk {
#clock-cells = <0>;
reg = <4>;
};
flex0_clk: flex0_clk {
#clock-cells = <0>;
reg = <5>;
};
flex1_clk: flex1_clk {
#clock-cells = <0>;
reg = <6>;
};
flex2_clk: flex2_clk {
#clock-cells = <0>;
reg = <7>;
};
flex3_clk: flex3_clk {
reg = <8>;
#clock-cells = <0>;
};
flex6_clk: flex6_clk {
#clock-cells = <0>;
reg = <9>;
};
flex7_clk: flex7_clk {
#clock-cells = <0>;
reg = <10>;
};
flex8_clk: flex8_clk {
#clock-cells = <0>;
reg = <11>;
};
sdmmc0_clk: sdmmc0_clk {
#clock-cells = <0>;
reg = <12>;
};
flex4_clk: flex4_clk {
#clock-cells = <0>;
reg = <13>;
};
flex5_clk: flex5_clk {
#clock-cells = <0>;
reg = <14>;
};
flex9_clk: flex9_clk {
#clock-cells = <0>;
reg = <15>;
};
flex10_clk: flex10_clk {
#clock-cells = <0>;
reg = <16>;
};
tcb0_clk: tcb0_clk {
#clock-cells = <0>;
reg = <17>;
};
pwm_clk: pwm_clk {
#clock-cells = <0>;
reg = <18>;
};
adc_clk: adc_clk {
#clock-cells = <0>;
reg = <19>;
};
dma0_clk: dma0_clk {
#clock-cells = <0>;
reg = <20>;
};
matrix_clk: matrix_clk {
#clock-cells = <0>;
reg = <21>;
};