New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Section 3.2.1 "Typical CPU cache architecture": also explain TLB and prefetching #174

Open

kbeyls opened this issue Feb 21, 2023 · 0 comments

Labels

content

Member

kbeyls commented Feb 21, 2023

See TODO.

This would only be needed if later in the book a threat/exploit is explained that uses cache coherency mechanisms.

kbeyls added the content label

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment