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RISCVInstrInfoVPseudos.td
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RISCVInstrInfoVPseudos.td
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//===-- RISCVInstrInfoVPseudos.td - RISC-V 'V' Pseudos -----*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
///
/// This file contains the required infrastructure to support code generation
/// for the standard 'V' (Vector) extension, version 1.0.
///
/// This file is included from RISCVInstrInfoV.td
///
//===----------------------------------------------------------------------===//
def riscv_vmv_x_s : SDNode<"RISCVISD::VMV_X_S",
SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>,
SDTCisInt<1>]>>;
def riscv_read_vlenb : SDNode<"RISCVISD::READ_VLENB",
SDTypeProfile<1, 0, [SDTCisVT<0, XLenVT>]>>;
// Operand that is allowed to be a register or a 5 bit immediate.
// This allows us to pick between VSETIVLI and VSETVLI opcodes using the same
// pseudo instructions.
def AVL : RegisterOperand<GPRNoX0> {
let OperandNamespace = "RISCVOp";
let OperandType = "OPERAND_AVL";
}
// X0 has special meaning for vsetvl/vsetvli.
// rd | rs1 | AVL value | Effect on vl
//--------------------------------------------------------------
// !X0 | X0 | VLMAX | Set vl to VLMAX
// X0 | X0 | Value in vl | Keep current vl, just change vtype.
def VLOp : ComplexPattern<XLenVT, 1, "selectVLOp">;
def DecImm : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getSExtValue() - 1, SDLoc(N),
N->getValueType(0));
}]>;
defvar TAIL_UNDISTURBED_MASK_UNDISTURBED = 0;
defvar TAIL_AGNOSTIC = 1;
//===----------------------------------------------------------------------===//
// Utilities.
//===----------------------------------------------------------------------===//
class PseudoToVInst<string PseudoInst> {
string VInst = !subst("_M8", "",
!subst("_M4", "",
!subst("_M2", "",
!subst("_M1", "",
!subst("_MF2", "",
!subst("_MF4", "",
!subst("_MF8", "",
!subst("_B1", "",
!subst("_B2", "",
!subst("_B4", "",
!subst("_B8", "",
!subst("_B16", "",
!subst("_B32", "",
!subst("_B64", "",
!subst("_MASK", "",
!subst("_TIED", "",
!subst("_TU", "",
!subst("F16", "F",
!subst("F32", "F",
!subst("F64", "F",
!subst("Pseudo", "", PseudoInst)))))))))))))))))))));
}
// This class describes information associated to the LMUL.
class LMULInfo<int lmul, int oct, VReg regclass, VReg wregclass,
VReg f2regclass, VReg f4regclass, VReg f8regclass, string mx> {
bits<3> value = lmul; // This is encoded as the vlmul field of vtype.
VReg vrclass = regclass;
VReg wvrclass = wregclass;
VReg f8vrclass = f8regclass;
VReg f4vrclass = f4regclass;
VReg f2vrclass = f2regclass;
string MX = mx;
int octuple = oct;
}
// Associate LMUL with tablegen records of register classes.
def V_M1 : LMULInfo<0b000, 8, VR, VRM2, VR, VR, VR, "M1">;
def V_M2 : LMULInfo<0b001, 16, VRM2, VRM4, VR, VR, VR, "M2">;
def V_M4 : LMULInfo<0b010, 32, VRM4, VRM8, VRM2, VR, VR, "M4">;
def V_M8 : LMULInfo<0b011, 64, VRM8,/*NoVReg*/VR, VRM4, VRM2, VR, "M8">;
def V_MF8 : LMULInfo<0b101, 1, VR, VR,/*NoVReg*/VR,/*NoVReg*/VR,/*NoVReg*/VR, "MF8">;
def V_MF4 : LMULInfo<0b110, 2, VR, VR, VR,/*NoVReg*/VR,/*NoVReg*/VR, "MF4">;
def V_MF2 : LMULInfo<0b111, 4, VR, VR, VR, VR,/*NoVReg*/VR, "MF2">;
// Used to iterate over all possible LMULs.
defvar MxList = [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8];
// For floating point which don't need MF8.
defvar MxListF = [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8];
// Used for widening and narrowing instructions as it doesn't contain M8.
defvar MxListW = [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4];
// For floating point which don't need MF8.
defvar MxListFW = [V_MF4, V_MF2, V_M1, V_M2, V_M4];
// Use for zext/sext.vf2
defvar MxListVF2 = [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8];
// Use for zext/sext.vf4
defvar MxListVF4 = [V_MF2, V_M1, V_M2, V_M4, V_M8];
// Use for zext/sext.vf8
defvar MxListVF8 = [V_M1, V_M2, V_M4, V_M8];
class MxSet<int eew> {
list<LMULInfo> m = !cond(!eq(eew, 8) : [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],
!eq(eew, 16) : [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],
!eq(eew, 32) : [V_MF2, V_M1, V_M2, V_M4, V_M8],
!eq(eew, 64) : [V_M1, V_M2, V_M4, V_M8]);
}
class FPR_Info<RegisterClass regclass, string fx, list<LMULInfo> mxlist> {
RegisterClass fprclass = regclass;
string FX = fx;
list<LMULInfo> MxList = mxlist;
}
def SCALAR_F16 : FPR_Info<FPR16, "F16", MxSet<16>.m>;
def SCALAR_F32 : FPR_Info<FPR32, "F32", MxSet<32>.m>;
def SCALAR_F64 : FPR_Info<FPR64, "F64", MxSet<64>.m>;
defvar FPList = [SCALAR_F16, SCALAR_F32, SCALAR_F64];
// Used for widening instructions. It excludes F64.
defvar FPListW = [SCALAR_F16, SCALAR_F32];
class NFSet<LMULInfo m> {
list<int> L = !cond(!eq(m.value, V_M8.value): [],
!eq(m.value, V_M4.value): [2],
!eq(m.value, V_M2.value): [2, 3, 4],
true: [2, 3, 4, 5, 6, 7, 8]);
}
class log2<int num> {
int val = !if(!eq(num, 1), 0, !add(1, log2<!srl(num, 1)>.val));
}
class octuple_to_str<int octuple> {
string ret = !if(!eq(octuple, 1), "MF8",
!if(!eq(octuple, 2), "MF4",
!if(!eq(octuple, 4), "MF2",
!if(!eq(octuple, 8), "M1",
!if(!eq(octuple, 16), "M2",
!if(!eq(octuple, 32), "M4",
!if(!eq(octuple, 64), "M8",
"NoDef")))))));
}
def VLOpFrag : PatFrag<(ops), (XLenVT (VLOp (XLenVT AVL:$vl)))>;
// Output pattern for X0 used to represent VLMAX in the pseudo instructions.
// We can't use X0 register becuase the AVL operands use GPRNoX0.
// This must be kept in sync with RISCV::VLMaxSentinel.
def VLMax : OutPatFrag<(ops), (XLenVT -1)>;
// List of EEW.
defvar EEWList = [8, 16, 32, 64];
class SegRegClass<LMULInfo m, int nf> {
VReg RC = !cast<VReg>("VRN" # nf # !cond(!eq(m.value, V_MF8.value): V_M1.MX,
!eq(m.value, V_MF4.value): V_M1.MX,
!eq(m.value, V_MF2.value): V_M1.MX,
true: m.MX));
}
//===----------------------------------------------------------------------===//
// Vector register and vector group type information.
//===----------------------------------------------------------------------===//
class VTypeInfo<ValueType Vec, ValueType Mas, int Sew, VReg Reg, LMULInfo M,
ValueType Scal = XLenVT, RegisterClass ScalarReg = GPR>
{
ValueType Vector = Vec;
ValueType Mask = Mas;
int SEW = Sew;
int Log2SEW = log2<Sew>.val;
VReg RegClass = Reg;
LMULInfo LMul = M;
ValueType Scalar = Scal;
RegisterClass ScalarRegClass = ScalarReg;
// The pattern fragment which produces the AVL operand, representing the
// "natural" vector length for this type. For scalable vectors this is VLMax.
OutPatFrag AVL = VLMax;
string ScalarSuffix = !cond(!eq(Scal, XLenVT) : "X",
!eq(Scal, f16) : "F16",
!eq(Scal, f32) : "F32",
!eq(Scal, f64) : "F64");
}
class GroupVTypeInfo<ValueType Vec, ValueType VecM1, ValueType Mas, int Sew,
VReg Reg, LMULInfo M, ValueType Scal = XLenVT,
RegisterClass ScalarReg = GPR>
: VTypeInfo<Vec, Mas, Sew, Reg, M, Scal, ScalarReg>
{
ValueType VectorM1 = VecM1;
}
defset list<VTypeInfo> AllVectors = {
defset list<VTypeInfo> AllIntegerVectors = {
defset list<VTypeInfo> NoGroupIntegerVectors = {
defset list<VTypeInfo> FractionalGroupIntegerVectors = {
def VI8MF8: VTypeInfo<vint8mf8_t, vbool64_t, 8, VR, V_MF8>;
def VI8MF4: VTypeInfo<vint8mf4_t, vbool32_t, 8, VR, V_MF4>;
def VI8MF2: VTypeInfo<vint8mf2_t, vbool16_t, 8, VR, V_MF2>;
def VI16MF4: VTypeInfo<vint16mf4_t, vbool64_t, 16, VR, V_MF4>;
def VI16MF2: VTypeInfo<vint16mf2_t, vbool32_t, 16, VR, V_MF2>;
def VI32MF2: VTypeInfo<vint32mf2_t, vbool64_t, 32, VR, V_MF2>;
}
def VI8M1: VTypeInfo<vint8m1_t, vbool8_t, 8, VR, V_M1>;
def VI16M1: VTypeInfo<vint16m1_t, vbool16_t, 16, VR, V_M1>;
def VI32M1: VTypeInfo<vint32m1_t, vbool32_t, 32, VR, V_M1>;
def VI64M1: VTypeInfo<vint64m1_t, vbool64_t, 64, VR, V_M1>;
}
defset list<GroupVTypeInfo> GroupIntegerVectors = {
def VI8M2: GroupVTypeInfo<vint8m2_t, vint8m1_t, vbool4_t, 8, VRM2, V_M2>;
def VI8M4: GroupVTypeInfo<vint8m4_t, vint8m1_t, vbool2_t, 8, VRM4, V_M4>;
def VI8M8: GroupVTypeInfo<vint8m8_t, vint8m1_t, vbool1_t, 8, VRM8, V_M8>;
def VI16M2: GroupVTypeInfo<vint16m2_t,vint16m1_t,vbool8_t, 16,VRM2, V_M2>;
def VI16M4: GroupVTypeInfo<vint16m4_t,vint16m1_t,vbool4_t, 16,VRM4, V_M4>;
def VI16M8: GroupVTypeInfo<vint16m8_t,vint16m1_t,vbool2_t, 16,VRM8, V_M8>;
def VI32M2: GroupVTypeInfo<vint32m2_t,vint32m1_t,vbool16_t,32,VRM2, V_M2>;
def VI32M4: GroupVTypeInfo<vint32m4_t,vint32m1_t,vbool8_t, 32,VRM4, V_M4>;
def VI32M8: GroupVTypeInfo<vint32m8_t,vint32m1_t,vbool4_t, 32,VRM8, V_M8>;
def VI64M2: GroupVTypeInfo<vint64m2_t,vint64m1_t,vbool32_t,64,VRM2, V_M2>;
def VI64M4: GroupVTypeInfo<vint64m4_t,vint64m1_t,vbool16_t,64,VRM4, V_M4>;
def VI64M8: GroupVTypeInfo<vint64m8_t,vint64m1_t,vbool8_t, 64,VRM8, V_M8>;
}
}
defset list<VTypeInfo> AllFloatVectors = {
defset list<VTypeInfo> NoGroupFloatVectors = {
defset list<VTypeInfo> FractionalGroupFloatVectors = {
def VF16MF4: VTypeInfo<vfloat16mf4_t, vbool64_t, 16, VR, V_MF4, f16, FPR16>;
def VF16MF2: VTypeInfo<vfloat16mf2_t, vbool32_t, 16, VR, V_MF2, f16, FPR16>;
def VF32MF2: VTypeInfo<vfloat32mf2_t,vbool64_t, 32, VR, V_MF2, f32, FPR32>;
}
def VF16M1: VTypeInfo<vfloat16m1_t, vbool16_t, 16, VR, V_M1, f16, FPR16>;
def VF32M1: VTypeInfo<vfloat32m1_t, vbool32_t, 32, VR, V_M1, f32, FPR32>;
def VF64M1: VTypeInfo<vfloat64m1_t, vbool64_t, 64, VR, V_M1, f64, FPR64>;
}
defset list<GroupVTypeInfo> GroupFloatVectors = {
def VF16M2: GroupVTypeInfo<vfloat16m2_t, vfloat16m1_t, vbool8_t, 16,
VRM2, V_M2, f16, FPR16>;
def VF16M4: GroupVTypeInfo<vfloat16m4_t, vfloat16m1_t, vbool4_t, 16,
VRM4, V_M4, f16, FPR16>;
def VF16M8: GroupVTypeInfo<vfloat16m8_t, vfloat16m1_t, vbool2_t, 16,
VRM8, V_M8, f16, FPR16>;
def VF32M2: GroupVTypeInfo<vfloat32m2_t, vfloat32m1_t, vbool16_t, 32,
VRM2, V_M2, f32, FPR32>;
def VF32M4: GroupVTypeInfo<vfloat32m4_t, vfloat32m1_t, vbool8_t, 32,
VRM4, V_M4, f32, FPR32>;
def VF32M8: GroupVTypeInfo<vfloat32m8_t, vfloat32m1_t, vbool4_t, 32,
VRM8, V_M8, f32, FPR32>;
def VF64M2: GroupVTypeInfo<vfloat64m2_t, vfloat64m1_t, vbool32_t, 64,
VRM2, V_M2, f64, FPR64>;
def VF64M4: GroupVTypeInfo<vfloat64m4_t, vfloat64m1_t, vbool16_t, 64,
VRM4, V_M4, f64, FPR64>;
def VF64M8: GroupVTypeInfo<vfloat64m8_t, vfloat64m1_t, vbool8_t, 64,
VRM8, V_M8, f64, FPR64>;
}
}
}
// This functor is used to obtain the int vector type that has the same SEW and
// multiplier as the input parameter type
class GetIntVTypeInfo<VTypeInfo vti>
{
// Equivalent integer vector type. Eg.
// VI8M1 → VI8M1 (identity)
// VF64M4 → VI64M4
VTypeInfo Vti = !cast<VTypeInfo>(!subst("VF", "VI", !cast<string>(vti)));
}
class MTypeInfo<ValueType Mas, LMULInfo M, string Bx> {
ValueType Mask = Mas;
// {SEW, VLMul} values set a valid VType to deal with this mask type.
// we assume SEW=1 and set corresponding LMUL. vsetvli insertion will
// look for SEW=1 to optimize based on surrounding instructions.
int SEW = 1;
int Log2SEW = 0;
LMULInfo LMul = M;
string BX = Bx; // Appendix of mask operations.
// The pattern fragment which produces the AVL operand, representing the
// "natural" vector length for this mask type. For scalable masks this is
// VLMax.
OutPatFrag AVL = VLMax;
}
defset list<MTypeInfo> AllMasks = {
// vbool<n>_t, <n> = SEW/LMUL, we assume SEW=8 and corresponding LMUL.
def : MTypeInfo<vbool64_t, V_MF8, "B1">;
def : MTypeInfo<vbool32_t, V_MF4, "B2">;
def : MTypeInfo<vbool16_t, V_MF2, "B4">;
def : MTypeInfo<vbool8_t, V_M1, "B8">;
def : MTypeInfo<vbool4_t, V_M2, "B16">;
def : MTypeInfo<vbool2_t, V_M4, "B32">;
def : MTypeInfo<vbool1_t, V_M8, "B64">;
}
class VTypeInfoToWide<VTypeInfo vti, VTypeInfo wti>
{
VTypeInfo Vti = vti;
VTypeInfo Wti = wti;
}
class VTypeInfoToFraction<VTypeInfo vti, VTypeInfo fti>
{
VTypeInfo Vti = vti;
VTypeInfo Fti = fti;
}
defset list<VTypeInfoToWide> AllWidenableIntVectors = {
def : VTypeInfoToWide<VI8MF8, VI16MF4>;
def : VTypeInfoToWide<VI8MF4, VI16MF2>;
def : VTypeInfoToWide<VI8MF2, VI16M1>;
def : VTypeInfoToWide<VI8M1, VI16M2>;
def : VTypeInfoToWide<VI8M2, VI16M4>;
def : VTypeInfoToWide<VI8M4, VI16M8>;
def : VTypeInfoToWide<VI16MF4, VI32MF2>;
def : VTypeInfoToWide<VI16MF2, VI32M1>;
def : VTypeInfoToWide<VI16M1, VI32M2>;
def : VTypeInfoToWide<VI16M2, VI32M4>;
def : VTypeInfoToWide<VI16M4, VI32M8>;
def : VTypeInfoToWide<VI32MF2, VI64M1>;
def : VTypeInfoToWide<VI32M1, VI64M2>;
def : VTypeInfoToWide<VI32M2, VI64M4>;
def : VTypeInfoToWide<VI32M4, VI64M8>;
}
defset list<VTypeInfoToWide> AllWidenableFloatVectors = {
def : VTypeInfoToWide<VF16MF4, VF32MF2>;
def : VTypeInfoToWide<VF16MF2, VF32M1>;
def : VTypeInfoToWide<VF16M1, VF32M2>;
def : VTypeInfoToWide<VF16M2, VF32M4>;
def : VTypeInfoToWide<VF16M4, VF32M8>;
def : VTypeInfoToWide<VF32MF2, VF64M1>;
def : VTypeInfoToWide<VF32M1, VF64M2>;
def : VTypeInfoToWide<VF32M2, VF64M4>;
def : VTypeInfoToWide<VF32M4, VF64M8>;
}
defset list<VTypeInfoToFraction> AllFractionableVF2IntVectors = {
def : VTypeInfoToFraction<VI16MF4, VI8MF8>;
def : VTypeInfoToFraction<VI16MF2, VI8MF4>;
def : VTypeInfoToFraction<VI16M1, VI8MF2>;
def : VTypeInfoToFraction<VI16M2, VI8M1>;
def : VTypeInfoToFraction<VI16M4, VI8M2>;
def : VTypeInfoToFraction<VI16M8, VI8M4>;
def : VTypeInfoToFraction<VI32MF2, VI16MF4>;
def : VTypeInfoToFraction<VI32M1, VI16MF2>;
def : VTypeInfoToFraction<VI32M2, VI16M1>;
def : VTypeInfoToFraction<VI32M4, VI16M2>;
def : VTypeInfoToFraction<VI32M8, VI16M4>;
def : VTypeInfoToFraction<VI64M1, VI32MF2>;
def : VTypeInfoToFraction<VI64M2, VI32M1>;
def : VTypeInfoToFraction<VI64M4, VI32M2>;
def : VTypeInfoToFraction<VI64M8, VI32M4>;
}
defset list<VTypeInfoToFraction> AllFractionableVF4IntVectors = {
def : VTypeInfoToFraction<VI32MF2, VI8MF8>;
def : VTypeInfoToFraction<VI32M1, VI8MF4>;
def : VTypeInfoToFraction<VI32M2, VI8MF2>;
def : VTypeInfoToFraction<VI32M4, VI8M1>;
def : VTypeInfoToFraction<VI32M8, VI8M2>;
def : VTypeInfoToFraction<VI64M1, VI16MF4>;
def : VTypeInfoToFraction<VI64M2, VI16MF2>;
def : VTypeInfoToFraction<VI64M4, VI16M1>;
def : VTypeInfoToFraction<VI64M8, VI16M2>;
}
defset list<VTypeInfoToFraction> AllFractionableVF8IntVectors = {
def : VTypeInfoToFraction<VI64M1, VI8MF8>;
def : VTypeInfoToFraction<VI64M2, VI8MF4>;
def : VTypeInfoToFraction<VI64M4, VI8MF2>;
def : VTypeInfoToFraction<VI64M8, VI8M1>;
}
defset list<VTypeInfoToWide> AllWidenableIntToFloatVectors = {
def : VTypeInfoToWide<VI8MF8, VF16MF4>;
def : VTypeInfoToWide<VI8MF4, VF16MF2>;
def : VTypeInfoToWide<VI8MF2, VF16M1>;
def : VTypeInfoToWide<VI8M1, VF16M2>;
def : VTypeInfoToWide<VI8M2, VF16M4>;
def : VTypeInfoToWide<VI8M4, VF16M8>;
def : VTypeInfoToWide<VI16MF4, VF32MF2>;
def : VTypeInfoToWide<VI16MF2, VF32M1>;
def : VTypeInfoToWide<VI16M1, VF32M2>;
def : VTypeInfoToWide<VI16M2, VF32M4>;
def : VTypeInfoToWide<VI16M4, VF32M8>;
def : VTypeInfoToWide<VI32MF2, VF64M1>;
def : VTypeInfoToWide<VI32M1, VF64M2>;
def : VTypeInfoToWide<VI32M2, VF64M4>;
def : VTypeInfoToWide<VI32M4, VF64M8>;
}
// This class holds the record of the RISCVVPseudoTable below.
// This represents the information we need in codegen for each pseudo.
// The definition should be consistent with `struct PseudoInfo` in
// RISCVBaseInfo.h.
class CONST8b<bits<8> val> {
bits<8> V = val;
}
def InvalidIndex : CONST8b<0x80>;
class RISCVVPseudo {
Pseudo Pseudo = !cast<Pseudo>(NAME); // Used as a key.
Instruction BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
// The actual table.
def RISCVVPseudosTable : GenericTable {
let FilterClass = "RISCVVPseudo";
let CppTypeName = "PseudoInfo";
let Fields = [ "Pseudo", "BaseInstr" ];
let PrimaryKey = [ "Pseudo" ];
let PrimaryKeyName = "getPseudoInfo";
let PrimaryKeyEarlyOut = true;
}
def RISCVVIntrinsicsTable : GenericTable {
let FilterClass = "RISCVVIntrinsic";
let CppTypeName = "RISCVVIntrinsicInfo";
let Fields = ["IntrinsicID", "ScalarOperand", "VLOperand"];
let PrimaryKey = ["IntrinsicID"];
let PrimaryKeyName = "getRISCVVIntrinsicInfo";
}
class RISCVMaskedPseudo<bits<4> MaskIdx, bit HasTU = true> {
Pseudo MaskedPseudo = !cast<Pseudo>(NAME);
Pseudo UnmaskedPseudo = !cast<Pseudo>(!subst("_MASK", "", NAME));
Pseudo UnmaskedTUPseudo = !if(HasTU, !cast<Pseudo>(!subst("_MASK", "", NAME # "_TU")), MaskedPseudo);
bits<4> MaskOpIdx = MaskIdx;
}
def RISCVMaskedPseudosTable : GenericTable {
let FilterClass = "RISCVMaskedPseudo";
let CppTypeName = "RISCVMaskedPseudoInfo";
let Fields = ["MaskedPseudo", "UnmaskedPseudo", "UnmaskedTUPseudo", "MaskOpIdx"];
let PrimaryKey = ["MaskedPseudo"];
let PrimaryKeyName = "getMaskedPseudoInfo";
}
class RISCVVLE<bit M, bit TU, bit Str, bit F, bits<3> S, bits<3> L> {
bits<1> Masked = M;
bits<1> IsTU = TU;
bits<1> Strided = Str;
bits<1> FF = F;
bits<3> Log2SEW = S;
bits<3> LMUL = L;
Pseudo Pseudo = !cast<Pseudo>(NAME);
}
def RISCVVLETable : GenericTable {
let FilterClass = "RISCVVLE";
let CppTypeName = "VLEPseudo";
let Fields = ["Masked", "IsTU", "Strided", "FF", "Log2SEW", "LMUL", "Pseudo"];
let PrimaryKey = ["Masked", "IsTU", "Strided", "FF", "Log2SEW", "LMUL"];
let PrimaryKeyName = "getVLEPseudo";
}
class RISCVVSE<bit M, bit Str, bits<3> S, bits<3> L> {
bits<1> Masked = M;
bits<1> Strided = Str;
bits<3> Log2SEW = S;
bits<3> LMUL = L;
Pseudo Pseudo = !cast<Pseudo>(NAME);
}
def RISCVVSETable : GenericTable {
let FilterClass = "RISCVVSE";
let CppTypeName = "VSEPseudo";
let Fields = ["Masked", "Strided", "Log2SEW", "LMUL", "Pseudo"];
let PrimaryKey = ["Masked", "Strided", "Log2SEW", "LMUL"];
let PrimaryKeyName = "getVSEPseudo";
}
class RISCVVLX_VSX<bit M, bit TU, bit O, bits<3> S, bits<3> L, bits<3> IL> {
bits<1> Masked = M;
bits<1> IsTU = TU;
bits<1> Ordered = O;
bits<3> Log2SEW = S;
bits<3> LMUL = L;
bits<3> IndexLMUL = IL;
Pseudo Pseudo = !cast<Pseudo>(NAME);
}
class RISCVVLX<bit M, bit TU, bit O, bits<3> S, bits<3> L, bits<3> IL> :
RISCVVLX_VSX<M, TU, O, S, L, IL>;
class RISCVVSX<bit M, bit O, bits<3> S, bits<3> L, bits<3> IL> :
RISCVVLX_VSX<M, /*TU*/0, O, S, L, IL>;
class RISCVVLX_VSXTable : GenericTable {
let CppTypeName = "VLX_VSXPseudo";
let Fields = ["Masked", "IsTU", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"];
let PrimaryKey = ["Masked", "IsTU", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"];
}
def RISCVVLXTable : RISCVVLX_VSXTable {
let FilterClass = "RISCVVLX";
let PrimaryKeyName = "getVLXPseudo";
}
def RISCVVSXTable : RISCVVLX_VSXTable {
let FilterClass = "RISCVVSX";
let PrimaryKeyName = "getVSXPseudo";
}
class RISCVVLSEG<bits<4> N, bit M, bit TU, bit Str, bit F, bits<3> S, bits<3> L> {
bits<4> NF = N;
bits<1> Masked = M;
bits<1> IsTU = TU;
bits<1> Strided = Str;
bits<1> FF = F;
bits<3> Log2SEW = S;
bits<3> LMUL = L;
Pseudo Pseudo = !cast<Pseudo>(NAME);
}
def RISCVVLSEGTable : GenericTable {
let FilterClass = "RISCVVLSEG";
let CppTypeName = "VLSEGPseudo";
let Fields = ["NF", "Masked", "IsTU", "Strided", "FF", "Log2SEW", "LMUL", "Pseudo"];
let PrimaryKey = ["NF", "Masked", "IsTU", "Strided", "FF", "Log2SEW", "LMUL"];
let PrimaryKeyName = "getVLSEGPseudo";
}
class RISCVVLXSEG<bits<4> N, bit M, bit TU, bit O, bits<3> S, bits<3> L, bits<3> IL> {
bits<4> NF = N;
bits<1> Masked = M;
bits<1> IsTU = TU;
bits<1> Ordered = O;
bits<3> Log2SEW = S;
bits<3> LMUL = L;
bits<3> IndexLMUL = IL;
Pseudo Pseudo = !cast<Pseudo>(NAME);
}
def RISCVVLXSEGTable : GenericTable {
let FilterClass = "RISCVVLXSEG";
let CppTypeName = "VLXSEGPseudo";
let Fields = ["NF", "Masked", "IsTU", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"];
let PrimaryKey = ["NF", "Masked", "IsTU", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"];
let PrimaryKeyName = "getVLXSEGPseudo";
}
class RISCVVSSEG<bits<4> N, bit M, bit Str, bits<3> S, bits<3> L> {
bits<4> NF = N;
bits<1> Masked = M;
bits<1> Strided = Str;
bits<3> Log2SEW = S;
bits<3> LMUL = L;
Pseudo Pseudo = !cast<Pseudo>(NAME);
}
def RISCVVSSEGTable : GenericTable {
let FilterClass = "RISCVVSSEG";
let CppTypeName = "VSSEGPseudo";
let Fields = ["NF", "Masked", "Strided", "Log2SEW", "LMUL", "Pseudo"];
let PrimaryKey = ["NF", "Masked", "Strided", "Log2SEW", "LMUL"];
let PrimaryKeyName = "getVSSEGPseudo";
}
class RISCVVSXSEG<bits<4> N, bit M, bit O, bits<3> S, bits<3> L, bits<3> IL> {
bits<4> NF = N;
bits<1> Masked = M;
bits<1> Ordered = O;
bits<3> Log2SEW = S;
bits<3> LMUL = L;
bits<3> IndexLMUL = IL;
Pseudo Pseudo = !cast<Pseudo>(NAME);
}
def RISCVVSXSEGTable : GenericTable {
let FilterClass = "RISCVVSXSEG";
let CppTypeName = "VSXSEGPseudo";
let Fields = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL", "Pseudo"];
let PrimaryKey = ["NF", "Masked", "Ordered", "Log2SEW", "LMUL", "IndexLMUL"];
let PrimaryKeyName = "getVSXSEGPseudo";
}
//===----------------------------------------------------------------------===//
// Helpers to define the different pseudo instructions.
//===----------------------------------------------------------------------===//
// The destination vector register group for a masked vector instruction cannot
// overlap the source mask register (v0), unless the destination vector register
// is being written with a mask value (e.g., comparisons) or the scalar result
// of a reduction.
class GetVRegNoV0<VReg VRegClass> {
VReg R = !cond(!eq(VRegClass, VR) : VRNoV0,
!eq(VRegClass, VRM2) : VRM2NoV0,
!eq(VRegClass, VRM4) : VRM4NoV0,
!eq(VRegClass, VRM8) : VRM8NoV0,
!eq(VRegClass, VRN2M1) : VRN2M1NoV0,
!eq(VRegClass, VRN2M2) : VRN2M2NoV0,
!eq(VRegClass, VRN2M4) : VRN2M4NoV0,
!eq(VRegClass, VRN3M1) : VRN3M1NoV0,
!eq(VRegClass, VRN3M2) : VRN3M2NoV0,
!eq(VRegClass, VRN4M1) : VRN4M1NoV0,
!eq(VRegClass, VRN4M2) : VRN4M2NoV0,
!eq(VRegClass, VRN5M1) : VRN5M1NoV0,
!eq(VRegClass, VRN6M1) : VRN6M1NoV0,
!eq(VRegClass, VRN7M1) : VRN7M1NoV0,
!eq(VRegClass, VRN8M1) : VRN8M1NoV0,
true : VRegClass);
}
// Join strings in list using separator and ignoring empty elements
class Join<list<string> strings, string separator> {
string ret = !foldl(!head(strings), !tail(strings), a, b,
!cond(
!and(!empty(a), !empty(b)) : "",
!empty(a) : b,
!empty(b) : a,
1 : a#separator#b));
}
class VPseudo<Instruction instr, LMULInfo m, dag outs, dag ins> :
Pseudo<outs, ins, []>, RISCVVPseudo {
let BaseInstr = instr;
let VLMul = m.value;
}
class VPseudoUSLoadNoMask<VReg RetClass, int EEW, bit DummyMask = 1> :
Pseudo<(outs RetClass:$rd),
(ins GPR:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
RISCVVLE</*Masked*/0, /*TU*/0, /*Strided*/0, /*FF*/0, log2<EEW>.val, VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = DummyMask;
}
class VPseudoUSLoadNoMaskTU<VReg RetClass, int EEW> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPR:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
RISCVVLE</*Masked*/0, /*TU*/1, /*Strided*/0, /*FF*/0, log2<EEW>.val, VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = "$rd = $dest";
}
class VPseudoUSLoadMask<VReg RetClass, int EEW> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge,
GPR:$rs1,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>,
RISCVVPseudo,
RISCVVLE</*Masked*/1, /*TU*/1, /*Strided*/0, /*FF*/0, log2<EEW>.val, VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = "$rd = $merge";
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
}
class VPseudoUSLoadFFNoMask<VReg RetClass, int EEW, bit DummyMask = 1> :
Pseudo<(outs RetClass:$rd, GPR:$vl),
(ins GPR:$rs1, AVL:$avl, ixlenimm:$sew),[]>,
RISCVVPseudo,
RISCVVLE</*Masked*/0, /*TU*/0, /*Strided*/0, /*FF*/1, log2<EEW>.val, VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = DummyMask;
}
class VPseudoUSLoadFFNoMaskTU<VReg RetClass, int EEW> :
Pseudo<(outs RetClass:$rd, GPR:$vl),
(ins RetClass:$dest, GPR:$rs1, AVL:$avl, ixlenimm:$sew),[]>,
RISCVVPseudo,
RISCVVLE</*Masked*/0, /*TU*/1, /*Strided*/0, /*FF*/1, log2<EEW>.val, VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = "$rd = $dest";
}
class VPseudoUSLoadFFMask<VReg RetClass, int EEW> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
(ins GetVRegNoV0<RetClass>.R:$merge,
GPR:$rs1,
VMaskOp:$vm, AVL:$avl, ixlenimm:$sew, ixlenimm:$policy),[]>,
RISCVVPseudo,
RISCVVLE</*Masked*/1, /*TU*/1, /*Strided*/0, /*FF*/1, log2<EEW>.val, VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = "$rd = $merge";
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
}
class VPseudoSLoadNoMask<VReg RetClass, int EEW>:
Pseudo<(outs RetClass:$rd),
(ins GPR:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
RISCVVLE</*Masked*/0, /*TU*/0, /*Strided*/1, /*FF*/0, log2<EEW>.val, VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
}
class VPseudoSLoadNoMaskTU<VReg RetClass, int EEW>:
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPR:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
RISCVVLE</*Masked*/0, /*TU*/1, /*Strided*/1, /*FF*/0, log2<EEW>.val, VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = "$rd = $dest";
}
class VPseudoSLoadMask<VReg RetClass, int EEW>:
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge,
GPR:$rs1, GPR:$rs2,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>,
RISCVVPseudo,
RISCVVLE</*Masked*/1, /*TU*/1, /*Strided*/1, /*FF*/0, log2<EEW>.val, VLMul> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = "$rd = $merge";
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
}
class VPseudoILoadNoMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
bit Ordered, bit EarlyClobber>:
Pseudo<(outs RetClass:$rd),
(ins GPR:$rs1, IdxClass:$rs2, AVL:$vl,
ixlenimm:$sew),[]>,
RISCVVPseudo,
RISCVVLX</*Masked*/0, /*TU*/0, Ordered, log2<EEW>.val, VLMul, LMUL> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd", "");
}
class VPseudoILoadNoMaskTU<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
bit Ordered, bit EarlyClobber>:
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPR:$rs1, IdxClass:$rs2, AVL:$vl,
ixlenimm:$sew),[]>,
RISCVVPseudo,
RISCVVLX</*Masked*/0, /*TU*/1, Ordered, log2<EEW>.val, VLMul, LMUL> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
let HasMergeOp = 1;
let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd, $rd = $dest", "$rd = $dest");
}
class VPseudoILoadMask<VReg RetClass, VReg IdxClass, int EEW, bits<3> LMUL,
bit Ordered, bit EarlyClobber>:
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge,
GPR:$rs1, IdxClass:$rs2,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>,
RISCVVPseudo,
RISCVVLX</*Masked*/1, /*TU*/1, Ordered, log2<EEW>.val, VLMul, LMUL> {
let mayLoad = 1;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd, $rd = $merge", "$rd = $merge");
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
}
class VPseudoUSStoreNoMask<VReg StClass, int EEW, bit DummyMask = 1>:
Pseudo<(outs),
(ins StClass:$rd, GPR:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
RISCVVSE</*Masked*/0, /*Strided*/0, log2<EEW>.val, VLMul> {
let mayLoad = 0;
let mayStore = 1;
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = DummyMask;
}
class VPseudoUSStoreMask<VReg StClass, int EEW>:
Pseudo<(outs),
(ins StClass:$rd, GPR:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
RISCVVSE</*Masked*/1, /*Strided*/0, log2<EEW>.val, VLMul> {
let mayLoad = 0;
let mayStore = 1;
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
}
class VPseudoSStoreNoMask<VReg StClass, int EEW>:
Pseudo<(outs),
(ins StClass:$rd, GPR:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
RISCVVSE</*Masked*/0, /*Strided*/1, log2<EEW>.val, VLMul> {
let mayLoad = 0;
let mayStore = 1;
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
}
class VPseudoSStoreMask<VReg StClass, int EEW>:
Pseudo<(outs),
(ins StClass:$rd, GPR:$rs1, GPR:$rs2, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>,
RISCVVPseudo,
RISCVVSE</*Masked*/1, /*Strided*/1, log2<EEW>.val, VLMul> {
let mayLoad = 0;
let mayStore = 1;
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
}
// Unary instruction that is never masked so HasDummyMask=0.
class VPseudoUnaryNoDummyMask<VReg RetClass,
DAGOperand Op2Class> :
Pseudo<(outs RetClass:$rd),
(ins Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
}
class VPseudoUnaryNoDummyMaskTU<VReg RetClass,
DAGOperand Op2Class> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
let Constraints = "$rd = $dest";
}
class VPseudoNullaryNoMask<VReg RegClass>:
Pseudo<(outs RegClass:$rd),
(ins AVL:$vl, ixlenimm:$sew),
[]>, RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
}
class VPseudoNullaryNoMaskTU<VReg RegClass>:
Pseudo<(outs RegClass:$rd),
(ins RegClass:$merge, AVL:$vl, ixlenimm:$sew),
[]>, RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = "$rd = $merge";
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
let HasMergeOp = 1;
}
class VPseudoNullaryMask<VReg RegClass>:
Pseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
(ins GetVRegNoV0<RegClass>.R:$merge, VMaskOp:$vm, AVL:$vl,
ixlenimm:$sew, ixlenimm:$policy), []>, RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints ="$rd = $merge";
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
let UsesMaskPolicy = 1;
let HasVecPolicyOp = 1;
}
// Nullary for pseudo instructions. They are expanded in
// RISCVExpandPseudoInsts pass.
class VPseudoNullaryPseudoM<string BaseInst>
: Pseudo<(outs VR:$rd), (ins AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let HasVLOp = 1;
let HasSEWOp = 1;
// BaseInstr is not used in RISCVExpandPseudoInsts pass.
// Just fill a corresponding real v-inst to pass tablegen check.
let BaseInstr = !cast<Instruction>(BaseInst);
}
// RetClass could be GPR or VReg.
class VPseudoUnaryNoMask<DAGOperand RetClass, VReg OpClass, string Constraint = ""> :
Pseudo<(outs RetClass:$rd),
(ins OpClass:$rs2, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = Constraint;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
}
// RetClass could be GPR or VReg.
class VPseudoUnaryNoMaskTU<DAGOperand RetClass, VReg OpClass, string Constraint = ""> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$merge, OpClass:$rs2, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
let HasMergeOp = 1;
}
class VPseudoUnaryMask<VReg RetClass, VReg OpClass, string Constraint = ""> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,