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SIRegisterInfo.cpp
3175 lines (2794 loc) · 115 KB
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SIRegisterInfo.cpp
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//===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
/// \file
/// SI implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
#include "AMDGPU.h"
#include "AMDGPURegisterBankInfo.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUInstPrinter.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIMachineFunctionInfo.h"
#include "SIRegisterInfo.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
using namespace llvm;
#define GET_REGINFO_TARGET_DESC
#include "AMDGPUGenRegisterInfo.inc"
static cl::opt<bool> EnableSpillSGPRToVGPR(
"amdgpu-spill-sgpr-to-vgpr",
cl::desc("Enable spilling VGPRs to SGPRs"),
cl::ReallyHidden,
cl::init(true));
std::array<std::vector<int16_t>, 16> SIRegisterInfo::RegSplitParts;
std::array<std::array<uint16_t, 32>, 9> SIRegisterInfo::SubRegFromChannelTable;
// Map numbers of DWORDs to indexes in SubRegFromChannelTable.
// Valid indexes are shifted 1, such that a 0 mapping means unsupported.
// e.g. for 8 DWORDs (256-bit), SubRegFromChannelTableWidthMap[8] = 8,
// meaning index 7 in SubRegFromChannelTable.
static const std::array<unsigned, 17> SubRegFromChannelTableWidthMap = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 9};
namespace llvm {
// A temporary struct to spill SGPRs.
// This is mostly to spill SGPRs to memory. Spilling SGPRs into VGPR lanes emits
// just v_writelane and v_readlane.
//
// When spilling to memory, the SGPRs are written into VGPR lanes and the VGPR
// is saved to scratch (or the other way around for loads).
// For this, a VGPR is required where the needed lanes can be clobbered. The
// RegScavenger can provide a VGPR where currently active lanes can be
// clobbered, but we still need to save inactive lanes.
// The high-level steps are:
// - Try to scavenge SGPR(s) to save exec
// - Try to scavenge VGPR
// - Save needed, all or inactive lanes of a TmpVGPR
// - Spill/Restore SGPRs using TmpVGPR
// - Restore TmpVGPR
//
// To save all lanes of TmpVGPR, exec needs to be saved and modified. If we
// cannot scavenge temporary SGPRs to save exec, we use the following code:
// buffer_store_dword TmpVGPR ; only if active lanes need to be saved
// s_not exec, exec
// buffer_store_dword TmpVGPR ; save inactive lanes
// s_not exec, exec
struct SGPRSpillBuilder {
struct PerVGPRData {
unsigned PerVGPR;
unsigned NumVGPRs;
int64_t VGPRLanes;
};
// The SGPR to save
Register SuperReg;
MachineBasicBlock::iterator MI;
ArrayRef<int16_t> SplitParts;
unsigned NumSubRegs;
bool IsKill;
const DebugLoc &DL;
/* When spilling to stack */
// The SGPRs are written into this VGPR, which is then written to scratch
// (or vice versa for loads).
Register TmpVGPR = AMDGPU::NoRegister;
// Temporary spill slot to save TmpVGPR to.
int TmpVGPRIndex = 0;
// If TmpVGPR is live before the spill or if it is scavenged.
bool TmpVGPRLive = false;
// Scavenged SGPR to save EXEC.
Register SavedExecReg = AMDGPU::NoRegister;
// Stack index to write the SGPRs to.
int Index;
unsigned EltSize = 4;
RegScavenger *RS;
MachineBasicBlock *MBB;
MachineFunction &MF;
SIMachineFunctionInfo &MFI;
const SIInstrInfo &TII;
const SIRegisterInfo &TRI;
bool IsWave32;
Register ExecReg;
unsigned MovOpc;
unsigned NotOpc;
SGPRSpillBuilder(const SIRegisterInfo &TRI, const SIInstrInfo &TII,
bool IsWave32, MachineBasicBlock::iterator MI, int Index,
RegScavenger *RS)
: SGPRSpillBuilder(TRI, TII, IsWave32, MI, MI->getOperand(0).getReg(),
MI->getOperand(0).isKill(), Index, RS) {}
SGPRSpillBuilder(const SIRegisterInfo &TRI, const SIInstrInfo &TII,
bool IsWave32, MachineBasicBlock::iterator MI, Register Reg,
bool IsKill, int Index, RegScavenger *RS)
: SuperReg(Reg), MI(MI), IsKill(IsKill), DL(MI->getDebugLoc()),
Index(Index), RS(RS), MBB(MI->getParent()), MF(*MBB->getParent()),
MFI(*MF.getInfo<SIMachineFunctionInfo>()), TII(TII), TRI(TRI),
IsWave32(IsWave32) {
const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg);
SplitParts = TRI.getRegSplitParts(RC, EltSize);
NumSubRegs = SplitParts.empty() ? 1 : SplitParts.size();
if (IsWave32) {
ExecReg = AMDGPU::EXEC_LO;
MovOpc = AMDGPU::S_MOV_B32;
NotOpc = AMDGPU::S_NOT_B32;
} else {
ExecReg = AMDGPU::EXEC;
MovOpc = AMDGPU::S_MOV_B64;
NotOpc = AMDGPU::S_NOT_B64;
}
assert(SuperReg != AMDGPU::M0 && "m0 should never spill");
assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI &&
SuperReg != AMDGPU::EXEC && "exec should never spill");
}
PerVGPRData getPerVGPRData() {
PerVGPRData Data;
Data.PerVGPR = IsWave32 ? 32 : 64;
Data.NumVGPRs = (NumSubRegs + (Data.PerVGPR - 1)) / Data.PerVGPR;
Data.VGPRLanes = (1LL << std::min(Data.PerVGPR, NumSubRegs)) - 1LL;
return Data;
}
// Tries to scavenge SGPRs to save EXEC and a VGPR. Uses v0 if no VGPR is
// free.
// Writes these instructions if an SGPR can be scavenged:
// s_mov_b64 s[6:7], exec ; Save exec
// s_mov_b64 exec, 3 ; Wanted lanemask
// buffer_store_dword v1 ; Write scavenged VGPR to emergency slot
//
// Writes these instructions if no SGPR can be scavenged:
// buffer_store_dword v0 ; Only if no free VGPR was found
// s_not_b64 exec, exec
// buffer_store_dword v0 ; Save inactive lanes
// ; exec stays inverted, it is flipped back in
// ; restore.
void prepare() {
// Scavenged temporary VGPR to use. It must be scavenged once for any number
// of spilled subregs.
// FIXME: The liveness analysis is limited and does not tell if a register
// is in use in lanes that are currently inactive. We can never be sure if
// a register as actually in use in another lane, so we need to save all
// used lanes of the chosen VGPR.
assert(RS && "Cannot spill SGPR to memory without RegScavenger");
TmpVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0, false);
// Reserve temporary stack slot
TmpVGPRIndex = MFI.getScavengeFI(MF.getFrameInfo(), TRI);
if (TmpVGPR) {
// Found a register that is dead in the currently active lanes, we only
// need to spill inactive lanes.
TmpVGPRLive = false;
} else {
// Pick v0 because it doesn't make a difference.
TmpVGPR = AMDGPU::VGPR0;
TmpVGPRLive = true;
}
if (TmpVGPRLive) {
// We need to inform the scavenger that this index is already in use until
// we're done with the custom emergency spill.
RS->assignRegToScavengingIndex(TmpVGPRIndex, TmpVGPR);
}
// We may end up recursively calling the scavenger, and don't want to re-use
// the same register.
RS->setRegUsed(TmpVGPR);
// Try to scavenge SGPRs to save exec
assert(!SavedExecReg && "Exec is already saved, refuse to save again");
const TargetRegisterClass &RC =
IsWave32 ? AMDGPU::SGPR_32RegClass : AMDGPU::SGPR_64RegClass;
RS->setRegUsed(SuperReg);
SavedExecReg = RS->scavengeRegister(&RC, MI, 0, false);
int64_t VGPRLanes = getPerVGPRData().VGPRLanes;
if (SavedExecReg) {
RS->setRegUsed(SavedExecReg);
// Set exec to needed lanes
BuildMI(*MBB, MI, DL, TII.get(MovOpc), SavedExecReg).addReg(ExecReg);
auto I =
BuildMI(*MBB, MI, DL, TII.get(MovOpc), ExecReg).addImm(VGPRLanes);
if (!TmpVGPRLive)
I.addReg(TmpVGPR, RegState::ImplicitDefine);
// Spill needed lanes
TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ false);
} else {
// The modify and restore of exec clobber SCC, which we would have to save
// and restore. FIXME: We probably would need to reserve a register for
// this.
if (RS->isRegUsed(AMDGPU::SCC))
MI->emitError("unhandled SGPR spill to memory");
// Spill active lanes
if (TmpVGPRLive)
TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ false,
/*IsKill*/ false);
// Spill inactive lanes
auto I = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg);
if (!TmpVGPRLive)
I.addReg(TmpVGPR, RegState::ImplicitDefine);
I->getOperand(2).setIsDead(); // Mark SCC as dead.
TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ false);
}
}
// Writes these instructions if an SGPR can be scavenged:
// buffer_load_dword v1 ; Write scavenged VGPR to emergency slot
// s_waitcnt vmcnt(0) ; If a free VGPR was found
// s_mov_b64 exec, s[6:7] ; Save exec
//
// Writes these instructions if no SGPR can be scavenged:
// buffer_load_dword v0 ; Restore inactive lanes
// s_waitcnt vmcnt(0) ; If a free VGPR was found
// s_not_b64 exec, exec
// buffer_load_dword v0 ; Only if no free VGPR was found
void restore() {
if (SavedExecReg) {
// Restore used lanes
TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ true,
/*IsKill*/ false);
// Restore exec
auto I = BuildMI(*MBB, MI, DL, TII.get(MovOpc), ExecReg)
.addReg(SavedExecReg, RegState::Kill);
// Add an implicit use of the load so it is not dead.
// FIXME This inserts an unnecessary waitcnt
if (!TmpVGPRLive) {
I.addReg(TmpVGPR, RegState::ImplicitKill);
}
} else {
// Restore inactive lanes
TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ true,
/*IsKill*/ false);
auto I = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg);
if (!TmpVGPRLive)
I.addReg(TmpVGPR, RegState::ImplicitKill);
I->getOperand(2).setIsDead(); // Mark SCC as dead.
// Restore active lanes
if (TmpVGPRLive)
TRI.buildVGPRSpillLoadStore(*this, TmpVGPRIndex, 0, /*IsLoad*/ true);
}
// Inform the scavenger where we're releasing our custom scavenged register.
if (TmpVGPRLive) {
MachineBasicBlock::iterator RestorePt = std::prev(MI);
RS->assignRegToScavengingIndex(TmpVGPRIndex, TmpVGPR, &*RestorePt);
}
}
// Write TmpVGPR to memory or read TmpVGPR from memory.
// Either using a single buffer_load/store if exec is set to the needed mask
// or using
// buffer_load
// s_not exec, exec
// buffer_load
// s_not exec, exec
void readWriteTmpVGPR(unsigned Offset, bool IsLoad) {
if (SavedExecReg) {
// Spill needed lanes
TRI.buildVGPRSpillLoadStore(*this, Index, Offset, IsLoad);
} else {
// The modify and restore of exec clobber SCC, which we would have to save
// and restore. FIXME: We probably would need to reserve a register for
// this.
if (RS->isRegUsed(AMDGPU::SCC))
MI->emitError("unhandled SGPR spill to memory");
// Spill active lanes
TRI.buildVGPRSpillLoadStore(*this, Index, Offset, IsLoad,
/*IsKill*/ false);
// Spill inactive lanes
auto Not0 = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg);
Not0->getOperand(2).setIsDead(); // Mark SCC as dead.
TRI.buildVGPRSpillLoadStore(*this, Index, Offset, IsLoad);
auto Not1 = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg);
Not1->getOperand(2).setIsDead(); // Mark SCC as dead.
}
}
void setMI(MachineBasicBlock *NewMBB, MachineBasicBlock::iterator NewMI) {
assert(MBB->getParent() == &MF);
MI = NewMI;
MBB = NewMBB;
}
};
} // namespace llvm
SIRegisterInfo::SIRegisterInfo(const GCNSubtarget &ST)
: AMDGPUGenRegisterInfo(AMDGPU::PC_REG, ST.getAMDGPUDwarfFlavour()), ST(ST),
SpillSGPRToVGPR(EnableSpillSGPRToVGPR), isWave32(ST.isWave32()) {
assert(getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() == 3 &&
getSubRegIndexLaneMask(AMDGPU::sub31).getAsInteger() == (3ULL << 62) &&
(getSubRegIndexLaneMask(AMDGPU::lo16) |
getSubRegIndexLaneMask(AMDGPU::hi16)).getAsInteger() ==
getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() &&
"getNumCoveredRegs() will not work with generated subreg masks!");
RegPressureIgnoredUnits.resize(getNumRegUnits());
RegPressureIgnoredUnits.set(
*MCRegUnitIterator(MCRegister::from(AMDGPU::M0), this));
for (auto Reg : AMDGPU::VGPR_HI16RegClass)
RegPressureIgnoredUnits.set(*MCRegUnitIterator(Reg, this));
// HACK: Until this is fully tablegen'd.
static llvm::once_flag InitializeRegSplitPartsFlag;
static auto InitializeRegSplitPartsOnce = [this]() {
for (unsigned Idx = 1, E = getNumSubRegIndices() - 1; Idx < E; ++Idx) {
unsigned Size = getSubRegIdxSize(Idx);
if (Size & 31)
continue;
std::vector<int16_t> &Vec = RegSplitParts[Size / 32 - 1];
unsigned Pos = getSubRegIdxOffset(Idx);
if (Pos % Size)
continue;
Pos /= Size;
if (Vec.empty()) {
unsigned MaxNumParts = 1024 / Size; // Maximum register is 1024 bits.
Vec.resize(MaxNumParts);
}
Vec[Pos] = Idx;
}
};
static llvm::once_flag InitializeSubRegFromChannelTableFlag;
static auto InitializeSubRegFromChannelTableOnce = [this]() {
for (auto &Row : SubRegFromChannelTable)
Row.fill(AMDGPU::NoSubRegister);
for (unsigned Idx = 1; Idx < getNumSubRegIndices(); ++Idx) {
unsigned Width = AMDGPUSubRegIdxRanges[Idx].Size / 32;
unsigned Offset = AMDGPUSubRegIdxRanges[Idx].Offset / 32;
assert(Width < SubRegFromChannelTableWidthMap.size());
Width = SubRegFromChannelTableWidthMap[Width];
if (Width == 0)
continue;
unsigned TableIdx = Width - 1;
assert(TableIdx < SubRegFromChannelTable.size());
assert(Offset < SubRegFromChannelTable[TableIdx].size());
SubRegFromChannelTable[TableIdx][Offset] = Idx;
}
};
llvm::call_once(InitializeRegSplitPartsFlag, InitializeRegSplitPartsOnce);
llvm::call_once(InitializeSubRegFromChannelTableFlag,
InitializeSubRegFromChannelTableOnce);
}
void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved,
MCRegister Reg) const {
MCRegAliasIterator R(Reg, this, true);
for (; R.isValid(); ++R)
Reserved.set(*R);
}
// Forced to be here by one .inc
const MCPhysReg *SIRegisterInfo::getCalleeSavedRegs(
const MachineFunction *MF) const {
CallingConv::ID CC = MF->getFunction().getCallingConv();
switch (CC) {
case CallingConv::C:
case CallingConv::Fast:
case CallingConv::Cold:
return ST.hasGFX90AInsts() ? CSR_AMDGPU_GFX90AInsts_SaveList
: CSR_AMDGPU_SaveList;
case CallingConv::AMDGPU_Gfx:
return ST.hasGFX90AInsts() ? CSR_AMDGPU_SI_Gfx_GFX90AInsts_SaveList
: CSR_AMDGPU_SI_Gfx_SaveList;
default: {
// Dummy to not crash RegisterClassInfo.
static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
return &NoCalleeSavedReg;
}
}
}
const MCPhysReg *
SIRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const {
return nullptr;
}
const uint32_t *SIRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
CallingConv::ID CC) const {
switch (CC) {
case CallingConv::C:
case CallingConv::Fast:
case CallingConv::Cold:
return ST.hasGFX90AInsts() ? CSR_AMDGPU_GFX90AInsts_RegMask
: CSR_AMDGPU_RegMask;
case CallingConv::AMDGPU_Gfx:
return ST.hasGFX90AInsts() ? CSR_AMDGPU_SI_Gfx_GFX90AInsts_RegMask
: CSR_AMDGPU_SI_Gfx_RegMask;
default:
return nullptr;
}
}
const uint32_t *SIRegisterInfo::getNoPreservedMask() const {
return CSR_AMDGPU_NoRegs_RegMask;
}
const TargetRegisterClass *
SIRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
const MachineFunction &MF) const {
// FIXME: Should have a helper function like getEquivalentVGPRClass to get the
// equivalent AV class. If used one, the verifier will crash after
// RegBankSelect in the GISel flow. The aligned regclasses are not fully given
// until Instruction selection.
if (ST.hasMAIInsts() && (isVGPRClass(RC) || isAGPRClass(RC))) {
if (RC == &AMDGPU::VGPR_32RegClass || RC == &AMDGPU::AGPR_32RegClass)
return &AMDGPU::AV_32RegClass;
if (RC == &AMDGPU::VReg_64RegClass || RC == &AMDGPU::AReg_64RegClass)
return &AMDGPU::AV_64RegClass;
if (RC == &AMDGPU::VReg_64_Align2RegClass ||
RC == &AMDGPU::AReg_64_Align2RegClass)
return &AMDGPU::AV_64_Align2RegClass;
if (RC == &AMDGPU::VReg_96RegClass || RC == &AMDGPU::AReg_96RegClass)
return &AMDGPU::AV_96RegClass;
if (RC == &AMDGPU::VReg_96_Align2RegClass ||
RC == &AMDGPU::AReg_96_Align2RegClass)
return &AMDGPU::AV_96_Align2RegClass;
if (RC == &AMDGPU::VReg_128RegClass || RC == &AMDGPU::AReg_128RegClass)
return &AMDGPU::AV_128RegClass;
if (RC == &AMDGPU::VReg_128_Align2RegClass ||
RC == &AMDGPU::AReg_128_Align2RegClass)
return &AMDGPU::AV_128_Align2RegClass;
if (RC == &AMDGPU::VReg_160RegClass || RC == &AMDGPU::AReg_160RegClass)
return &AMDGPU::AV_160RegClass;
if (RC == &AMDGPU::VReg_160_Align2RegClass ||
RC == &AMDGPU::AReg_160_Align2RegClass)
return &AMDGPU::AV_160_Align2RegClass;
if (RC == &AMDGPU::VReg_192RegClass || RC == &AMDGPU::AReg_192RegClass)
return &AMDGPU::AV_192RegClass;
if (RC == &AMDGPU::VReg_192_Align2RegClass ||
RC == &AMDGPU::AReg_192_Align2RegClass)
return &AMDGPU::AV_192_Align2RegClass;
if (RC == &AMDGPU::VReg_256RegClass || RC == &AMDGPU::AReg_256RegClass)
return &AMDGPU::AV_256RegClass;
if (RC == &AMDGPU::VReg_256_Align2RegClass ||
RC == &AMDGPU::AReg_256_Align2RegClass)
return &AMDGPU::AV_256_Align2RegClass;
if (RC == &AMDGPU::VReg_512RegClass || RC == &AMDGPU::AReg_512RegClass)
return &AMDGPU::AV_512RegClass;
if (RC == &AMDGPU::VReg_512_Align2RegClass ||
RC == &AMDGPU::AReg_512_Align2RegClass)
return &AMDGPU::AV_512_Align2RegClass;
if (RC == &AMDGPU::VReg_1024RegClass || RC == &AMDGPU::AReg_1024RegClass)
return &AMDGPU::AV_1024RegClass;
if (RC == &AMDGPU::VReg_1024_Align2RegClass ||
RC == &AMDGPU::AReg_1024_Align2RegClass)
return &AMDGPU::AV_1024_Align2RegClass;
}
return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF);
}
Register SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const SIFrameLowering *TFI = ST.getFrameLowering();
const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
// During ISel lowering we always reserve the stack pointer in entry
// functions, but never actually want to reference it when accessing our own
// frame. If we need a frame pointer we use it, but otherwise we can just use
// an immediate "0" which we represent by returning NoRegister.
if (FuncInfo->isEntryFunction()) {
return TFI->hasFP(MF) ? FuncInfo->getFrameOffsetReg() : Register();
}
return TFI->hasFP(MF) ? FuncInfo->getFrameOffsetReg()
: FuncInfo->getStackPtrOffsetReg();
}
bool SIRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
// When we need stack realignment, we can't reference off of the
// stack pointer, so we reserve a base pointer.
const MachineFrameInfo &MFI = MF.getFrameInfo();
return MFI.getNumFixedObjects() && shouldRealignStack(MF);
}
Register SIRegisterInfo::getBaseRegister() const { return AMDGPU::SGPR34; }
const uint32_t *SIRegisterInfo::getAllVGPRRegMask() const {
return AMDGPU_AllVGPRs_RegMask;
}
const uint32_t *SIRegisterInfo::getAllAGPRRegMask() const {
return AMDGPU_AllAGPRs_RegMask;
}
const uint32_t *SIRegisterInfo::getAllVectorRegMask() const {
return AMDGPU_AllVectorRegs_RegMask;
}
const uint32_t *SIRegisterInfo::getAllAllocatableSRegMask() const {
return AMDGPU_AllAllocatableSRegs_RegMask;
}
unsigned SIRegisterInfo::getSubRegFromChannel(unsigned Channel,
unsigned NumRegs) {
assert(NumRegs < SubRegFromChannelTableWidthMap.size());
unsigned NumRegIndex = SubRegFromChannelTableWidthMap[NumRegs];
assert(NumRegIndex && "Not implemented");
assert(Channel < SubRegFromChannelTable[NumRegIndex - 1].size());
return SubRegFromChannelTable[NumRegIndex - 1][Channel];
}
MCRegister SIRegisterInfo::reservedPrivateSegmentBufferReg(
const MachineFunction &MF) const {
unsigned BaseIdx = alignDown(ST.getMaxNumSGPRs(MF), 4) - 4;
MCRegister BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx));
return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SGPR_128RegClass);
}
BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
Reserved.set(AMDGPU::MODE);
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
// Reserve special purpose registers.
//
// EXEC_LO and EXEC_HI could be allocated and used as regular register, but
// this seems likely to result in bugs, so I'm marking them as reserved.
reserveRegisterTuples(Reserved, AMDGPU::EXEC);
reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR);
// M0 has to be reserved so that llvm accepts it as a live-in into a block.
reserveRegisterTuples(Reserved, AMDGPU::M0);
// Reserve src_vccz, src_execz, src_scc.
reserveRegisterTuples(Reserved, AMDGPU::SRC_VCCZ);
reserveRegisterTuples(Reserved, AMDGPU::SRC_EXECZ);
reserveRegisterTuples(Reserved, AMDGPU::SRC_SCC);
// Reserve the memory aperture registers
reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_BASE);
reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_LIMIT);
reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_BASE);
reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_LIMIT);
// Reserve src_pops_exiting_wave_id - support is not implemented in Codegen.
reserveRegisterTuples(Reserved, AMDGPU::SRC_POPS_EXITING_WAVE_ID);
// Reserve xnack_mask registers - support is not implemented in Codegen.
reserveRegisterTuples(Reserved, AMDGPU::XNACK_MASK);
// Reserve lds_direct register - support is not implemented in Codegen.
reserveRegisterTuples(Reserved, AMDGPU::LDS_DIRECT);
// Reserve Trap Handler registers - support is not implemented in Codegen.
reserveRegisterTuples(Reserved, AMDGPU::TBA);
reserveRegisterTuples(Reserved, AMDGPU::TMA);
reserveRegisterTuples(Reserved, AMDGPU::TTMP0_TTMP1);
reserveRegisterTuples(Reserved, AMDGPU::TTMP2_TTMP3);
reserveRegisterTuples(Reserved, AMDGPU::TTMP4_TTMP5);
reserveRegisterTuples(Reserved, AMDGPU::TTMP6_TTMP7);
reserveRegisterTuples(Reserved, AMDGPU::TTMP8_TTMP9);
reserveRegisterTuples(Reserved, AMDGPU::TTMP10_TTMP11);
reserveRegisterTuples(Reserved, AMDGPU::TTMP12_TTMP13);
reserveRegisterTuples(Reserved, AMDGPU::TTMP14_TTMP15);
// Reserve null register - it shall never be allocated
reserveRegisterTuples(Reserved, AMDGPU::SGPR_NULL64);
// Disallow vcc_hi allocation in wave32. It may be allocated but most likely
// will result in bugs.
if (isWave32) {
Reserved.set(AMDGPU::VCC);
Reserved.set(AMDGPU::VCC_HI);
}
// Reserve SGPRs.
//
unsigned MaxNumSGPRs = ST.getMaxNumSGPRs(MF);
unsigned TotalNumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
for (unsigned i = MaxNumSGPRs; i < TotalNumSGPRs; ++i) {
unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i);
reserveRegisterTuples(Reserved, Reg);
}
for (auto Reg : AMDGPU::SReg_32RegClass) {
Reserved.set(getSubReg(Reg, AMDGPU::hi16));
Register Low = getSubReg(Reg, AMDGPU::lo16);
// This is to prevent BB vcc liveness errors.
if (!AMDGPU::SGPR_LO16RegClass.contains(Low))
Reserved.set(Low);
}
Register ScratchRSrcReg = MFI->getScratchRSrcReg();
if (ScratchRSrcReg != AMDGPU::NoRegister) {
// Reserve 4 SGPRs for the scratch buffer resource descriptor in case we
// need to spill.
// TODO: May need to reserve a VGPR if doing LDS spilling.
reserveRegisterTuples(Reserved, ScratchRSrcReg);
}
// We have to assume the SP is needed in case there are calls in the function,
// which is detected after the function is lowered. If we aren't really going
// to need SP, don't bother reserving it.
MCRegister StackPtrReg = MFI->getStackPtrOffsetReg();
if (StackPtrReg) {
reserveRegisterTuples(Reserved, StackPtrReg);
assert(!isSubRegister(ScratchRSrcReg, StackPtrReg));
}
MCRegister FrameReg = MFI->getFrameOffsetReg();
if (FrameReg) {
reserveRegisterTuples(Reserved, FrameReg);
assert(!isSubRegister(ScratchRSrcReg, FrameReg));
}
if (hasBasePointer(MF)) {
MCRegister BasePtrReg = getBaseRegister();
reserveRegisterTuples(Reserved, BasePtrReg);
assert(!isSubRegister(ScratchRSrcReg, BasePtrReg));
}
// Reserve VGPRs/AGPRs.
//
unsigned MaxNumVGPRs = ST.getMaxNumVGPRs(MF);
unsigned MaxNumAGPRs = MaxNumVGPRs;
unsigned TotalNumVGPRs = AMDGPU::VGPR_32RegClass.getNumRegs();
// Reserve all the AGPRs if there are no instructions to use it.
if (!ST.hasMAIInsts()) {
for (unsigned i = 0; i < MaxNumAGPRs; ++i) {
unsigned Reg = AMDGPU::AGPR_32RegClass.getRegister(i);
reserveRegisterTuples(Reserved, Reg);
}
}
for (auto Reg : AMDGPU::AGPR_32RegClass) {
Reserved.set(getSubReg(Reg, AMDGPU::hi16));
}
// On GFX90A, the number of VGPRs and AGPRs need not be equal. Theoretically,
// a wave may have up to 512 total vector registers combining together both
// VGPRs and AGPRs. Hence, in an entry function without calls and without
// AGPRs used within it, it is possible to use the whole vector register
// budget for VGPRs.
//
// TODO: it shall be possible to estimate maximum AGPR/VGPR pressure and split
// register file accordingly.
if (ST.hasGFX90AInsts()) {
if (MFI->usesAGPRs(MF)) {
MaxNumVGPRs /= 2;
MaxNumAGPRs = MaxNumVGPRs;
} else {
if (MaxNumVGPRs > TotalNumVGPRs) {
MaxNumAGPRs = MaxNumVGPRs - TotalNumVGPRs;
MaxNumVGPRs = TotalNumVGPRs;
} else
MaxNumAGPRs = 0;
}
}
for (unsigned i = MaxNumVGPRs; i < TotalNumVGPRs; ++i) {
unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i);
reserveRegisterTuples(Reserved, Reg);
}
for (unsigned i = MaxNumAGPRs; i < TotalNumVGPRs; ++i) {
unsigned Reg = AMDGPU::AGPR_32RegClass.getRegister(i);
reserveRegisterTuples(Reserved, Reg);
}
// On GFX908, in order to guarantee copying between AGPRs, we need a scratch
// VGPR available at all times.
if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) {
reserveRegisterTuples(Reserved, MFI->getVGPRForAGPRCopy());
}
for (Register Reg : MFI->getWWMReservedRegs())
reserveRegisterTuples(Reserved, Reg);
// FIXME: Stop using reserved registers for this.
for (MCPhysReg Reg : MFI->getAGPRSpillVGPRs())
reserveRegisterTuples(Reserved, Reg);
for (MCPhysReg Reg : MFI->getVGPRSpillAGPRs())
reserveRegisterTuples(Reserved, Reg);
for (auto Reg : MFI->getSGPRSpillVGPRs())
reserveRegisterTuples(Reserved, Reg);
return Reserved;
}
bool SIRegisterInfo::isAsmClobberable(const MachineFunction &MF,
MCRegister PhysReg) const {
return !MF.getRegInfo().isReserved(PhysReg);
}
bool SIRegisterInfo::shouldRealignStack(const MachineFunction &MF) const {
const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
// On entry, the base address is 0, so it can't possibly need any more
// alignment.
// FIXME: Should be able to specify the entry frame alignment per calling
// convention instead.
if (Info->isEntryFunction())
return false;
return TargetRegisterInfo::shouldRealignStack(MF);
}
bool SIRegisterInfo::requiresRegisterScavenging(const MachineFunction &Fn) const {
const SIMachineFunctionInfo *Info = Fn.getInfo<SIMachineFunctionInfo>();
if (Info->isEntryFunction()) {
const MachineFrameInfo &MFI = Fn.getFrameInfo();
return MFI.hasStackObjects() || MFI.hasCalls();
}
// May need scavenger for dealing with callee saved registers.
return true;
}
bool SIRegisterInfo::requiresFrameIndexScavenging(
const MachineFunction &MF) const {
// Do not use frame virtual registers. They used to be used for SGPRs, but
// once we reach PrologEpilogInserter, we can no longer spill SGPRs. If the
// scavenger fails, we can increment/decrement the necessary SGPRs to avoid a
// spill.
return false;
}
bool SIRegisterInfo::requiresFrameIndexReplacementScavenging(
const MachineFunction &MF) const {
const MachineFrameInfo &MFI = MF.getFrameInfo();
return MFI.hasStackObjects();
}
bool SIRegisterInfo::requiresVirtualBaseRegisters(
const MachineFunction &) const {
// There are no special dedicated stack or frame pointers.
return true;
}
int64_t SIRegisterInfo::getScratchInstrOffset(const MachineInstr *MI) const {
assert(SIInstrInfo::isMUBUF(*MI) || SIInstrInfo::isFLATScratch(*MI));
int OffIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
AMDGPU::OpName::offset);
return MI->getOperand(OffIdx).getImm();
}
int64_t SIRegisterInfo::getFrameIndexInstrOffset(const MachineInstr *MI,
int Idx) const {
if (!SIInstrInfo::isMUBUF(*MI) && !SIInstrInfo::isFLATScratch(*MI))
return 0;
assert((Idx == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
AMDGPU::OpName::vaddr) ||
(Idx == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
AMDGPU::OpName::saddr))) &&
"Should never see frame index on non-address operand");
return getScratchInstrOffset(MI);
}
bool SIRegisterInfo::needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
if (!SIInstrInfo::isMUBUF(*MI) && !SIInstrInfo::isFLATScratch(*MI))
return false;
int64_t FullOffset = Offset + getScratchInstrOffset(MI);
if (SIInstrInfo::isMUBUF(*MI))
return !SIInstrInfo::isLegalMUBUFImmOffset(FullOffset);
const SIInstrInfo *TII = ST.getInstrInfo();
return !TII->isLegalFLATOffset(FullOffset, AMDGPUAS::PRIVATE_ADDRESS,
SIInstrFlags::FlatScratch);
}
Register SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
int FrameIdx,
int64_t Offset) const {
MachineBasicBlock::iterator Ins = MBB->begin();
DebugLoc DL; // Defaults to "unknown"
if (Ins != MBB->end())
DL = Ins->getDebugLoc();
MachineFunction *MF = MBB->getParent();
const SIInstrInfo *TII = ST.getInstrInfo();
MachineRegisterInfo &MRI = MF->getRegInfo();
unsigned MovOpc = ST.enableFlatScratch() ? AMDGPU::S_MOV_B32
: AMDGPU::V_MOV_B32_e32;
Register BaseReg = MRI.createVirtualRegister(
ST.enableFlatScratch() ? &AMDGPU::SReg_32_XEXEC_HIRegClass
: &AMDGPU::VGPR_32RegClass);
if (Offset == 0) {
BuildMI(*MBB, Ins, DL, TII->get(MovOpc), BaseReg)
.addFrameIndex(FrameIdx);
return BaseReg;
}
Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
Register FIReg = MRI.createVirtualRegister(
ST.enableFlatScratch() ? &AMDGPU::SReg_32_XM0RegClass
: &AMDGPU::VGPR_32RegClass);
BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg)
.addImm(Offset);
BuildMI(*MBB, Ins, DL, TII->get(MovOpc), FIReg)
.addFrameIndex(FrameIdx);
if (ST.enableFlatScratch() ) {
BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_ADD_I32), BaseReg)
.addReg(OffsetReg, RegState::Kill)
.addReg(FIReg);
return BaseReg;
}
TII->getAddNoCarry(*MBB, Ins, DL, BaseReg)
.addReg(OffsetReg, RegState::Kill)
.addReg(FIReg)
.addImm(0); // clamp bit
return BaseReg;
}
void SIRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg,
int64_t Offset) const {
const SIInstrInfo *TII = ST.getInstrInfo();
bool IsFlat = TII->isFLATScratch(MI);
#ifndef NDEBUG
// FIXME: Is it possible to be storing a frame index to itself?
bool SeenFI = false;
for (const MachineOperand &MO: MI.operands()) {
if (MO.isFI()) {
if (SeenFI)
llvm_unreachable("should not see multiple frame indices");
SeenFI = true;
}
}
#endif
MachineOperand *FIOp =
TII->getNamedOperand(MI, IsFlat ? AMDGPU::OpName::saddr
: AMDGPU::OpName::vaddr);
MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset);
int64_t NewOffset = OffsetOp->getImm() + Offset;
assert(FIOp && FIOp->isFI() && "frame index must be address operand");
assert(TII->isMUBUF(MI) || TII->isFLATScratch(MI));
if (IsFlat) {
assert(TII->isLegalFLATOffset(NewOffset, AMDGPUAS::PRIVATE_ADDRESS,
SIInstrFlags::FlatScratch) &&
"offset should be legal");
FIOp->ChangeToRegister(BaseReg, false);
OffsetOp->setImm(NewOffset);
return;
}
#ifndef NDEBUG
MachineOperand *SOffset = TII->getNamedOperand(MI, AMDGPU::OpName::soffset);
assert(SOffset->isImm() && SOffset->getImm() == 0);
#endif
assert(SIInstrInfo::isLegalMUBUFImmOffset(NewOffset) &&
"offset should be legal");
FIOp->ChangeToRegister(BaseReg, false);
OffsetOp->setImm(NewOffset);
}
bool SIRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
Register BaseReg,
int64_t Offset) const {
if (!SIInstrInfo::isMUBUF(*MI) && !SIInstrInfo::isFLATScratch(*MI))
return false;
int64_t NewOffset = Offset + getScratchInstrOffset(MI);
if (SIInstrInfo::isMUBUF(*MI))
return SIInstrInfo::isLegalMUBUFImmOffset(NewOffset);
const SIInstrInfo *TII = ST.getInstrInfo();
return TII->isLegalFLATOffset(NewOffset, AMDGPUAS::PRIVATE_ADDRESS,
SIInstrFlags::FlatScratch);
}
const TargetRegisterClass *SIRegisterInfo::getPointerRegClass(
const MachineFunction &MF, unsigned Kind) const {
// This is inaccurate. It depends on the instruction and address space. The
// only place where we should hit this is for dealing with frame indexes /
// private accesses, so this is correct in that case.
return &AMDGPU::VGPR_32RegClass;
}
const TargetRegisterClass *
SIRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
if (isAGPRClass(RC) && !ST.hasGFX90AInsts())
return getEquivalentVGPRClass(RC);
if (RC == &AMDGPU::SCC_CLASSRegClass)
return getWaveMaskRegClass();
return RC;
}
static unsigned getNumSubRegsForSpillOp(unsigned Op) {
switch (Op) {
case AMDGPU::SI_SPILL_S1024_SAVE:
case AMDGPU::SI_SPILL_S1024_RESTORE:
case AMDGPU::SI_SPILL_V1024_SAVE:
case AMDGPU::SI_SPILL_V1024_RESTORE:
case AMDGPU::SI_SPILL_A1024_SAVE:
case AMDGPU::SI_SPILL_A1024_RESTORE:
case AMDGPU::SI_SPILL_AV1024_SAVE:
case AMDGPU::SI_SPILL_AV1024_RESTORE:
return 32;
case AMDGPU::SI_SPILL_S512_SAVE:
case AMDGPU::SI_SPILL_S512_RESTORE:
case AMDGPU::SI_SPILL_V512_SAVE:
case AMDGPU::SI_SPILL_V512_RESTORE:
case AMDGPU::SI_SPILL_A512_SAVE:
case AMDGPU::SI_SPILL_A512_RESTORE:
case AMDGPU::SI_SPILL_AV512_SAVE:
case AMDGPU::SI_SPILL_AV512_RESTORE:
return 16;
case AMDGPU::SI_SPILL_S384_SAVE:
case AMDGPU::SI_SPILL_S384_RESTORE:
case AMDGPU::SI_SPILL_V384_SAVE:
case AMDGPU::SI_SPILL_V384_RESTORE:
case AMDGPU::SI_SPILL_A384_SAVE:
case AMDGPU::SI_SPILL_A384_RESTORE:
case AMDGPU::SI_SPILL_AV384_SAVE:
case AMDGPU::SI_SPILL_AV384_RESTORE:
return 12;
case AMDGPU::SI_SPILL_S352_SAVE:
case AMDGPU::SI_SPILL_S352_RESTORE:
case AMDGPU::SI_SPILL_V352_SAVE:
case AMDGPU::SI_SPILL_V352_RESTORE:
case AMDGPU::SI_SPILL_A352_SAVE:
case AMDGPU::SI_SPILL_A352_RESTORE:
case AMDGPU::SI_SPILL_AV352_SAVE:
case AMDGPU::SI_SPILL_AV352_RESTORE:
return 11;
case AMDGPU::SI_SPILL_S320_SAVE:
case AMDGPU::SI_SPILL_S320_RESTORE:
case AMDGPU::SI_SPILL_V320_SAVE:
case AMDGPU::SI_SPILL_V320_RESTORE:
case AMDGPU::SI_SPILL_A320_SAVE:
case AMDGPU::SI_SPILL_A320_RESTORE:
case AMDGPU::SI_SPILL_AV320_SAVE:
case AMDGPU::SI_SPILL_AV320_RESTORE:
return 10;
case AMDGPU::SI_SPILL_S288_SAVE:
case AMDGPU::SI_SPILL_S288_RESTORE:
case AMDGPU::SI_SPILL_V288_SAVE:
case AMDGPU::SI_SPILL_V288_RESTORE:
case AMDGPU::SI_SPILL_A288_SAVE:
case AMDGPU::SI_SPILL_A288_RESTORE:
case AMDGPU::SI_SPILL_AV288_SAVE:
case AMDGPU::SI_SPILL_AV288_RESTORE:
return 9;
case AMDGPU::SI_SPILL_S256_SAVE:
case AMDGPU::SI_SPILL_S256_RESTORE:
case AMDGPU::SI_SPILL_V256_SAVE:
case AMDGPU::SI_SPILL_V256_RESTORE: