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X86SchedSandyBridge.td
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X86SchedSandyBridge.td
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//=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the machine model for Sandy Bridge to support instruction
// scheduling and other instruction cost heuristics.
//
//===----------------------------------------------------------------------===//
def SandyBridgeModel : SchedMachineModel {
// All x86 instructions are modeled as a single micro-op, and SB can decode 4
// instructions per cycle.
// FIXME: Identify instructions that aren't a single fused micro-op.
let IssueWidth = 4;
let MicroOpBufferSize = 168; // Based on the reorder buffer.
let LoadLatency = 4;
let MispredictPenalty = 16;
// Based on the LSD (loop-stream detector) queue size.
let LoopMicroOpBufferSize = 28;
// This flag is set to allow the scheduler to assign
// a default model to unrecognized opcodes.
let CompleteModel = 0;
}
let SchedModel = SandyBridgeModel in {
// Sandy Bridge can issue micro-ops to 6 different ports in one cycle.
// Ports 0, 1, and 5 handle all computation.
def SBPort0 : ProcResource<1>;
def SBPort1 : ProcResource<1>;
def SBPort5 : ProcResource<1>;
// Ports 2 and 3 are identical. They handle loads and the address half of
// stores.
def SBPort23 : ProcResource<2>;
// Port 4 gets the data half of stores. Store data can be available later than
// the store address, but since we don't model the latency of stores, we can
// ignore that.
def SBPort4 : ProcResource<1>;
// Many micro-ops are capable of issuing on multiple ports.
def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>;
def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>;
def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>;
def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;
// 54 Entry Unified Scheduler
def SBPortAny : ProcResGroup<[SBPort0, SBPort1, SBPort23, SBPort4, SBPort5]> {
let BufferSize=54;
}
// Integer division issued on port 0.
def SBDivider : ProcResource<1>;
// Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
// cycles after the memory operand.
def : ReadAdvance<ReadAfterLd, 4>;
// Many SchedWrites are defined in pairs with and without a folded load.
// Instructions with folded loads are usually micro-fused, so they only appear
// as two micro-ops when queued in the reservation station.
// This multiclass defines the resource usage for variants with and without
// folded loads.
multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW,
list<ProcResourceKind> ExePorts,
int Lat, list<int> Res = [1], int UOps = 1,
int LoadLat = 4> {
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ResourceCycles = Res;
let NumMicroOps = UOps;
}
// Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
// the latency (default = 4).
def : WriteRes<SchedRW.Folded, !listconcat([SBPort23], ExePorts)> {
let Latency = !add(Lat, LoadLat);
let ResourceCycles = !listconcat([1], Res);
let NumMicroOps = !add(UOps, 1);
}
}
// A folded store needs a cycle on port 4 for the store data, but it does not
// need an extra port 2/3 cycle to recompute the address.
def : WriteRes<WriteRMW, [SBPort4]>;
def : WriteRes<WriteStore, [SBPort23, SBPort4]>;
def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 4; }
def : WriteRes<WriteMove, [SBPort015]>;
def : WriteRes<WriteZero, []>;
defm : SBWriteResPair<WriteALU, [SBPort015], 1>;
defm : SBWriteResPair<WriteIMul, [SBPort1], 3>;
defm : SBWriteResPair<WriteIDiv, [SBPort0, SBDivider], 25, [1, 10]>;
def : WriteRes<WriteIMulH, []> { let Latency = 3; }
defm : SBWriteResPair<WriteShift, [SBPort05], 1>;
defm : SBWriteResPair<WriteJump, [SBPort5], 1>;
defm : SBWriteResPair<WriteCRC32, [SBPort1], 3, [1], 1, 5>;
// This is for simple LEAs with one or two input operands.
// The complex ones can only execute on port 1, and they require two cycles on
// the port to read all inputs. We don't model that.
def : WriteRes<WriteLEA, [SBPort15]>;
// Bit counts.
defm : SBWriteResPair<WriteBitScan, [SBPort1], 3, [1], 1, 5>;
defm : SBWriteResPair<WriteLZCNT, [SBPort1], 3, [1], 1, 5>;
defm : SBWriteResPair<WriteTZCNT, [SBPort1], 3, [1], 1, 5>;
defm : SBWriteResPair<WritePOPCNT, [SBPort1], 3, [1], 1, 5>;
// Scalar and vector floating point.
def : WriteRes<WriteFStore, [SBPort23, SBPort4]>;
def : WriteRes<WriteFLoad, [SBPort23]> { let Latency = 6; }
def : WriteRes<WriteFMove, [SBPort5]>;
defm : SBWriteResPair<WriteFAdd, [SBPort1], 3>;
defm : SBWriteResPair<WriteFMul, [SBPort0], 5>;
defm : SBWriteResPair<WriteFDiv, [SBPort0], 24>;
defm : SBWriteResPair<WriteFRcp, [SBPort0], 5>;
defm : SBWriteResPair<WriteFRsqrt, [SBPort0], 5>;
defm : SBWriteResPair<WriteFSqrt, [SBPort0], 14>;
defm : SBWriteResPair<WriteCvtF2I, [SBPort1], 3>;
defm : SBWriteResPair<WriteCvtI2F, [SBPort1], 4>;
defm : SBWriteResPair<WriteCvtF2F, [SBPort1], 3>;
defm : SBWriteResPair<WriteFShuffle, [SBPort5], 1>;
defm : SBWriteResPair<WriteFBlend, [SBPort05], 1>;
defm : SBWriteResPair<WriteFVarBlend, [SBPort0, SBPort5], 2>;
// Vector integer operations.
def : WriteRes<WriteVecStore, [SBPort23, SBPort4]>;
def : WriteRes<WriteVecLoad, [SBPort23]> { let Latency = 6; }
def : WriteRes<WriteVecMove, [SBPort05]>;
defm : SBWriteResPair<WriteVecShift, [SBPort5], 1>;
defm : SBWriteResPair<WriteVecLogic, [SBPort5], 1>;
defm : SBWriteResPair<WriteVecALU, [SBPort1], 3>;
defm : SBWriteResPair<WriteVecIMul, [SBPort0], 5>;
defm : SBWriteResPair<WriteShuffle, [SBPort5], 1>;
defm : SBWriteResPair<WriteBlend, [SBPort15], 1>;
defm : SBWriteResPair<WriteVarBlend, [SBPort1, SBPort5], 2>;
defm : SBWriteResPair<WriteMPSAD, [SBPort0, SBPort15], 5, [1,2], 3>;
////////////////////////////////////////////////////////////////////////////////
// Horizontal add/sub instructions.
////////////////////////////////////////////////////////////////////////////////
defm : SBWriteResPair<WriteFHAdd, [SBPort1], 3>;
defm : SBWriteResPair<WritePHAdd, [SBPort15], 1>;
// String instructions.
// Packed Compare Implicit Length Strings, Return Mask
def : WriteRes<WritePCmpIStrM, [SBPort0]> {
let Latency = 11;
let NumMicroOps = 3;
let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrMLd, [SBPort0, SBPort23]> {
let Latency = 17;
let NumMicroOps = 4;
let ResourceCycles = [3,1];
}
// Packed Compare Explicit Length Strings, Return Mask
def : WriteRes<WritePCmpEStrM, [SBPort015]> {
let Latency = 11;
let ResourceCycles = [8];
}
def : WriteRes<WritePCmpEStrMLd, [SBPort015, SBPort23]> {
let Latency = 11;
let ResourceCycles = [7, 1];
}
// Packed Compare Implicit Length Strings, Return Index
def : WriteRes<WritePCmpIStrI, [SBPort0]> {
let Latency = 11;
let NumMicroOps = 3;
let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrILd, [SBPort0,SBPort23]> {
let Latency = 17;
let NumMicroOps = 4;
let ResourceCycles = [3,1];
}
// Packed Compare Explicit Length Strings, Return Index
def : WriteRes<WritePCmpEStrI, [SBPort015]> {
let Latency = 4;
let ResourceCycles = [8];
}
def : WriteRes<WritePCmpEStrILd, [SBPort015, SBPort23]> {
let Latency = 4;
let ResourceCycles = [7, 1];
}
// AES Instructions.
def : WriteRes<WriteAESDecEnc, [SBPort5,SBPort015]> {
let Latency = 7;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def : WriteRes<WriteAESDecEncLd, [SBPort5,SBPort23,SBPort015]> {
let Latency = 13;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def : WriteRes<WriteAESIMC, [SBPort5]> {
let Latency = 12;
let NumMicroOps = 2;
let ResourceCycles = [2];
}
def : WriteRes<WriteAESIMCLd, [SBPort5,SBPort23]> {
let Latency = 18;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
def : WriteRes<WriteAESKeyGen, [SBPort015]> {
let Latency = 8;
let ResourceCycles = [11];
}
def : WriteRes<WriteAESKeyGenLd, [SBPort015, SBPort23]> {
let Latency = 8;
let ResourceCycles = [10, 1];
}
// Carry-less multiplication instructions.
def : WriteRes<WriteCLMul, [SBPort015]> {
let Latency = 14;
let ResourceCycles = [18];
}
def : WriteRes<WriteCLMulLd, [SBPort015, SBPort23]> {
let Latency = 14;
let ResourceCycles = [17, 1];
}
def : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; }
def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; }
def : WriteRes<WriteFence, [SBPort23, SBPort4]>;
def : WriteRes<WriteNop, []>;
// AVX2/FMA is not supported on that architecture, but we should define the basic
// scheduling resources anyway.
defm : SBWriteResPair<WriteFShuffle256, [SBPort0], 1>;
defm : SBWriteResPair<WriteShuffle256, [SBPort0], 1>;
defm : SBWriteResPair<WriteVarVecShift, [SBPort0], 1>;
defm : SBWriteResPair<WriteFMA, [SBPort01], 5>;
// Remaining SNB instrs.
def SBWriteResGroup0 : SchedWriteRes<[SBPort0]> {
let Latency = 1;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup0], (instregex "(V?)CVTSS2SDrr",
"(V?)PSLLDri",
"(V?)PSLLQri",
"(V?)PSLLWri",
"(V?)PSRADri",
"(V?)PSRAWri",
"(V?)PSRLDri",
"(V?)PSRLQri",
"(V?)PSRLWri",
"VTESTPD(Y?)rr",
"VTESTPS(Y?)rr")>;
def SBWriteResGroup1 : SchedWriteRes<[SBPort1]> {
let Latency = 1;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup1], (instregex "COMP_FST0r",
"COM_FST0r",
"UCOM_FPr",
"UCOM_Fr")>;
def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> {
let Latency = 1;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup2], (instrs LOOP, LOOPE, LOOPNE)>;
def: InstRW<[SBWriteResGroup2], (instregex "FDECSTP",
"FFREE",
"FINCSTP",
"FNOP",
"INSERTPSrr",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
"JMP(16|32|64)r",
"JMP_1",
"JMP_4",
"LD_Frr",
"RETQ",
"ST_FPrr",
"ST_Frr",
"(V?)ANDNPD(Y?)rr",
"(V?)ANDNPS(Y?)rr",
"(V?)ANDPD(Y?)rr",
"(V?)ANDPS(Y?)rr",
"VEXTRACTF128rr",
"VINSERTF128rr",
"VINSERTPSrr",
"(V?)MOV64toPQIrr",
"(V?)MOVAPD(Y?)rr",
"(V?)MOVAPS(Y?)rr",
"(V?)MOVDDUP(Y?)rr",
"(V?)MOVDI2PDIrr",
"(V?)MOVHLPSrr",
"(V?)MOVLHPSrr",
"(V?)MOVSDrr",
"(V?)MOVSHDUP(Y?)rr",
"(V?)MOVSLDUP(Y?)rr",
"(V?)MOVSSrr",
"(V?)MOVUPD(Y?)rr",
"(V?)MOVUPS(Y?)rr",
"(V?)ORPD(Y?)rr",
"(V?)ORPS(Y?)rr",
"VPERM2F128rr",
"VPERMILPD(Y?)ri",
"VPERMILPD(Y?)rr",
"VPERMILPS(Y?)ri",
"VPERMILPS(Y?)rr",
"(V?)SHUFPD(Y?)rri",
"(V?)SHUFPS(Y?)rri",
"(V?)UNPCKHPD(Y?)rr",
"(V?)UNPCKHPS(Y?)rr",
"(V?)UNPCKLPD(Y?)rr",
"(V?)UNPCKLPS(Y?)rr",
"(V?)XORPD(Y?)rr",
"(V?)XORPS(Y?)rr")>;
def SBWriteResGroup3 : SchedWriteRes<[SBPort01]> {
let Latency = 1;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup3], (instregex "LEA(16|32|64)(_32)?r")>;
def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> {
let Latency = 1;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup4], (instregex "BT(16|32|64)ri8",
"BT(16|32|64)rr",
"BTC(16|32|64)ri8",
"BTC(16|32|64)rr",
"BTR(16|32|64)ri8",
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
"BTS(16|32|64)rr",
"CDQ",
"CQO",
"LAHF",
"SAHF",
"SAR(8|16|32|64)ri",
"SAR(8|16|32|64)r1",
"SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
"SHL(8|16|32|64)ri",
"SHL(8|16|32|64)r1",
"SHR(8|16|32|64)ri",
"SHR(8|16|32|64)r1",
"(V?)BLENDPD(Y?)rri",
"(V?)BLENDPS(Y?)rri",
"VMOVDQA(Y?)rr",
"VMOVDQU(Y?)rr")>;
def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> {
let Latency = 1;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSBrr",
"MMX_PABSDrr",
"MMX_PABSWrr",
"MMX_PADDQirr",
"MMX_PALIGNRrri",
"MMX_PSHUFBrr",
"MMX_PSIGNBrr",
"MMX_PSIGNDrr",
"MMX_PSIGNWrr",
"(V?)PABSBrr",
"(V?)PABSDrr",
"(V?)PABSWrr",
"(V?)PACKSSDWrr",
"(V?)PACKSSWBrr",
"(V?)PACKUSDWrr",
"(V?)PACKUSWBrr",
"(V?)PADDBrr",
"(V?)PADDDrr",
"(V?)PADDQrr",
"(V?)PADDSBrr",
"(V?)PADDSWrr",
"(V?)PADDUSBrr",
"(V?)PADDUSWrr",
"(V?)PADDWrr",
"(V?)PALIGNRrri",
"(V?)PAVGBrr",
"(V?)PAVGWrr",
"(V?)PBLENDWrri",
"(V?)PCMPEQBrr",
"(V?)PCMPEQDrr",
"(V?)PCMPEQQrr",
"(V?)PCMPEQWrr",
"(V?)PCMPGTBrr",
"(V?)PCMPGTDrr",
"(V?)PCMPGTWrr",
"(V?)PMAXSBrr",
"(V?)PMAXSDrr",
"(V?)PMAXSWrr",
"(V?)PMAXUBrr",
"(V?)PMAXUDrr",
"(V?)PMAXUWrr",
"(V?)PMINSBrr",
"(V?)PMINSDrr",
"(V?)PMINSWrr",
"(V?)PMINUBrr",
"(V?)PMINUDrr",
"(V?)PMINUWrr",
"(V?)PMOVSXBDrr",
"(V?)PMOVSXBQrr",
"(V?)PMOVSXBWrr",
"(V?)PMOVSXDQrr",
"(V?)PMOVSXWDrr",
"(V?)PMOVSXWQrr",
"(V?)PMOVZXBDrr",
"(V?)PMOVZXBQrr",
"(V?)PMOVZXBWrr",
"(V?)PMOVZXDQrr",
"(V?)PMOVZXWDrr",
"(V?)PMOVZXWQrr",
"(V?)PSHUFBrr",
"(V?)PSHUFDri",
"(V?)PSHUFHWri",
"(V?)PSHUFLWri",
"(V?)PSIGNBrr",
"(V?)PSIGNDrr",
"(V?)PSIGNWrr",
"(V?)PSLLDQri",
"(V?)PSRLDQri",
"(V?)PSUBBrr",
"(V?)PSUBDrr",
"(V?)PSUBQrr",
"(V?)PSUBSBrr",
"(V?)PSUBSWrr",
"(V?)PSUBUSBrr",
"(V?)PSUBUSWrr",
"(V?)PSUBWrr",
"(V?)PUNPCKHBWrr",
"(V?)PUNPCKHDQrr",
"(V?)PUNPCKHQDQrr",
"(V?)PUNPCKHWDrr",
"(V?)PUNPCKLBWrr",
"(V?)PUNPCKLDQrr",
"(V?)PUNPCKLQDQrr",
"(V?)PUNPCKLWDrr")>;
def SBWriteResGroup6 : SchedWriteRes<[SBPort015]> {
let Latency = 1;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup6], (instrs CWDE)>;
def: InstRW<[SBWriteResGroup6], (instregex "ADD(8|16|32|64)ri",
"ADD(8|16|32|64)rr",
"ADD(8|16|32|64)i",
"AND(8|16|32|64)ri",
"AND(8|16|32|64)rr",
"AND(8|16|32|64)i",
"CBW",
"CMC",
"CMP(8|16|32|64)ri",
"CMP(8|16|32|64)rr",
"CMP(8|16|32|64)i",
"DEC(8|16|32|64)r",
"INC(8|16|32|64)r",
"MMX_MOVD64from64rr",
"MMX_MOVQ2DQrr",
"MOV(8|16|32|64)rr",
"MOV(8|16|32|64)ri",
"MOVDQArr",
"MOVDQUrr",
"MOVSX(16|32|64)rr16",
"MOVSX(16|32|64)rr32",
"MOVSX(16|32|64)rr8",
"MOVZX(16|32|64)rr16",
"MOVZX(16|32|64)rr8",
"NEG(8|16|32|64)r",
"NOT(8|16|32|64)r",
"OR(8|16|32|64)ri",
"OR(8|16|32|64)rr",
"OR(8|16|32|64)i",
"STC",
"SUB(8|16|32|64)ri",
"SUB(8|16|32|64)rr",
"SUB(8|16|32|64)i",
"TEST(8|16|32|64)rr",
"TEST(8|16|32|64)i",
"TEST(8|16|32|64)ri",
"(V?)MOVPQI2QIrr",
"VMOVZPQILo2PQIrr",
"(V?)PANDNrr",
"(V?)PANDrr",
"(V?)PORrr",
"(V?)PXORrr",
"XOR(8|16|32|64)ri",
"XOR(8|16|32|64)rr",
"XOR(8|16|32|64)i")>;
def SBWriteResGroup7 : SchedWriteRes<[SBPort0]> {
let Latency = 2;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup7], (instregex "(V?)PMOVMSKBrr",
"(V?)MOVMSKPD(Y?)rr",
"(V?)MOVMSKPS(Y?)rr",
"(V?)MOVPDI2DIrr",
"(V?)MOVPQIto64rr")>;
def SBWriteResGroup9 : SchedWriteRes<[SBPort05]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [2];
}
def: InstRW<[SBWriteResGroup9], (instregex "BLENDVPDrr0",
"BLENDVPSrr0",
"ROL(8|16|32|64)r1",
"ROL(8|16|32|64)ri",
"ROR(8|16|32|64)r1",
"ROR(8|16|32|64)ri",
"SET(A|BE)r",
"VBLENDVPD(Y?)rr",
"VBLENDVPS(Y?)rr")>;
def SBWriteResGroup10 : SchedWriteRes<[SBPort15]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [2];
}
def: InstRW<[SBWriteResGroup10], (instregex "PBLENDVBrr0",
"VPBLENDVBrr")>;
def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [2];
}
def: InstRW<[SBWriteResGroup11], (instregex "SCASB",
"SCASL",
"SCASQ",
"SCASW")>;
def SBWriteResGroup12 : SchedWriteRes<[SBPort0,SBPort1]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup12], (instregex "(V?)COMISDrr",
"(V?)COMISSrr",
"(V?)UCOMISDrr",
"(V?)UCOMISSrr")>;
def SBWriteResGroup13 : SchedWriteRes<[SBPort0,SBPort5]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup13], (instregex "(V?)CVTPS2PD(Y?)rr",
"(V?)PTEST(Y?)rr")>;
def SBWriteResGroup14 : SchedWriteRes<[SBPort0,SBPort15]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup14], (instregex "(V?)PSLLDrr",
"(V?)PSLLQrr",
"(V?)PSLLWrr",
"(V?)PSRADrr",
"(V?)PSRAWrr",
"(V?)PSRLDrr",
"(V?)PSRLQrr",
"(V?)PSRLWrr")>;
def SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup15], (instrs CWD)>;
def: InstRW<[SBWriteResGroup15], (instregex "FNSTSW16r")>;
def SBWriteResGroup16 : SchedWriteRes<[SBPort1,SBPort05]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup16], (instregex "BSWAP(16|32|64)r")>;
def SBWriteResGroup17 : SchedWriteRes<[SBPort5,SBPort15]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup17], (instregex "(V?)PINSRBrr",
"(V?)PINSRDrr",
"(V?)PINSRQrr",
"(V?)PINSRWrr")>;
def SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup18], (instrs JCXZ, JECXZ, JRCXZ)>;
def: InstRW<[SBWriteResGroup18], (instregex "MMX_MOVDQ2Qrr")>;
def SBWriteResGroup19 : SchedWriteRes<[SBPort05,SBPort015]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup19], (instregex "ADC(8|16|32|64)ri",
"ADC(8|16|32|64)rr",
"ADC(8|16|32|64)i",
"CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
"SBB(8|16|32|64)ri",
"SBB(8|16|32|64)rr",
"SBB(8|16|32|64)i",
"SHLD(16|32|64)rri8",
"SHRD(16|32|64)rri8")>;
def SBWriteResGroup20 : SchedWriteRes<[SBPort0]> {
let Latency = 5;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMADDUBSWrr",
"MMX_PMADDWDirr",
"MMX_PMULHRSWrr",
"MMX_PMULHUWirr",
"MMX_PMULHWirr",
"MMX_PMULLWirr",
"MMX_PMULUDQirr",
"MMX_PSADBWirr",
"(V?)PMADDUBSWrr",
"(V?)PMADDWDrr",
"(V?)PMULDQrr",
"(V?)PMULHRSWrr",
"(V?)PMULHUWrr",
"(V?)PMULHWrr",
"(V?)PMULLDrr",
"(V?)PMULLWrr",
"(V?)PMULUDQrr",
"(V?)PSADBWrr")>;
def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> {
let Latency = 3;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup21], (instrs MUL8r, IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>;
def: InstRW<[SBWriteResGroup21], (instregex "ADD_FPrST0",
"ADD_FST0r",
"ADD_FrST0",
"MMX_CVTPI2PSirr",
"MMX_CVTPS2PIirr",
"MMX_CVTTPS2PIirr",
"POPCNT(16|32|64)rr",
"PUSHFS64",
"SUBR_FPrST0",
"SUBR_FST0r",
"SUBR_FrST0",
"SUB_FPrST0",
"SUB_FST0r",
"SUB_FrST0",
"(V?)ADDPD(Y?)rr",
"(V?)ADDPS(Y?)rr",
"(V?)ADDSDrr",
"(V?)ADDSSrr",
"(V?)ADDSUBPD(Y?)rr",
"(V?)ADDSUBPS(Y?)rr",
"(V?)CMPPD(Y?)rri",
"(V?)CMPPS(Y?)rri",
"(V?)CMPSDrr",
"(V?)CMPSSrr",
"(V?)CVTDQ2PS(Y?)rr",
"(V?)CVTPS2DQ(Y?)rr",
"(V?)CVTTPS2DQ(Y?)rr",
"(V?)MAX(C?)PD(Y?)rr",
"(V?)MAX(C?)PS(Y?)rr",
"(V?)MAX(C?)SDrr",
"(V?)MAX(C?)SSrr",
"(V?)MIN(C?)PD(Y?)rr",
"(V?)MIN(C?)PS(Y?)rr",
"(V?)MIN(C?)SDrr",
"(V?)MIN(C?)SSrr",
"(V?)ROUNDPD(Y?)r",
"(V?)ROUNDPS(Y?)r",
"(V?)ROUNDSDr",
"(V?)ROUNDSSr",
"(V?)SUBPD(Y?)rr",
"(V?)SUBPS(Y?)rr",
"(V?)SUBSDrr",
"(V?)SUBSSrr")>;
def SBWriteResGroup21_16i : SchedWriteRes<[SBPort1, SBPort015]> {
let Latency = 3;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup21_16i], (instrs IMUL16rri, IMUL16rri8)>;
def SBWriteResGroup22 : SchedWriteRes<[SBPort0,SBPort5]> {
let Latency = 3;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup22], (instregex "(V?)EXTRACTPSrr")>;
def SBWriteResGroup23 : SchedWriteRes<[SBPort0,SBPort15]> {
let Latency = 3;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup23], (instregex "(V?)PEXTRBrr",
"(V?)PEXTRDrr",
"(V?)PEXTRQrr",
"(V?)PEXTRWrr")>;
def SBWriteResGroup23_2 : SchedWriteRes<[SBPort05]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [3];
}
def: InstRW<[SBWriteResGroup23_2], (instregex "ROL(8|16|32|64)rCL",
"ROR(8|16|32|64)rCL",
"SAR(8|16|32|64)rCL",
"SHL(8|16|32|64)rCL",
"SHR(8|16|32|64)rCL")>;
def SBWriteResGroup24 : SchedWriteRes<[SBPort15]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [3];
}
def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDDrr",
"MMX_PHADDSWrr",
"MMX_PHADDWrr",
"MMX_PHSUBDrr",
"MMX_PHSUBSWrr",
"MMX_PHSUBWrr",
"(V?)PHADDDrr",
"(V?)PHADDSWrr",
"(V?)PHADDWrr",
"(V?)PHSUBDrr",
"(V?)PHSUBSWrr",
"(V?)PHSUBWrr")>;
def SBWriteResGroup25 : SchedWriteRes<[SBPort015]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [3];
}
def: InstRW<[SBWriteResGroup25], (instregex "LEAVE64",
"XADD(8|16|32|64)rr")>;
def SBWriteResGroup25_2 : SchedWriteRes<[SBPort5,SBPort05]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
def: InstRW<[SBWriteResGroup25_2], (instregex "CMOVBE_F",
"CMOVB_F",
"CMOVE_F",
"CMOVNBE_F",
"CMOVNB_F",
"CMOVNE_F",
"CMOVNP_F",
"CMOVP_F")>;
def SBWriteResGroup26 : SchedWriteRes<[SBPort05,SBPort015]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
def: InstRW<[SBWriteResGroup26], (instregex "CMOV(A|BE)(16|32|64)rr")>;
def SBWriteResGroup26_2 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup26_2], (instregex "COM_FIPr",
"COM_FIr",
"UCOM_FIPr",
"UCOM_FIr")>;
// FIXME: this is probably incorrect.
def SBWriteResGroup27 : SchedWriteRes<[SBPort0,SBPort1]> {
let Latency = 4;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup27], (instrs MUL16r, MUL32r, MUL64r)>;
def SBWriteResGroup28 : SchedWriteRes<[SBPort1,SBPort5]> {
let Latency = 4;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup28], (instregex "MMX_CVTPD2PIirr",
"MMX_CVTPI2PDirr",
"MMX_CVTTPD2PIirr",
"(V?)CVTDQ2PD(Y?)rr",
"(V?)CVTPD2DQ(Y?)rr",
"(V?)CVTPD2PS(Y?)rr",
"(V?)CVTSD2SSrr",
"(V?)CVTSI642SDrr",
"(V?)CVTSI2SDrr",
"(V?)CVTTPD2DQ(Y?)rr")>;
def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> {
let Latency = 4;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup29], (instregex "MOV64sr")>;
def SBWriteResGroup29_2 : SchedWriteRes<[SBPort5,SBPort015]> {
let Latency = 4;
let NumMicroOps = 4;
let ResourceCycles = [1,3];
}
def: InstRW<[SBWriteResGroup29_2], (instregex "PAUSE")>;
def SBWriteResGroup29_3 : SchedWriteRes<[SBPort05,SBPort015]> {
let Latency = 4;
let NumMicroOps = 4;
let ResourceCycles = [3,1];
}
def: InstRW<[SBWriteResGroup29_3], (instregex "SHLD(16|32|64)rrCL",
"SHRD(16|32|64)rrCL")>;
def SBWriteResGroup30 : SchedWriteRes<[SBPort0]> {
let Latency = 5;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup30], (instregex "MUL_FPrST0",
"MUL_FST0r",
"MUL_FrST0",
"(V?)MULPD(Y?)rr",
"(V?)MULPS(Y?)rr",
"(V?)MULSDrr",
"(V?)MULSSrr",
"(V?)PCMPGTQrr",
"(V?)PHMINPOSUWrr",
"(V?)RCPPSr",
"(V?)RCPSSr",
"(V?)RSQRTPSr",
"(V?)RSQRTSSr")>;
def SBWriteResGroup31 : SchedWriteRes<[SBPort23]> {
let Latency = 5;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup31], (instregex "MOV(8|16|32|64)rm",
"MOVSX(16|32|64)rm16",
"MOVSX(16|32|64)rm32",
"MOVSX(16|32|64)rm8",
"MOVZX(16|32|64)rm16",
"MOVZX(16|32|64)rm8",
"PREFETCH")>;
def SBWriteResGroup32 : SchedWriteRes<[SBPort0,SBPort1]> {
let Latency = 5;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup32], (instregex "(V?)CVTSD2SI64rr",
"(V?)CVTSD2SIrr",
"(V?)CVTSS2SI64rr",
"(V?)CVTSS2SIrr",
"(V?)CVTTSD2SI64rr",
"(V?)CVTTSD2SIrr",
"(V?)CVTTSS2SI64rr",
"(V?)CVTTSS2SIrr")>;
def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> {
let Latency = 5;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup33], (instregex "MOV(8|16|32|64)mr",
"MOVNTI_64mr",
"MOVNTImr",
"PUSH64i8",
"PUSH(16|32|64)r",
"VEXTRACTF128mr",
"(V?)MOVAPD(Y?)mr",
"(V?)MOVAPS(Y?)mr",
"(V?)MOVDQA(Y?)mr",
"(V?)MOVDQU(Y?)mr",
"(V?)MOVHPDmr",
"(V?)MOVHPSmr",
"(V?)MOVLPDmr",
"(V?)MOVLPSmr",
"(V?)MOVNTDQ(Y?)mr",
"(V?)MOVNTPD(Y?)mr",
"(V?)MOVNTPS(Y?)mr",
"(V?)MOVPDI2DImr",
"(V?)MOVPQI2QImr",
"(V?)MOVPQIto64mr",
"(V?)MOVSDmr",
"(V?)MOVSSmr",
"(V?)MOVUPD(Y?)mr",
"(V?)MOVUPS(Y?)mr")>;
def SBWriteResGroup34 : SchedWriteRes<[SBPort0,SBPort15]> {
let Latency = 7;
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
def: InstRW<[SBWriteResGroup34], (instregex "(V?)MPSADBWrri")>;
def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> {
let Latency = 5;
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
def: InstRW<[SBWriteResGroup35], (instregex "CLI")>;
def: InstRW<[SBWriteResGroup35], (instregex "(V?)CVTSI642SSrr",
"(V?)CVTSI2SSrr",
"(V?)HADDPD(Y?)rr",
"(V?)HADDPS(Y?)rr",
"(V?)HSUBPD(Y?)rr",
"(V?)HSUBPS(Y?)rr")>;
def SBWriteResGroup35_2 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
let Latency = 5;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP16m",
"ISTT_FP32m",
"ISTT_FP64m",
"PUSHGS64")>;
def SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
let Latency = 5;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup36], (instregex "CALL64pcrel32",
"CALL(16|32|64)r",
"(V?)EXTRACTPSmr")>;
def SBWriteResGroup37 : SchedWriteRes<[SBPort4,SBPort01,SBPort23]> {
let Latency = 5;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup37], (instregex "VMASKMOVPD(Y?)mr",
"VMASKMOVPS(Y?)mr")>;
def SBWriteResGroup38 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
let Latency = 5;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup38], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;
def SBWriteResGroup39 : SchedWriteRes<[SBPort4,SBPort23,SBPort15]> {
let Latency = 5;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup39], (instregex "(V?)PEXTRBmr",
"VPEXTRDmr",
"VPEXTRWmr")>;
def SBWriteResGroup40 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {