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amdgpu-codegenprepare-idiv.ll
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amdgpu-codegenprepare-idiv.ll
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: opt -S -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-codegenprepare -amdgpu-bypass-slow-div=0 %s | FileCheck %s
; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-bypass-slow-div=0 < %s | FileCheck -check-prefix=GCN %s
define amdgpu_kernel void @udiv_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
; CHECK-LABEL: @udiv_i32(
; CHECK-NEXT: [[TMP1:%.*]] = uitofp i32 [[Y:%.*]] to float
; CHECK-NEXT: [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP2]], 0x41F0000000000000
; CHECK-NEXT: [[TMP4:%.*]] = fptoui float [[TMP3]] to i32
; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[Y]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[TMP5]], [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP7]] to i32
; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP7]], 32
; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
; CHECK-NEXT: [[TMP11:%.*]] = sub i32 0, [[TMP8]]
; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[TMP10]], 0
; CHECK-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i32 [[TMP11]], i32 [[TMP8]]
; CHECK-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP4]] to i64
; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP14]], [[TMP15]]
; CHECK-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32
; CHECK-NEXT: [[TMP18:%.*]] = lshr i64 [[TMP16]], 32
; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TMP4]], [[TMP19]]
; CHECK-NEXT: [[TMP21:%.*]] = sub i32 [[TMP4]], [[TMP19]]
; CHECK-NEXT: [[TMP22:%.*]] = select i1 [[TMP12]], i32 [[TMP20]], i32 [[TMP21]]
; CHECK-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
; CHECK-NEXT: [[TMP24:%.*]] = zext i32 [[X:%.*]] to i64
; CHECK-NEXT: [[TMP25:%.*]] = mul i64 [[TMP23]], [[TMP24]]
; CHECK-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32
; CHECK-NEXT: [[TMP27:%.*]] = lshr i64 [[TMP25]], 32
; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i32
; CHECK-NEXT: [[TMP29:%.*]] = mul i32 [[TMP28]], [[Y]]
; CHECK-NEXT: [[TMP30:%.*]] = sub i32 [[X]], [[TMP29]]
; CHECK-NEXT: [[TMP31:%.*]] = icmp uge i32 [[TMP30]], [[Y]]
; CHECK-NEXT: [[TMP32:%.*]] = icmp uge i32 [[X]], [[TMP29]]
; CHECK-NEXT: [[TMP33:%.*]] = and i1 [[TMP31]], [[TMP32]]
; CHECK-NEXT: [[TMP34:%.*]] = add i32 [[TMP28]], 1
; CHECK-NEXT: [[TMP35:%.*]] = sub i32 [[TMP28]], 1
; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP33]], i32 [[TMP34]], i32 [[TMP28]]
; CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP32]], i32 [[TMP36]], i32 [[TMP35]]
; CHECK-NEXT: store i32 [[TMP37]], i32 addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void
;
; GCN-LABEL: udiv_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9
; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_mul_lo_u32 v1, v0, s9
; GCN-NEXT: v_mul_hi_u32 v2, v0, s9
; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v2
; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[2:3]
; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[2:3]
; GCN-NEXT: v_mul_hi_u32 v0, v0, s8
; GCN-NEXT: v_mul_lo_u32 v1, v0, s9
; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0
; GCN-NEXT: v_sub_i32_e32 v4, vcc, s8, v1
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, s8, v1
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4
; GCN-NEXT: s_and_b64 s[0:1], s[0:1], vcc
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GCN-NEXT: s_endpgm
%r = udiv i32 %x, %y
store i32 %r, i32 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @urem_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
; CHECK-LABEL: @urem_i32(
; CHECK-NEXT: [[TMP1:%.*]] = uitofp i32 [[Y:%.*]] to float
; CHECK-NEXT: [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP2]], 0x41F0000000000000
; CHECK-NEXT: [[TMP4:%.*]] = fptoui float [[TMP3]] to i32
; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[Y]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[TMP5]], [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP7]] to i32
; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP7]], 32
; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
; CHECK-NEXT: [[TMP11:%.*]] = sub i32 0, [[TMP8]]
; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[TMP10]], 0
; CHECK-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i32 [[TMP11]], i32 [[TMP8]]
; CHECK-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP4]] to i64
; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP14]], [[TMP15]]
; CHECK-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32
; CHECK-NEXT: [[TMP18:%.*]] = lshr i64 [[TMP16]], 32
; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TMP4]], [[TMP19]]
; CHECK-NEXT: [[TMP21:%.*]] = sub i32 [[TMP4]], [[TMP19]]
; CHECK-NEXT: [[TMP22:%.*]] = select i1 [[TMP12]], i32 [[TMP20]], i32 [[TMP21]]
; CHECK-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
; CHECK-NEXT: [[TMP24:%.*]] = zext i32 [[X:%.*]] to i64
; CHECK-NEXT: [[TMP25:%.*]] = mul i64 [[TMP23]], [[TMP24]]
; CHECK-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32
; CHECK-NEXT: [[TMP27:%.*]] = lshr i64 [[TMP25]], 32
; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i32
; CHECK-NEXT: [[TMP29:%.*]] = mul i32 [[TMP28]], [[Y]]
; CHECK-NEXT: [[TMP30:%.*]] = sub i32 [[X]], [[TMP29]]
; CHECK-NEXT: [[TMP31:%.*]] = icmp uge i32 [[TMP30]], [[Y]]
; CHECK-NEXT: [[TMP32:%.*]] = icmp uge i32 [[X]], [[TMP29]]
; CHECK-NEXT: [[TMP33:%.*]] = and i1 [[TMP31]], [[TMP32]]
; CHECK-NEXT: [[TMP34:%.*]] = sub i32 [[TMP30]], [[Y]]
; CHECK-NEXT: [[TMP35:%.*]] = add i32 [[TMP30]], [[Y]]
; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP33]], i32 [[TMP34]], i32 [[TMP30]]
; CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP32]], i32 [[TMP36]], i32 [[TMP35]]
; CHECK-NEXT: store i32 [[TMP37]], i32 addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void
;
; GCN-LABEL: urem_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9
; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_mul_lo_u32 v1, v0, s9
; GCN-NEXT: v_mul_hi_u32 v2, v0, s9
; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v2
; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[2:3]
; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[2:3]
; GCN-NEXT: v_mul_hi_u32 v0, v0, s8
; GCN-NEXT: v_mul_lo_u32 v0, v0, s9
; GCN-NEXT: v_sub_i32_e32 v1, vcc, s8, v0
; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s8, v0
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, s9, v1
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s9, v1
; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3]
; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[2:3]
; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GCN-NEXT: s_endpgm
%r = urem i32 %x, %y
store i32 %r, i32 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @sdiv_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
; CHECK-LABEL: @sdiv_i32(
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 31
; CHECK-NEXT: [[TMP2:%.*]] = ashr i32 [[Y:%.*]], 31
; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[X]], [[TMP1]]
; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[Y]], [[TMP2]]
; CHECK-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], [[TMP1]]
; CHECK-NEXT: [[TMP7:%.*]] = xor i32 [[TMP5]], [[TMP2]]
; CHECK-NEXT: [[TMP8:%.*]] = uitofp i32 [[TMP7]] to float
; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP8]])
; CHECK-NEXT: [[TMP10:%.*]] = fmul fast float [[TMP9]], 0x41F0000000000000
; CHECK-NEXT: [[TMP11:%.*]] = fptoui float [[TMP10]] to i32
; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
; CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP7]] to i64
; CHECK-NEXT: [[TMP14:%.*]] = mul i64 [[TMP12]], [[TMP13]]
; CHECK-NEXT: [[TMP15:%.*]] = trunc i64 [[TMP14]] to i32
; CHECK-NEXT: [[TMP16:%.*]] = lshr i64 [[TMP14]], 32
; CHECK-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32
; CHECK-NEXT: [[TMP18:%.*]] = sub i32 0, [[TMP15]]
; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[TMP17]], 0
; CHECK-NEXT: [[TMP20:%.*]] = select i1 [[TMP19]], i32 [[TMP18]], i32 [[TMP15]]
; CHECK-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64
; CHECK-NEXT: [[TMP22:%.*]] = zext i32 [[TMP11]] to i64
; CHECK-NEXT: [[TMP23:%.*]] = mul i64 [[TMP21]], [[TMP22]]
; CHECK-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32
; CHECK-NEXT: [[TMP25:%.*]] = lshr i64 [[TMP23]], 32
; CHECK-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32
; CHECK-NEXT: [[TMP27:%.*]] = add i32 [[TMP11]], [[TMP26]]
; CHECK-NEXT: [[TMP28:%.*]] = sub i32 [[TMP11]], [[TMP26]]
; CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP19]], i32 [[TMP27]], i32 [[TMP28]]
; CHECK-NEXT: [[TMP30:%.*]] = zext i32 [[TMP29]] to i64
; CHECK-NEXT: [[TMP31:%.*]] = zext i32 [[TMP6]] to i64
; CHECK-NEXT: [[TMP32:%.*]] = mul i64 [[TMP30]], [[TMP31]]
; CHECK-NEXT: [[TMP33:%.*]] = trunc i64 [[TMP32]] to i32
; CHECK-NEXT: [[TMP34:%.*]] = lshr i64 [[TMP32]], 32
; CHECK-NEXT: [[TMP35:%.*]] = trunc i64 [[TMP34]] to i32
; CHECK-NEXT: [[TMP36:%.*]] = mul i32 [[TMP35]], [[TMP7]]
; CHECK-NEXT: [[TMP37:%.*]] = sub i32 [[TMP6]], [[TMP36]]
; CHECK-NEXT: [[TMP38:%.*]] = icmp uge i32 [[TMP37]], [[TMP7]]
; CHECK-NEXT: [[TMP39:%.*]] = icmp uge i32 [[TMP6]], [[TMP36]]
; CHECK-NEXT: [[TMP40:%.*]] = and i1 [[TMP38]], [[TMP39]]
; CHECK-NEXT: [[TMP41:%.*]] = add i32 [[TMP35]], 1
; CHECK-NEXT: [[TMP42:%.*]] = sub i32 [[TMP35]], 1
; CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP40]], i32 [[TMP41]], i32 [[TMP35]]
; CHECK-NEXT: [[TMP44:%.*]] = select i1 [[TMP39]], i32 [[TMP43]], i32 [[TMP42]]
; CHECK-NEXT: [[TMP45:%.*]] = xor i32 [[TMP44]], [[TMP3]]
; CHECK-NEXT: [[TMP46:%.*]] = sub i32 [[TMP45]], [[TMP3]]
; CHECK-NEXT: store i32 [[TMP46]], i32 addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void
;
; GCN-LABEL: sdiv_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i32 s8, s3, 31
; GCN-NEXT: s_add_i32 s3, s3, s8
; GCN-NEXT: s_xor_b32 s9, s3, s8
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9
; GCN-NEXT: s_ashr_i32 s3, s2, 31
; GCN-NEXT: s_add_i32 s2, s2, s3
; GCN-NEXT: s_xor_b32 s2, s2, s3
; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GCN-NEXT: s_xor_b32 s3, s3, s8
; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_mul_lo_u32 v1, v0, s9
; GCN-NEXT: v_mul_hi_u32 v2, v0, s9
; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GCN-NEXT: v_mul_hi_u32 v0, v0, s2
; GCN-NEXT: v_mul_lo_u32 v1, v0, s9
; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0
; GCN-NEXT: v_sub_i32_e32 v4, vcc, s2, v1
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, s2, v1
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4
; GCN-NEXT: s_and_b64 s[0:1], s[0:1], vcc
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
; GCN-NEXT: v_xor_b32_e32 v0, s3, v0
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0
; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GCN-NEXT: s_endpgm
%r = sdiv i32 %x, %y
store i32 %r, i32 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @srem_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) {
; CHECK-LABEL: @srem_i32(
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 31
; CHECK-NEXT: [[TMP2:%.*]] = ashr i32 [[Y:%.*]], 31
; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[X]], [[TMP1]]
; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[Y]], [[TMP2]]
; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP1]]
; CHECK-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], [[TMP2]]
; CHECK-NEXT: [[TMP7:%.*]] = uitofp i32 [[TMP6]] to float
; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP8]], 0x41F0000000000000
; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP9]] to i32
; CHECK-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP6]] to i64
; CHECK-NEXT: [[TMP13:%.*]] = mul i64 [[TMP11]], [[TMP12]]
; CHECK-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32
; CHECK-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP13]], 32
; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i32
; CHECK-NEXT: [[TMP17:%.*]] = sub i32 0, [[TMP14]]
; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[TMP16]], 0
; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP17]], i32 [[TMP14]]
; CHECK-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
; CHECK-NEXT: [[TMP21:%.*]] = zext i32 [[TMP10]] to i64
; CHECK-NEXT: [[TMP22:%.*]] = mul i64 [[TMP20]], [[TMP21]]
; CHECK-NEXT: [[TMP23:%.*]] = trunc i64 [[TMP22]] to i32
; CHECK-NEXT: [[TMP24:%.*]] = lshr i64 [[TMP22]], 32
; CHECK-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP24]] to i32
; CHECK-NEXT: [[TMP26:%.*]] = add i32 [[TMP10]], [[TMP25]]
; CHECK-NEXT: [[TMP27:%.*]] = sub i32 [[TMP10]], [[TMP25]]
; CHECK-NEXT: [[TMP28:%.*]] = select i1 [[TMP18]], i32 [[TMP26]], i32 [[TMP27]]
; CHECK-NEXT: [[TMP29:%.*]] = zext i32 [[TMP28]] to i64
; CHECK-NEXT: [[TMP30:%.*]] = zext i32 [[TMP5]] to i64
; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[TMP29]], [[TMP30]]
; CHECK-NEXT: [[TMP32:%.*]] = trunc i64 [[TMP31]] to i32
; CHECK-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP31]], 32
; CHECK-NEXT: [[TMP34:%.*]] = trunc i64 [[TMP33]] to i32
; CHECK-NEXT: [[TMP35:%.*]] = mul i32 [[TMP34]], [[TMP6]]
; CHECK-NEXT: [[TMP36:%.*]] = sub i32 [[TMP5]], [[TMP35]]
; CHECK-NEXT: [[TMP37:%.*]] = icmp uge i32 [[TMP36]], [[TMP6]]
; CHECK-NEXT: [[TMP38:%.*]] = icmp uge i32 [[TMP5]], [[TMP35]]
; CHECK-NEXT: [[TMP39:%.*]] = and i1 [[TMP37]], [[TMP38]]
; CHECK-NEXT: [[TMP40:%.*]] = sub i32 [[TMP36]], [[TMP6]]
; CHECK-NEXT: [[TMP41:%.*]] = add i32 [[TMP36]], [[TMP6]]
; CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP39]], i32 [[TMP40]], i32 [[TMP36]]
; CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP38]], i32 [[TMP42]], i32 [[TMP41]]
; CHECK-NEXT: [[TMP44:%.*]] = xor i32 [[TMP43]], [[TMP1]]
; CHECK-NEXT: [[TMP45:%.*]] = sub i32 [[TMP44]], [[TMP1]]
; CHECK-NEXT: store i32 [[TMP45]], i32 addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void
;
; GCN-LABEL: srem_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i32 s2, s5, 31
; GCN-NEXT: s_add_i32 s3, s5, s2
; GCN-NEXT: s_xor_b32 s10, s3, s2
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s10
; GCN-NEXT: s_ashr_i32 s8, s4, 31
; GCN-NEXT: s_add_i32 s4, s4, s8
; GCN-NEXT: s_xor_b32 s9, s4, s8
; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_mul_lo_u32 v1, v0, s10
; GCN-NEXT: v_mul_hi_u32 v2, v0, s10
; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v2
; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[2:3]
; GCN-NEXT: v_mul_hi_u32 v1, v1, v0
; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[2:3]
; GCN-NEXT: v_mul_hi_u32 v0, v0, s9
; GCN-NEXT: v_mul_lo_u32 v0, v0, s10
; GCN-NEXT: v_sub_i32_e32 v1, vcc, s9, v0
; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s9, v0
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, s10, v1
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s10, v1
; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3]
; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[2:3]
; GCN-NEXT: v_xor_b32_e32 v0, s8, v0
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GCN-NEXT: s_endpgm
%r = srem i32 %x, %y
store i32 %r, i32 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @udiv_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
; CHECK-LABEL: @udiv_i16(
; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[X:%.*]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[Y:%.*]] to i32
; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
; CHECK-NEXT: [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
; CHECK-NEXT: [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
; CHECK-NEXT: [[TMP16:%.*]] = and i32 [[TMP15]], 65535
; CHECK-NEXT: [[TMP17:%.*]] = trunc i32 [[TMP16]] to i16
; CHECK-NEXT: store i16 [[TMP17]], i16 addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void
;
; GCN-LABEL: udiv_i16:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dword s2, s[0:1], 0xb
; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_lshr_b32 s3, s2, 16
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s3
; GCN-NEXT: s_and_b32 s2, s2, 0xffff
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s2
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
; GCN-NEXT: buffer_store_short v0, off, s[0:3], 0
; GCN-NEXT: s_endpgm
%r = udiv i16 %x, %y
store i16 %r, i16 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @urem_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
; CHECK-LABEL: @urem_i16(
; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[X:%.*]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[Y:%.*]] to i32
; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
; CHECK-NEXT: [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
; CHECK-NEXT: [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
; CHECK-NEXT: [[TMP16:%.*]] = mul i32 [[TMP15]], [[TMP2]]
; CHECK-NEXT: [[TMP17:%.*]] = sub i32 [[TMP1]], [[TMP16]]
; CHECK-NEXT: [[TMP18:%.*]] = and i32 [[TMP17]], 65535
; CHECK-NEXT: [[TMP19:%.*]] = trunc i32 [[TMP18]] to i16
; CHECK-NEXT: store i16 [[TMP19]], i16 addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void
;
; GCN-LABEL: urem_i16:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dword s4, s[0:1], 0xb
; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_lshr_b32 s2, s4, 16
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
; GCN-NEXT: s_and_b32 s3, s4, 0xffff
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
; GCN-NEXT: v_mul_lo_u32 v0, v0, s2
; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GCN-NEXT: buffer_store_short v0, off, s[0:3], 0
; GCN-NEXT: s_endpgm
%r = urem i16 %x, %y
store i16 %r, i16 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @sdiv_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
; CHECK-LABEL: @sdiv_i16(
; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[X:%.*]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = sext i16 [[Y:%.*]] to i32
; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], 1
; CHECK-NEXT: [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
; CHECK-NEXT: [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]]
; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
; CHECK-NEXT: [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
; CHECK-NEXT: [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
; CHECK-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
; CHECK-NEXT: [[TMP19:%.*]] = shl i32 [[TMP18]], 16
; CHECK-NEXT: [[TMP20:%.*]] = ashr i32 [[TMP19]], 16
; CHECK-NEXT: [[TMP21:%.*]] = trunc i32 [[TMP20]] to i16
; CHECK-NEXT: store i16 [[TMP21]], i16 addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void
;
; GCN-LABEL: sdiv_i16:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i32 s1, s0, 16
; GCN-NEXT: v_cvt_f32_i32_e32 v0, s1
; GCN-NEXT: s_sext_i32_i16 s0, s0
; GCN-NEXT: v_cvt_f32_i32_e32 v1, s0
; GCN-NEXT: s_xor_b32 s0, s0, s1
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
; GCN-NEXT: s_ashr_i32 s0, s0, 30
; GCN-NEXT: s_or_b32 s0, s0, 1
; GCN-NEXT: v_mov_b32_e32 v3, s0
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: buffer_store_short v0, off, s[4:7], 0
; GCN-NEXT: s_endpgm
%r = sdiv i16 %x, %y
store i16 %r, i16 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @srem_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
; CHECK-LABEL: @srem_i16(
; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[X:%.*]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = sext i16 [[Y:%.*]] to i32
; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], 1
; CHECK-NEXT: [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
; CHECK-NEXT: [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]]
; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
; CHECK-NEXT: [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
; CHECK-NEXT: [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
; CHECK-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[TMP18]], [[TMP2]]
; CHECK-NEXT: [[TMP20:%.*]] = sub i32 [[TMP1]], [[TMP19]]
; CHECK-NEXT: [[TMP21:%.*]] = shl i32 [[TMP20]], 16
; CHECK-NEXT: [[TMP22:%.*]] = ashr i32 [[TMP21]], 16
; CHECK-NEXT: [[TMP23:%.*]] = trunc i32 [[TMP22]] to i16
; CHECK-NEXT: store i16 [[TMP23]], i16 addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void
;
; GCN-LABEL: srem_i16:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dword s4, s[0:1], 0xb
; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i32 s2, s4, 16
; GCN-NEXT: v_cvt_f32_i32_e32 v0, s2
; GCN-NEXT: s_sext_i32_i16 s3, s4
; GCN-NEXT: v_cvt_f32_i32_e32 v1, s3
; GCN-NEXT: s_xor_b32 s3, s3, s2
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
; GCN-NEXT: s_ashr_i32 s3, s3, 30
; GCN-NEXT: s_or_b32 s3, s3, 1
; GCN-NEXT: v_mov_b32_e32 v3, s3
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_mul_lo_u32 v0, v0, s2
; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GCN-NEXT: buffer_store_short v0, off, s[0:3], 0
; GCN-NEXT: s_endpgm
%r = srem i16 %x, %y
store i16 %r, i16 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @udiv_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
; CHECK-LABEL: @udiv_i8(
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[X:%.*]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[Y:%.*]] to i32
; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
; CHECK-NEXT: [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
; CHECK-NEXT: [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
; CHECK-NEXT: [[TMP16:%.*]] = and i32 [[TMP15]], 255
; CHECK-NEXT: [[TMP17:%.*]] = trunc i32 [[TMP16]] to i8
; CHECK-NEXT: store i8 [[TMP17]], i8 addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void
;
; GCN-LABEL: udiv_i8:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_cvt_f32_ubyte1_e32 v0, s0
; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
; GCN-NEXT: v_cvt_f32_ubyte0_e32 v2, s0
; GCN-NEXT: v_mul_f32_e32 v1, v2, v1
; GCN-NEXT: v_trunc_f32_e32 v1, v1
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v1
; GCN-NEXT: v_mad_f32 v1, -v1, v0, v2
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
; GCN-NEXT: buffer_store_byte v0, off, s[4:7], 0
; GCN-NEXT: s_endpgm
%r = udiv i8 %x, %y
store i8 %r, i8 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @urem_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
; CHECK-LABEL: @urem_i8(
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[X:%.*]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[Y:%.*]] to i32
; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float
; CHECK-NEXT: [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float
; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]])
; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]])
; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]])
; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i32
; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
; CHECK-NEXT: [[TMP13:%.*]] = fcmp fast oge float [[TMP11]], [[TMP12]]
; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i32 1, i32 0
; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
; CHECK-NEXT: [[TMP16:%.*]] = mul i32 [[TMP15]], [[TMP2]]
; CHECK-NEXT: [[TMP17:%.*]] = sub i32 [[TMP1]], [[TMP16]]
; CHECK-NEXT: [[TMP18:%.*]] = and i32 [[TMP17]], 255
; CHECK-NEXT: [[TMP19:%.*]] = trunc i32 [[TMP18]] to i8
; CHECK-NEXT: store i8 [[TMP19]], i8 addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void
;
; GCN-LABEL: urem_i8:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dword s4, s[0:1], 0xb
; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_cvt_f32_ubyte1_e32 v0, s4
; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
; GCN-NEXT: v_cvt_f32_ubyte0_e32 v2, s4
; GCN-NEXT: s_lshr_b32 s2, s4, 8
; GCN-NEXT: v_mul_f32_e32 v1, v2, v1
; GCN-NEXT: v_trunc_f32_e32 v1, v1
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v1
; GCN-NEXT: v_mad_f32 v1, -v1, v0, v2
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
; GCN-NEXT: v_mul_lo_u32 v0, v0, s2
; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
; GCN-NEXT: buffer_store_byte v0, off, s[0:3], 0
; GCN-NEXT: s_endpgm
%r = urem i8 %x, %y
store i8 %r, i8 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @sdiv_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
; CHECK-LABEL: @sdiv_i8(
; CHECK-NEXT: [[TMP1:%.*]] = sext i8 [[X:%.*]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = sext i8 [[Y:%.*]] to i32
; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], 1
; CHECK-NEXT: [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
; CHECK-NEXT: [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]]
; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
; CHECK-NEXT: [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
; CHECK-NEXT: [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
; CHECK-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
; CHECK-NEXT: [[TMP19:%.*]] = shl i32 [[TMP18]], 24
; CHECK-NEXT: [[TMP20:%.*]] = ashr i32 [[TMP19]], 24
; CHECK-NEXT: [[TMP21:%.*]] = trunc i32 [[TMP20]] to i8
; CHECK-NEXT: store i8 [[TMP21]], i8 addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void
;
; GCN-LABEL: sdiv_i8:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_bfe_i32 s1, s0, 0x80008
; GCN-NEXT: v_cvt_f32_i32_e32 v0, s1
; GCN-NEXT: s_sext_i32_i8 s0, s0
; GCN-NEXT: v_cvt_f32_i32_e32 v1, s0
; GCN-NEXT: s_xor_b32 s0, s0, s1
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
; GCN-NEXT: s_ashr_i32 s0, s0, 30
; GCN-NEXT: s_or_b32 s0, s0, 1
; GCN-NEXT: v_mov_b32_e32 v3, s0
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: buffer_store_byte v0, off, s[4:7], 0
; GCN-NEXT: s_endpgm
%r = sdiv i8 %x, %y
store i8 %r, i8 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @srem_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
; CHECK-LABEL: @srem_i8(
; CHECK-NEXT: [[TMP1:%.*]] = sext i8 [[X:%.*]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = sext i8 [[Y:%.*]] to i32
; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = ashr i32 [[TMP3]], 30
; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], 1
; CHECK-NEXT: [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float
; CHECK-NEXT: [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float
; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]])
; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]])
; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]]
; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
; CHECK-NEXT: [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
; CHECK-NEXT: [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
; CHECK-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[TMP18]], [[TMP2]]
; CHECK-NEXT: [[TMP20:%.*]] = sub i32 [[TMP1]], [[TMP19]]
; CHECK-NEXT: [[TMP21:%.*]] = shl i32 [[TMP20]], 24
; CHECK-NEXT: [[TMP22:%.*]] = ashr i32 [[TMP21]], 24
; CHECK-NEXT: [[TMP23:%.*]] = trunc i32 [[TMP22]] to i8
; CHECK-NEXT: store i8 [[TMP23]], i8 addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void
;
; GCN-LABEL: srem_i8:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_bfe_i32 s1, s0, 0x80008
; GCN-NEXT: v_cvt_f32_i32_e32 v0, s1
; GCN-NEXT: s_sext_i32_i8 s3, s0
; GCN-NEXT: v_cvt_f32_i32_e32 v1, s3
; GCN-NEXT: s_xor_b32 s1, s3, s1
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
; GCN-NEXT: s_ashr_i32 s1, s1, 30
; GCN-NEXT: s_or_b32 s1, s1, 1
; GCN-NEXT: v_mov_b32_e32 v3, s1
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GCN-NEXT: s_lshr_b32 s2, s0, 8
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_mul_lo_u32 v0, v0, s2
; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
; GCN-NEXT: buffer_store_byte v0, off, s[4:7], 0
; GCN-NEXT: s_endpgm
%r = srem i8 %x, %y
store i8 %r, i8 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @udiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @udiv_v4i32(
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float
; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]])
; CHECK-NEXT: [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41F0000000000000
; CHECK-NEXT: [[TMP6:%.*]] = fptoui float [[TMP5]] to i32
; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP2]] to i64
; CHECK-NEXT: [[TMP9:%.*]] = mul i64 [[TMP7]], [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
; CHECK-NEXT: [[TMP11:%.*]] = lshr i64 [[TMP9]], 32
; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32
; CHECK-NEXT: [[TMP13:%.*]] = sub i32 0, [[TMP10]]
; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[TMP12]], 0
; CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i32 [[TMP13]], i32 [[TMP10]]
; CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
; CHECK-NEXT: [[TMP17:%.*]] = zext i32 [[TMP6]] to i64
; CHECK-NEXT: [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]]
; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
; CHECK-NEXT: [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
; CHECK-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
; CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP6]], [[TMP21]]
; CHECK-NEXT: [[TMP23:%.*]] = sub i32 [[TMP6]], [[TMP21]]
; CHECK-NEXT: [[TMP24:%.*]] = select i1 [[TMP14]], i32 [[TMP22]], i32 [[TMP23]]
; CHECK-NEXT: [[TMP25:%.*]] = zext i32 [[TMP24]] to i64
; CHECK-NEXT: [[TMP26:%.*]] = zext i32 [[TMP1]] to i64
; CHECK-NEXT: [[TMP27:%.*]] = mul i64 [[TMP25]], [[TMP26]]
; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i32
; CHECK-NEXT: [[TMP29:%.*]] = lshr i64 [[TMP27]], 32
; CHECK-NEXT: [[TMP30:%.*]] = trunc i64 [[TMP29]] to i32
; CHECK-NEXT: [[TMP31:%.*]] = mul i32 [[TMP30]], [[TMP2]]
; CHECK-NEXT: [[TMP32:%.*]] = sub i32 [[TMP1]], [[TMP31]]
; CHECK-NEXT: [[TMP33:%.*]] = icmp uge i32 [[TMP32]], [[TMP2]]
; CHECK-NEXT: [[TMP34:%.*]] = icmp uge i32 [[TMP1]], [[TMP31]]
; CHECK-NEXT: [[TMP35:%.*]] = and i1 [[TMP33]], [[TMP34]]
; CHECK-NEXT: [[TMP36:%.*]] = add i32 [[TMP30]], 1
; CHECK-NEXT: [[TMP37:%.*]] = sub i32 [[TMP30]], 1
; CHECK-NEXT: [[TMP38:%.*]] = select i1 [[TMP35]], i32 [[TMP36]], i32 [[TMP30]]
; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP34]], i32 [[TMP38]], i32 [[TMP37]]
; CHECK-NEXT: [[TMP40:%.*]] = insertelement <4 x i32> undef, i32 [[TMP39]], i64 0
; CHECK-NEXT: [[TMP41:%.*]] = extractelement <4 x i32> [[X]], i64 1
; CHECK-NEXT: [[TMP42:%.*]] = extractelement <4 x i32> [[Y]], i64 1
; CHECK-NEXT: [[TMP43:%.*]] = uitofp i32 [[TMP42]] to float
; CHECK-NEXT: [[TMP44:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP43]])
; CHECK-NEXT: [[TMP45:%.*]] = fmul fast float [[TMP44]], 0x41F0000000000000
; CHECK-NEXT: [[TMP46:%.*]] = fptoui float [[TMP45]] to i32
; CHECK-NEXT: [[TMP47:%.*]] = zext i32 [[TMP46]] to i64
; CHECK-NEXT: [[TMP48:%.*]] = zext i32 [[TMP42]] to i64
; CHECK-NEXT: [[TMP49:%.*]] = mul i64 [[TMP47]], [[TMP48]]
; CHECK-NEXT: [[TMP50:%.*]] = trunc i64 [[TMP49]] to i32
; CHECK-NEXT: [[TMP51:%.*]] = lshr i64 [[TMP49]], 32
; CHECK-NEXT: [[TMP52:%.*]] = trunc i64 [[TMP51]] to i32
; CHECK-NEXT: [[TMP53:%.*]] = sub i32 0, [[TMP50]]
; CHECK-NEXT: [[TMP54:%.*]] = icmp eq i32 [[TMP52]], 0
; CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i32 [[TMP53]], i32 [[TMP50]]
; CHECK-NEXT: [[TMP56:%.*]] = zext i32 [[TMP55]] to i64
; CHECK-NEXT: [[TMP57:%.*]] = zext i32 [[TMP46]] to i64
; CHECK-NEXT: [[TMP58:%.*]] = mul i64 [[TMP56]], [[TMP57]]
; CHECK-NEXT: [[TMP59:%.*]] = trunc i64 [[TMP58]] to i32
; CHECK-NEXT: [[TMP60:%.*]] = lshr i64 [[TMP58]], 32
; CHECK-NEXT: [[TMP61:%.*]] = trunc i64 [[TMP60]] to i32
; CHECK-NEXT: [[TMP62:%.*]] = add i32 [[TMP46]], [[TMP61]]
; CHECK-NEXT: [[TMP63:%.*]] = sub i32 [[TMP46]], [[TMP61]]
; CHECK-NEXT: [[TMP64:%.*]] = select i1 [[TMP54]], i32 [[TMP62]], i32 [[TMP63]]
; CHECK-NEXT: [[TMP65:%.*]] = zext i32 [[TMP64]] to i64
; CHECK-NEXT: [[TMP66:%.*]] = zext i32 [[TMP41]] to i64
; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[TMP65]], [[TMP66]]
; CHECK-NEXT: [[TMP68:%.*]] = trunc i64 [[TMP67]] to i32
; CHECK-NEXT: [[TMP69:%.*]] = lshr i64 [[TMP67]], 32
; CHECK-NEXT: [[TMP70:%.*]] = trunc i64 [[TMP69]] to i32
; CHECK-NEXT: [[TMP71:%.*]] = mul i32 [[TMP70]], [[TMP42]]
; CHECK-NEXT: [[TMP72:%.*]] = sub i32 [[TMP41]], [[TMP71]]
; CHECK-NEXT: [[TMP73:%.*]] = icmp uge i32 [[TMP72]], [[TMP42]]
; CHECK-NEXT: [[TMP74:%.*]] = icmp uge i32 [[TMP41]], [[TMP71]]
; CHECK-NEXT: [[TMP75:%.*]] = and i1 [[TMP73]], [[TMP74]]
; CHECK-NEXT: [[TMP76:%.*]] = add i32 [[TMP70]], 1
; CHECK-NEXT: [[TMP77:%.*]] = sub i32 [[TMP70]], 1
; CHECK-NEXT: [[TMP78:%.*]] = select i1 [[TMP75]], i32 [[TMP76]], i32 [[TMP70]]
; CHECK-NEXT: [[TMP79:%.*]] = select i1 [[TMP74]], i32 [[TMP78]], i32 [[TMP77]]
; CHECK-NEXT: [[TMP80:%.*]] = insertelement <4 x i32> [[TMP40]], i32 [[TMP79]], i64 1
; CHECK-NEXT: [[TMP81:%.*]] = extractelement <4 x i32> [[X]], i64 2
; CHECK-NEXT: [[TMP82:%.*]] = extractelement <4 x i32> [[Y]], i64 2
; CHECK-NEXT: [[TMP83:%.*]] = uitofp i32 [[TMP82]] to float
; CHECK-NEXT: [[TMP84:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP83]])
; CHECK-NEXT: [[TMP85:%.*]] = fmul fast float [[TMP84]], 0x41F0000000000000
; CHECK-NEXT: [[TMP86:%.*]] = fptoui float [[TMP85]] to i32
; CHECK-NEXT: [[TMP87:%.*]] = zext i32 [[TMP86]] to i64
; CHECK-NEXT: [[TMP88:%.*]] = zext i32 [[TMP82]] to i64
; CHECK-NEXT: [[TMP89:%.*]] = mul i64 [[TMP87]], [[TMP88]]
; CHECK-NEXT: [[TMP90:%.*]] = trunc i64 [[TMP89]] to i32
; CHECK-NEXT: [[TMP91:%.*]] = lshr i64 [[TMP89]], 32
; CHECK-NEXT: [[TMP92:%.*]] = trunc i64 [[TMP91]] to i32
; CHECK-NEXT: [[TMP93:%.*]] = sub i32 0, [[TMP90]]
; CHECK-NEXT: [[TMP94:%.*]] = icmp eq i32 [[TMP92]], 0
; CHECK-NEXT: [[TMP95:%.*]] = select i1 [[TMP94]], i32 [[TMP93]], i32 [[TMP90]]
; CHECK-NEXT: [[TMP96:%.*]] = zext i32 [[TMP95]] to i64
; CHECK-NEXT: [[TMP97:%.*]] = zext i32 [[TMP86]] to i64
; CHECK-NEXT: [[TMP98:%.*]] = mul i64 [[TMP96]], [[TMP97]]
; CHECK-NEXT: [[TMP99:%.*]] = trunc i64 [[TMP98]] to i32
; CHECK-NEXT: [[TMP100:%.*]] = lshr i64 [[TMP98]], 32
; CHECK-NEXT: [[TMP101:%.*]] = trunc i64 [[TMP100]] to i32
; CHECK-NEXT: [[TMP102:%.*]] = add i32 [[TMP86]], [[TMP101]]
; CHECK-NEXT: [[TMP103:%.*]] = sub i32 [[TMP86]], [[TMP101]]
; CHECK-NEXT: [[TMP104:%.*]] = select i1 [[TMP94]], i32 [[TMP102]], i32 [[TMP103]]
; CHECK-NEXT: [[TMP105:%.*]] = zext i32 [[TMP104]] to i64
; CHECK-NEXT: [[TMP106:%.*]] = zext i32 [[TMP81]] to i64
; CHECK-NEXT: [[TMP107:%.*]] = mul i64 [[TMP105]], [[TMP106]]
; CHECK-NEXT: [[TMP108:%.*]] = trunc i64 [[TMP107]] to i32
; CHECK-NEXT: [[TMP109:%.*]] = lshr i64 [[TMP107]], 32
; CHECK-NEXT: [[TMP110:%.*]] = trunc i64 [[TMP109]] to i32
; CHECK-NEXT: [[TMP111:%.*]] = mul i32 [[TMP110]], [[TMP82]]
; CHECK-NEXT: [[TMP112:%.*]] = sub i32 [[TMP81]], [[TMP111]]
; CHECK-NEXT: [[TMP113:%.*]] = icmp uge i32 [[TMP112]], [[TMP82]]
; CHECK-NEXT: [[TMP114:%.*]] = icmp uge i32 [[TMP81]], [[TMP111]]
; CHECK-NEXT: [[TMP115:%.*]] = and i1 [[TMP113]], [[TMP114]]
; CHECK-NEXT: [[TMP116:%.*]] = add i32 [[TMP110]], 1
; CHECK-NEXT: [[TMP117:%.*]] = sub i32 [[TMP110]], 1
; CHECK-NEXT: [[TMP118:%.*]] = select i1 [[TMP115]], i32 [[TMP116]], i32 [[TMP110]]
; CHECK-NEXT: [[TMP119:%.*]] = select i1 [[TMP114]], i32 [[TMP118]], i32 [[TMP117]]
; CHECK-NEXT: [[TMP120:%.*]] = insertelement <4 x i32> [[TMP80]], i32 [[TMP119]], i64 2
; CHECK-NEXT: [[TMP121:%.*]] = extractelement <4 x i32> [[X]], i64 3
; CHECK-NEXT: [[TMP122:%.*]] = extractelement <4 x i32> [[Y]], i64 3
; CHECK-NEXT: [[TMP123:%.*]] = uitofp i32 [[TMP122]] to float
; CHECK-NEXT: [[TMP124:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP123]])
; CHECK-NEXT: [[TMP125:%.*]] = fmul fast float [[TMP124]], 0x41F0000000000000
; CHECK-NEXT: [[TMP126:%.*]] = fptoui float [[TMP125]] to i32
; CHECK-NEXT: [[TMP127:%.*]] = zext i32 [[TMP126]] to i64
; CHECK-NEXT: [[TMP128:%.*]] = zext i32 [[TMP122]] to i64
; CHECK-NEXT: [[TMP129:%.*]] = mul i64 [[TMP127]], [[TMP128]]
; CHECK-NEXT: [[TMP130:%.*]] = trunc i64 [[TMP129]] to i32
; CHECK-NEXT: [[TMP131:%.*]] = lshr i64 [[TMP129]], 32
; CHECK-NEXT: [[TMP132:%.*]] = trunc i64 [[TMP131]] to i32
; CHECK-NEXT: [[TMP133:%.*]] = sub i32 0, [[TMP130]]
; CHECK-NEXT: [[TMP134:%.*]] = icmp eq i32 [[TMP132]], 0
; CHECK-NEXT: [[TMP135:%.*]] = select i1 [[TMP134]], i32 [[TMP133]], i32 [[TMP130]]
; CHECK-NEXT: [[TMP136:%.*]] = zext i32 [[TMP135]] to i64
; CHECK-NEXT: [[TMP137:%.*]] = zext i32 [[TMP126]] to i64
; CHECK-NEXT: [[TMP138:%.*]] = mul i64 [[TMP136]], [[TMP137]]
; CHECK-NEXT: [[TMP139:%.*]] = trunc i64 [[TMP138]] to i32
; CHECK-NEXT: [[TMP140:%.*]] = lshr i64 [[TMP138]], 32
; CHECK-NEXT: [[TMP141:%.*]] = trunc i64 [[TMP140]] to i32
; CHECK-NEXT: [[TMP142:%.*]] = add i32 [[TMP126]], [[TMP141]]
; CHECK-NEXT: [[TMP143:%.*]] = sub i32 [[TMP126]], [[TMP141]]
; CHECK-NEXT: [[TMP144:%.*]] = select i1 [[TMP134]], i32 [[TMP142]], i32 [[TMP143]]
; CHECK-NEXT: [[TMP145:%.*]] = zext i32 [[TMP144]] to i64
; CHECK-NEXT: [[TMP146:%.*]] = zext i32 [[TMP121]] to i64
; CHECK-NEXT: [[TMP147:%.*]] = mul i64 [[TMP145]], [[TMP146]]
; CHECK-NEXT: [[TMP148:%.*]] = trunc i64 [[TMP147]] to i32
; CHECK-NEXT: [[TMP149:%.*]] = lshr i64 [[TMP147]], 32
; CHECK-NEXT: [[TMP150:%.*]] = trunc i64 [[TMP149]] to i32
; CHECK-NEXT: [[TMP151:%.*]] = mul i32 [[TMP150]], [[TMP122]]
; CHECK-NEXT: [[TMP152:%.*]] = sub i32 [[TMP121]], [[TMP151]]
; CHECK-NEXT: [[TMP153:%.*]] = icmp uge i32 [[TMP152]], [[TMP122]]
; CHECK-NEXT: [[TMP154:%.*]] = icmp uge i32 [[TMP121]], [[TMP151]]
; CHECK-NEXT: [[TMP155:%.*]] = and i1 [[TMP153]], [[TMP154]]
; CHECK-NEXT: [[TMP156:%.*]] = add i32 [[TMP150]], 1
; CHECK-NEXT: [[TMP157:%.*]] = sub i32 [[TMP150]], 1
; CHECK-NEXT: [[TMP158:%.*]] = select i1 [[TMP155]], i32 [[TMP156]], i32 [[TMP150]]
; CHECK-NEXT: [[TMP159:%.*]] = select i1 [[TMP154]], i32 [[TMP158]], i32 [[TMP157]]
; CHECK-NEXT: [[TMP160:%.*]] = insertelement <4 x i32> [[TMP120]], i32 [[TMP159]], i64 3
; CHECK-NEXT: store <4 x i32> [[TMP160]], <4 x i32> addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void
;
; GCN-LABEL: udiv_v4i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx8 s[8:15], s[0:1], 0xd
; GCN-NEXT: s_mov_b32 s6, 0x4f800000
; GCN-NEXT: s_load_dwordx2 s[16:17], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s19, 0xf000
; GCN-NEXT: s_mov_b32 s18, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13
; GCN-NEXT: v_cvt_f32_u32_e32 v7, s15
; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GCN-NEXT: v_mul_f32_e32 v0, s6, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v1, s6, v1
; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
; GCN-NEXT: v_mul_hi_u32 v2, v0, s12
; GCN-NEXT: v_mul_lo_u32 v3, v0, s12
; GCN-NEXT: v_mul_hi_u32 v4, v1, s13
; GCN-NEXT: v_mul_lo_u32 v5, v1, s13
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v3
; GCN-NEXT: v_cndmask_b32_e64 v2, v3, v6, s[0:1]
; GCN-NEXT: v_mul_hi_u32 v2, v2, v0
; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, v2, v0
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v2, v0
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1]
; GCN-NEXT: v_mul_hi_u32 v0, v0, s8
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v3, s[0:1]
; GCN-NEXT: v_mul_hi_u32 v2, v2, v1
; GCN-NEXT: v_mul_lo_u32 v3, v0, s12
; GCN-NEXT: v_add_i32_e32 v4, vcc, -1, v0
; GCN-NEXT: v_sub_i32_e32 v5, vcc, s8, v3
; GCN-NEXT: v_cmp_le_u32_e64 s[4:5], s12, v5
; GCN-NEXT: v_add_i32_e32 v5, vcc, v2, v1
; GCN-NEXT: v_subrev_i32_e32 v1, vcc, v2, v1
; GCN-NEXT: v_cvt_f32_u32_e32 v2, s14
; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1]
; GCN-NEXT: v_mul_hi_u32 v1, v1, s9
; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s8, v3
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GCN-NEXT: v_add_i32_e32 v3, vcc, 1, v0
; GCN-NEXT: s_and_b64 vcc, s[4:5], s[2:3]
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GCN-NEXT: v_mul_f32_e32 v2, s6, v2
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
; GCN-NEXT: v_mul_lo_u32 v3, v1, s13
; GCN-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[2:3]
; GCN-NEXT: v_mul_hi_u32 v6, v2, s14
; GCN-NEXT: v_mul_lo_u32 v5, v2, s14