-
Notifications
You must be signed in to change notification settings - Fork 10.7k
/
builtins-ppc-p10vsx.ll
241 lines (229 loc) · 7.91 KB
/
builtins-ppc-p10vsx.ll
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O0 \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-O0
; These test cases aims to test the builtins for the Power10 VSX vector
; instructions introduced in ISA 3.1.
declare i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8>, i32)
define signext i32 @test_vec_test_lsbb_all_ones(<16 x i8> %vuca) {
; CHECK-LABEL: test_vec_test_lsbb_all_ones:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvtlsbb cr0, v2
; CHECK-NEXT: mfocrf r3, 128
; CHECK-NEXT: srwi r3, r3, 31
; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-O0-LABEL: test_vec_test_lsbb_all_ones:
; CHECK-O0: # %bb.0: # %entry
; CHECK-O0-NEXT: xvtlsbb cr0, v2
; CHECK-O0-NEXT: mfocrf r3, 128
; CHECK-O0-NEXT: srwi r3, r3, 31
; CHECK-O0-NEXT: extsw r3, r3
; CHECK-O0-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i32 1)
ret i32 %0
}
define signext i32 @test_vec_test_lsbb_all_zeros(<16 x i8> %vuca) {
; CHECK-LABEL: test_vec_test_lsbb_all_zeros:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvtlsbb cr0, v2
; CHECK-NEXT: mfocrf r3, 128
; CHECK-NEXT: rlwinm r3, r3, 3, 31, 31
; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-O0-LABEL: test_vec_test_lsbb_all_zeros:
; CHECK-O0: # %bb.0: # %entry
; CHECK-O0-NEXT: xvtlsbb cr0, v2
; CHECK-O0-NEXT: mfocrf r3, 128
; CHECK-O0-NEXT: rlwinm r3, r3, 3, 31, 31
; CHECK-O0-NEXT: extsw r3, r3
; CHECK-O0-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i32 0)
ret i32 %0
}
define void @vec_xst_trunc_sc(<1 x i128> %__vec, i64 %__offset, i8* nocapture %__ptr) {
; CHECK-LABEL: vec_xst_trunc_sc:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stxvrbx v2, r6, r5
; CHECK-NEXT: blr
;
; CHECK-O0-LABEL: vec_xst_trunc_sc:
; CHECK-O0: # %bb.0: # %entry
; CHECK-O0-NEXT: li r3, 0
; CHECK-O0-NEXT: vextubrx r3, r3, v2
; CHECK-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
; CHECK-O0-NEXT: add r4, r6, r5
; CHECK-O0-NEXT: stb r3, 0(r4)
; CHECK-O0-NEXT: blr
entry:
%0 = bitcast <1 x i128> %__vec to <16 x i8>
%conv = extractelement <16 x i8> %0, i32 0
%add.ptr = getelementptr inbounds i8, i8* %__ptr, i64 %__offset
store i8 %conv, i8* %add.ptr, align 1
ret void
}
define void @vec_xst_trunc_uc(<1 x i128> %__vec, i64 %__offset, i8* nocapture %__ptr) {
; CHECK-LABEL: vec_xst_trunc_uc:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stxvrbx v2, r6, r5
; CHECK-NEXT: blr
;
; CHECK-O0-LABEL: vec_xst_trunc_uc:
; CHECK-O0: # %bb.0: # %entry
; CHECK-O0-NEXT: li r3, 0
; CHECK-O0-NEXT: vextubrx r3, r3, v2
; CHECK-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
; CHECK-O0-NEXT: add r4, r6, r5
; CHECK-O0-NEXT: stb r3, 0(r4)
; CHECK-O0-NEXT: blr
entry:
%0 = bitcast <1 x i128> %__vec to <16 x i8>
%conv = extractelement <16 x i8> %0, i32 0
%add.ptr = getelementptr inbounds i8, i8* %__ptr, i64 %__offset
store i8 %conv, i8* %add.ptr, align 1
ret void
}
define void @vec_xst_trunc_ss(<1 x i128> %__vec, i64 %__offset, i16* nocapture %__ptr) {
; CHECK-LABEL: vec_xst_trunc_ss:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sldi r3, r5, 1
; CHECK-NEXT: stxvrhx v2, r6, r3
; CHECK-NEXT: blr
;
; CHECK-O0-LABEL: vec_xst_trunc_ss:
; CHECK-O0: # %bb.0: # %entry
; CHECK-O0-NEXT: li r3, 0
; CHECK-O0-NEXT: vextuhrx r3, r3, v2
; CHECK-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
; CHECK-O0-NEXT: sldi r4, r5, 1
; CHECK-O0-NEXT: add r4, r6, r4
; CHECK-O0-NEXT: sth r3, 0(r4)
; CHECK-O0-NEXT: blr
entry:
%0 = bitcast <1 x i128> %__vec to <8 x i16>
%conv = extractelement <8 x i16> %0, i32 0
%add.ptr = getelementptr inbounds i16, i16* %__ptr, i64 %__offset
store i16 %conv, i16* %add.ptr, align 2
ret void
}
define void @vec_xst_trunc_us(<1 x i128> %__vec, i64 %__offset, i16* nocapture %__ptr) {
; CHECK-LABEL: vec_xst_trunc_us:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sldi r3, r5, 1
; CHECK-NEXT: stxvrhx v2, r6, r3
; CHECK-NEXT: blr
;
; CHECK-O0-LABEL: vec_xst_trunc_us:
; CHECK-O0: # %bb.0: # %entry
; CHECK-O0-NEXT: li r3, 0
; CHECK-O0-NEXT: vextuhrx r3, r3, v2
; CHECK-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
; CHECK-O0-NEXT: sldi r4, r5, 1
; CHECK-O0-NEXT: add r4, r6, r4
; CHECK-O0-NEXT: sth r3, 0(r4)
; CHECK-O0-NEXT: blr
entry:
%0 = bitcast <1 x i128> %__vec to <8 x i16>
%conv = extractelement <8 x i16> %0, i32 0
%add.ptr = getelementptr inbounds i16, i16* %__ptr, i64 %__offset
store i16 %conv, i16* %add.ptr, align 2
ret void
}
define void @vec_xst_trunc_si(<1 x i128> %__vec, i64 %__offset, i32* nocapture %__ptr) {
; CHECK-LABEL: vec_xst_trunc_si:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sldi r3, r5, 2
; CHECK-NEXT: stxvrwx v2, r6, r3
; CHECK-NEXT: blr
;
; CHECK-O0-LABEL: vec_xst_trunc_si:
; CHECK-O0: # %bb.0: # %entry
; CHECK-O0-NEXT: li r3, 0
; CHECK-O0-NEXT: vextuwrx r3, r3, v2
; CHECK-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
; CHECK-O0-NEXT: sldi r4, r5, 2
; CHECK-O0-NEXT: add r4, r6, r4
; CHECK-O0-NEXT: stw r3, 0(r4)
; CHECK-O0-NEXT: blr
entry:
%0 = bitcast <1 x i128> %__vec to <4 x i32>
%conv = extractelement <4 x i32> %0, i32 0
%add.ptr = getelementptr inbounds i32, i32* %__ptr, i64 %__offset
store i32 %conv, i32* %add.ptr, align 4
ret void
}
define void @vec_xst_trunc_ui(<1 x i128> %__vec, i64 %__offset, i32* nocapture %__ptr) {
; CHECK-LABEL: vec_xst_trunc_ui:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sldi r3, r5, 2
; CHECK-NEXT: stxvrwx v2, r6, r3
; CHECK-NEXT: blr
;
; CHECK-O0-LABEL: vec_xst_trunc_ui:
; CHECK-O0: # %bb.0: # %entry
; CHECK-O0-NEXT: li r3, 0
; CHECK-O0-NEXT: vextuwrx r3, r3, v2
; CHECK-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
; CHECK-O0-NEXT: sldi r4, r5, 2
; CHECK-O0-NEXT: add r4, r6, r4
; CHECK-O0-NEXT: stw r3, 0(r4)
; CHECK-O0-NEXT: blr
entry:
%0 = bitcast <1 x i128> %__vec to <4 x i32>
%conv = extractelement <4 x i32> %0, i32 0
%add.ptr = getelementptr inbounds i32, i32* %__ptr, i64 %__offset
store i32 %conv, i32* %add.ptr, align 4
ret void
}
define void @vec_xst_trunc_sll(<1 x i128> %__vec, i64 %__offset, i64* nocapture %__ptr) {
; CHECK-LABEL: vec_xst_trunc_sll:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sldi r3, r5, 3
; CHECK-NEXT: stxvrdx v2, r6, r3
; CHECK-NEXT: blr
;
; CHECK-O0-LABEL: vec_xst_trunc_sll:
; CHECK-O0: # %bb.0: # %entry
; CHECK-O0-NEXT: mfvsrld r3, v2
; CHECK-O0-NEXT: sldi r4, r5, 3
; CHECK-O0-NEXT: add r4, r6, r4
; CHECK-O0-NEXT: std r3, 0(r4)
; CHECK-O0-NEXT: blr
entry:
%0 = bitcast <1 x i128> %__vec to <2 x i64>
%conv = extractelement <2 x i64> %0, i32 0
%add.ptr = getelementptr inbounds i64, i64* %__ptr, i64 %__offset
store i64 %conv, i64* %add.ptr, align 8
ret void
}
define void @vec_xst_trunc_ull(<1 x i128> %__vec, i64 %__offset, i64* nocapture %__ptr) {
; CHECK-LABEL: vec_xst_trunc_ull:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sldi r3, r5, 3
; CHECK-NEXT: stxvrdx v2, r6, r3
; CHECK-NEXT: blr
;
; CHECK-O0-LABEL: vec_xst_trunc_ull:
; CHECK-O0: # %bb.0: # %entry
; CHECK-O0-NEXT: mfvsrld r3, v2
; CHECK-O0-NEXT: sldi r4, r5, 3
; CHECK-O0-NEXT: add r4, r6, r4
; CHECK-O0-NEXT: std r3, 0(r4)
; CHECK-O0-NEXT: blr
entry:
%0 = bitcast <1 x i128> %__vec to <2 x i64>
%conv = extractelement <2 x i64> %0, i32 0
%add.ptr = getelementptr inbounds i64, i64* %__ptr, i64 %__offset
store i64 %conv, i64* %add.ptr, align 8
ret void
}