/
MipsInstrInfo.td
2693 lines (2363 loc) · 107 KB
/
MipsInstrInfo.td
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//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the Mips implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Mips profiles and nodes
//===----------------------------------------------------------------------===//
def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
SDTCisSameAs<1, 2>,
SDTCisSameAs<3, 4>,
SDTCisInt<4>]>;
def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
SDTCisSameAs<1, 2>]>;
def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
[SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
SDTCisSameAs<0, 4>]>;
def SDTMipsLoadLR : SDTypeProfile<1, 2,
[SDTCisInt<0>, SDTCisPtrTy<1>,
SDTCisSameAs<0, 2>]>;
// Call
def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
SDNPVariadic]>;
// Tail call
def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
// Hi and Lo nodes are used to handle global addresses. Used on
// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
// static model. (nothing to do with Mips Registers Hi and Lo)
def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
// TlsGd node is used to handle General Dynamic TLS
def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
// TprelHi and TprelLo nodes are used to handle Local Exec TLS
def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
// Thread pointer
def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
// Return
def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
def MipsERet : SDNode<"MipsISD::ERet", SDTNone,
[SDNPHasChain, SDNPOptInGlue, SDNPSideEffect]>;
// These are target-independent nodes, but have target-specific formats.
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
[SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
[SDNPHasChain, SDNPSideEffect,
SDNPOptInGlue, SDNPOutGlue]>;
// Nodes used to extract LO/HI registers.
def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
// Node used to insert 32-bit integers to LOHI register pair.
def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
// Mult nodes.
def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
// MAdd*/MSub* nodes
def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
// DivRem(u) nodes
def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
[SDNPOutGlue]>;
def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
[SDNPOutGlue]>;
// Target constant nodes that are not part of any isel patterns and remain
// unchanged can cause instructions with illegal operands to be emitted.
// Wrapper node patterns give the instruction selector a chance to replace
// target constant nodes that would otherwise remain unchanged with ADDiu
// nodes. Without these wrapper node patterns, the following conditional move
// instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
// compiled:
// movn %got(d)($gp), %got(c)($gp), $4
// This instruction is illegal since movn can take only register operands.
def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
//===----------------------------------------------------------------------===//
// Mips Instruction Predicate Definitions.
//===----------------------------------------------------------------------===//
def HasMips2 : Predicate<"Subtarget->hasMips2()">,
AssemblerPredicate<"FeatureMips2">;
def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">,
AssemblerPredicate<"FeatureMips3_32">;
def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">,
AssemblerPredicate<"FeatureMips3_32r2">;
def HasMips3 : Predicate<"Subtarget->hasMips3()">,
AssemblerPredicate<"FeatureMips3">;
def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,
AssemblerPredicate<"FeatureMips4_32">;
def NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">,
AssemblerPredicate<"!FeatureMips4_32">;
def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,
AssemblerPredicate<"FeatureMips4_32r2">;
def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,
AssemblerPredicate<"FeatureMips5_32r2">;
def HasMips32 : Predicate<"Subtarget->hasMips32()">,
AssemblerPredicate<"FeatureMips32">;
def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,
AssemblerPredicate<"FeatureMips32r2">;
def HasMips32r5 : Predicate<"Subtarget->hasMips32r5()">,
AssemblerPredicate<"FeatureMips32r5">;
def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,
AssemblerPredicate<"FeatureMips32r6">;
def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,
AssemblerPredicate<"!FeatureMips32r6">;
def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
AssemblerPredicate<"FeatureGP64Bit">;
def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
AssemblerPredicate<"!FeatureGP64Bit">;
def IsPTR64bit : Predicate<"Subtarget->isABI_N64()">,
AssemblerPredicate<"FeaturePTR64Bit">;
def IsPTR32bit : Predicate<"!Subtarget->isABI_N64()">,
AssemblerPredicate<"!FeaturePTR64Bit">;
def HasMips64 : Predicate<"Subtarget->hasMips64()">,
AssemblerPredicate<"FeatureMips64">;
def NotMips64 : Predicate<"!Subtarget->hasMips64()">,
AssemblerPredicate<"!FeatureMips64">;
def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">,
AssemblerPredicate<"FeatureMips64r2">;
def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,
AssemblerPredicate<"FeatureMips64r6">;
def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
AssemblerPredicate<"!FeatureMips64r6">;
def HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">,
AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">;
def HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">,
AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">;
def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
AssemblerPredicate<"FeatureMips16">;
def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
AssemblerPredicate<"FeatureCnMips">;
def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">;
def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,
AssemblerPredicate<"!FeatureMips16">;
def NotDSP : Predicate<"!Subtarget->hasDSP()">;
def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">,
AssemblerPredicate<"FeatureMicroMips">;
def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">,
AssemblerPredicate<"!FeatureMicroMips">;
def IsLE : Predicate<"Subtarget->isLittle()">;
def IsBE : Predicate<"!Subtarget->isLittle()">;
def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
def UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">;
def HasEVA : Predicate<"Subtarget->hasEVA()">,
AssemblerPredicate<"FeatureEVA,FeatureMips32r2">;
def HasMSA : Predicate<"Subtarget->hasMSA()">,
AssemblerPredicate<"FeatureMSA">;
//===----------------------------------------------------------------------===//
// Mips GPR size adjectives.
// They are mutually exclusive.
//===----------------------------------------------------------------------===//
class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
class PTR_32 { list<Predicate> PTRPredicates = [IsPTR32bit]; }
class PTR_64 { list<Predicate> PTRPredicates = [IsPTR64bit]; }
//===----------------------------------------------------------------------===//
// Mips ISA/ASE membership and instruction group membership adjectives.
// They are mutually exclusive.
//===----------------------------------------------------------------------===//
// FIXME: I'd prefer to use additive predicates to build the instruction sets
// but we are short on assembler feature bits at the moment. Using a
// subtractive predicate will hopefully keep us under the 32 predicate
// limit long enough to develop an alternative way to handle P1||P2
// predicates.
class ISA_MIPS1_NOT_4_32 {
list<Predicate> InsnPredicates = [NotMips4_32];
}
class ISA_MIPS1_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
}
class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
class ISA_MIPS2_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
}
class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
class ISA_MIPS3_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
}
class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
class ISA_MIPS32_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
}
class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
class ISA_MIPS32R2_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
}
class ISA_MIPS32R5 { list<Predicate> InsnPredicates = [HasMips32r5]; }
class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
class ISA_MIPS64_NOT_64R6 {
list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
}
class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
class ISA_MICROMIPS { list<Predicate> InsnPredicates = [InMicroMips]; }
class ISA_MICROMIPS32R6 {
list<Predicate> InsnPredicates = [HasMicroMips32r6];
}
class ISA_MICROMIPS64R6 {
list<Predicate> InsnPredicates = [HasMicroMips64r6];
}
class ISA_MICROMIPS32_NOT_MIPS32R6 {
list<Predicate> InsnPredicates = [InMicroMips, NotMips32r6];
}
class INSN_EVA { list<Predicate> InsnPredicates = [HasEVA]; }
class INSN_EVA_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6, HasEVA];
}
// The portions of MIPS-III that were also added to MIPS32
class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
// The portions of MIPS-III that were also added to MIPS32 but were removed in
// MIPS32r6 and MIPS64r6.
class INSN_MIPS3_32_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
}
// The portions of MIPS-III that were also added to MIPS32
class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
// The portions of MIPS-IV that were also added to MIPS32 but were removed in
// MIPS32r6 and MIPS64r6.
class INSN_MIPS4_32_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
}
// The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
// MIPS32r6 and MIPS64r6.
class INSN_MIPS4_32R2_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
}
// The portions of MIPS-V that were also added to MIPS32r2 but were removed in
// MIPS32r6 and MIPS64r6.
class INSN_MIPS5_32R2_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
}
class ASE_CNMIPS {
list<Predicate> InsnPredicates = [HasCnMips];
}
class ASE_MIPS64_CNMIPS {
list<Predicate> InsnPredicates = [HasMips64, HasCnMips];
}
class ASE_MSA {
list<Predicate> InsnPredicates = [HasMSA];
}
class ASE_MSA_NOT_MSA64 {
list<Predicate> InsnPredicates = [HasMSA, NotMips64];
}
class ASE_MSA64 {
list<Predicate> InsnPredicates = [HasMSA, HasMips64];
}
// Class used for separating microMIPSr6 and microMIPS (r3) instruction.
// It can be used only on instructions that doesn't inherit PredicateControl.
class ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl {
let InsnPredicates = [InMicroMips, NotMips32r6, NotMips64r6];
}
class ASE_NOT_DSP {
list<Predicate> InsnPredicates = [NotDSP];
}
//===----------------------------------------------------------------------===//
class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
let EncodingPredicates = [HasStdEnc];
}
class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
InstAlias<Asm, Result, Emit>, PredicateControl;
class IsCommutable {
bit isCommutable = 1;
}
class IsBranch {
bit isBranch = 1;
bit isCTI = 1;
}
class IsReturn {
bit isReturn = 1;
bit isCTI = 1;
}
class IsCall {
bit isCall = 1;
bit isCTI = 1;
}
class IsTailCall {
bit isCall = 1;
bit isTerminator = 1;
bit isReturn = 1;
bit isBarrier = 1;
bit hasExtraSrcRegAllocReq = 1;
bit isCodeGenOnly = 1;
bit isCTI = 1;
}
class IsAsCheapAsAMove {
bit isAsCheapAsAMove = 1;
}
class NeverHasSideEffects {
bit hasSideEffects = 0;
}
//===----------------------------------------------------------------------===//
// Instruction format superclass
//===----------------------------------------------------------------------===//
include "MipsInstrFormats.td"
//===----------------------------------------------------------------------===//
// Mips Operand, Complex Patterns and Transformations Definitions.
//===----------------------------------------------------------------------===//
class ConstantSImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [],
int Offset = 0> : AsmOperandClass {
let Name = "ConstantSImm" # Bits # "_" # Offset;
let RenderMethod = "addConstantSImmOperands<" # Bits # ", " # Offset # ">";
let PredicateMethod = "isConstantSImm<" # Bits # ", " # Offset # ">";
let SuperClasses = Supers;
let DiagnosticType = "SImm" # Bits # "_" # Offset;
}
class ConstantUImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [],
int Offset = 0> : AsmOperandClass {
let Name = "ConstantUImm" # Bits # "_" # Offset;
let RenderMethod = "addConstantUImmOperands<" # Bits # ", " # Offset # ">";
let PredicateMethod = "isConstantUImm<" # Bits # ", " # Offset # ">";
let SuperClasses = Supers;
let DiagnosticType = "UImm" # Bits # "_" # Offset;
}
class ConstantUImmRangeAsmOperandClass<int Bottom, int Top,
list<AsmOperandClass> Supers = []>
: AsmOperandClass {
let Name = "ConstantUImmRange" # Bottom # "_" # Top;
let RenderMethod = "addImmOperands";
let PredicateMethod = "isConstantUImmRange<" # Bottom # ", " # Top # ">";
let SuperClasses = Supers;
let DiagnosticType = "UImmRange" # Bottom # "_" # Top;
}
class SImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []>
: AsmOperandClass {
let Name = "SImm" # Bits;
let RenderMethod = "addSImmOperands<" # Bits # ">";
let PredicateMethod = "isSImm<" # Bits # ">";
let SuperClasses = Supers;
let DiagnosticType = "SImm" # Bits;
}
class UImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []>
: AsmOperandClass {
let Name = "UImm" # Bits;
let RenderMethod = "addUImmOperands<" # Bits # ">";
let PredicateMethod = "isUImm<" # Bits # ">";
let SuperClasses = Supers;
let DiagnosticType = "UImm" # Bits;
}
// AsmOperandClasses require a strict ordering which is difficult to manage
// as a hierarchy. Instead, we use a linear ordering and impose an order that
// is in some places arbitrary.
//
// Here the rules that are in use:
// * Wider immediates are a superset of narrower immediates:
// uimm4 < uimm5 < uimm6
// * For the same bit-width, unsigned immediates are a superset of signed
// immediates::
// simm4 < uimm4 < simm5 < uimm5
// * For the same upper-bound, signed immediates are a superset of unsigned
// immediates:
// uimm3 < simm4 < uimm4 < simm4
// * Modified immediates are a superset of ordinary immediates:
// uimm5 < uimm5_plus1 (1..32) < uimm5_plus32 (32..63) < uimm6
// The term 'superset' starts to break down here since the uimm5_plus* classes
// are not true supersets of uimm5 (but they are still subsets of uimm6).
// * 'Relaxed' immediates are supersets of the corresponding unsigned immediate.
// uimm16 < uimm16_relaxed
// * The codeGen pattern type is arbitrarily ordered.
// uimm5 < uimm5_64, and uimm5 < vsplat_uimm5
// This is entirely arbitrary. We need an ordering and what we pick is
// unimportant since only one is possible for a given mnemonic.
def SImm32RelaxedAsmOperandClass
: SImmAsmOperandClass<32, []> {
let Name = "SImm32_Relaxed";
let PredicateMethod = "isAnyImm<32>";
let DiagnosticType = "SImm32_Relaxed";
}
def SImm32AsmOperandClass
: SImmAsmOperandClass<32, [SImm32RelaxedAsmOperandClass]>;
def ConstantUImm26AsmOperandClass
: ConstantUImmAsmOperandClass<26, [SImm32AsmOperandClass]>;
def ConstantUImm20AsmOperandClass
: ConstantUImmAsmOperandClass<20, [ConstantUImm26AsmOperandClass]>;
def UImm16RelaxedAsmOperandClass
: UImmAsmOperandClass<16, [ConstantUImm20AsmOperandClass]> {
let Name = "UImm16_Relaxed";
let PredicateMethod = "isAnyImm<16>";
let DiagnosticType = "UImm16_Relaxed";
}
def UImm16AsmOperandClass
: UImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]>;
def SImm16RelaxedAsmOperandClass
: SImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]> {
let Name = "SImm16_Relaxed";
let PredicateMethod = "isAnyImm<16>";
let DiagnosticType = "SImm16_Relaxed";
}
def SImm16AsmOperandClass
: SImmAsmOperandClass<16, [SImm16RelaxedAsmOperandClass]>;
def ConstantSImm10Lsl3AsmOperandClass : AsmOperandClass {
let Name = "SImm10Lsl3";
let RenderMethod = "addImmOperands";
let PredicateMethod = "isScaledSImm<10, 3>";
let SuperClasses = [SImm16AsmOperandClass];
let DiagnosticType = "SImm10_Lsl3";
}
def ConstantSImm10Lsl2AsmOperandClass : AsmOperandClass {
let Name = "SImm10Lsl2";
let RenderMethod = "addImmOperands";
let PredicateMethod = "isScaledSImm<10, 2>";
let SuperClasses = [ConstantSImm10Lsl3AsmOperandClass];
let DiagnosticType = "SImm10_Lsl2";
}
def ConstantSImm11AsmOperandClass
: ConstantSImmAsmOperandClass<11, [ConstantSImm10Lsl2AsmOperandClass]>;
def ConstantSImm10Lsl1AsmOperandClass : AsmOperandClass {
let Name = "SImm10Lsl1";
let RenderMethod = "addImmOperands";
let PredicateMethod = "isScaledSImm<10, 1>";
let SuperClasses = [ConstantSImm11AsmOperandClass];
let DiagnosticType = "SImm10_Lsl1";
}
def ConstantUImm10AsmOperandClass
: ConstantUImmAsmOperandClass<10, [ConstantSImm10Lsl1AsmOperandClass]>;
def ConstantSImm10AsmOperandClass
: ConstantSImmAsmOperandClass<10, [ConstantUImm10AsmOperandClass]>;
def ConstantSImm9AsmOperandClass
: ConstantSImmAsmOperandClass<9, [ConstantSImm10AsmOperandClass]>;
def ConstantSImm7Lsl2AsmOperandClass : AsmOperandClass {
let Name = "SImm7Lsl2";
let RenderMethod = "addImmOperands";
let PredicateMethod = "isScaledSImm<7, 2>";
let SuperClasses = [ConstantSImm9AsmOperandClass];
let DiagnosticType = "SImm7_Lsl2";
}
def ConstantUImm8AsmOperandClass
: ConstantUImmAsmOperandClass<8, [ConstantSImm7Lsl2AsmOperandClass]>;
def ConstantUImm7Sub1AsmOperandClass
: ConstantUImmAsmOperandClass<7, [ConstantUImm8AsmOperandClass], -1> {
// Specify the names since the -1 offset causes invalid identifiers otherwise.
let Name = "UImm7_N1";
let DiagnosticType = "UImm7_N1";
}
def ConstantUImm7AsmOperandClass
: ConstantUImmAsmOperandClass<7, [ConstantUImm7Sub1AsmOperandClass]>;
def ConstantUImm6Lsl2AsmOperandClass : AsmOperandClass {
let Name = "UImm6Lsl2";
let RenderMethod = "addImmOperands";
let PredicateMethod = "isScaledUImm<6, 2>";
let SuperClasses = [ConstantUImm7AsmOperandClass];
let DiagnosticType = "UImm6_Lsl2";
}
def ConstantUImm6AsmOperandClass
: ConstantUImmAsmOperandClass<6, [ConstantUImm6Lsl2AsmOperandClass]>;
def ConstantSImm6AsmOperandClass
: ConstantSImmAsmOperandClass<6, [ConstantUImm6AsmOperandClass]>;
def ConstantUImm5Lsl2AsmOperandClass : AsmOperandClass {
let Name = "UImm5Lsl2";
let RenderMethod = "addImmOperands";
let PredicateMethod = "isScaledUImm<5, 2>";
let SuperClasses = [ConstantSImm6AsmOperandClass];
let DiagnosticType = "UImm5_Lsl2";
}
def ConstantUImm5_Range2_64AsmOperandClass
: ConstantUImmRangeAsmOperandClass<2, 64, [ConstantUImm5Lsl2AsmOperandClass]>;
def ConstantUImm5Plus33AsmOperandClass
: ConstantUImmAsmOperandClass<5, [ConstantUImm5_Range2_64AsmOperandClass],
33>;
def ConstantUImm5ReportUImm6AsmOperandClass
: ConstantUImmAsmOperandClass<5, [ConstantUImm5Plus33AsmOperandClass]> {
let Name = "ConstantUImm5_0_Report_UImm6";
let DiagnosticType = "UImm5_0_Report_UImm6";
}
def ConstantUImm5Plus32AsmOperandClass
: ConstantUImmAsmOperandClass<
5, [ConstantUImm5ReportUImm6AsmOperandClass], 32>;
def ConstantUImm5Plus32NormalizeAsmOperandClass
: ConstantUImmAsmOperandClass<5, [ConstantUImm5Plus32AsmOperandClass], 32> {
let Name = "ConstantUImm5_32_Norm";
// We must also subtract 32 when we render the operand.
let RenderMethod = "addConstantUImmOperands<5, 32, -32>";
}
def ConstantUImm5Plus1AsmOperandClass
: ConstantUImmAsmOperandClass<
5, [ConstantUImm5Plus32NormalizeAsmOperandClass], 1>;
def ConstantUImm5AsmOperandClass
: ConstantUImmAsmOperandClass<5, [ConstantUImm5Plus1AsmOperandClass]>;
def ConstantSImm5AsmOperandClass
: ConstantSImmAsmOperandClass<5, [ConstantUImm5AsmOperandClass]>;
def ConstantUImm4AsmOperandClass
: ConstantUImmAsmOperandClass<4, [ConstantSImm5AsmOperandClass]>;
def ConstantSImm4AsmOperandClass
: ConstantSImmAsmOperandClass<4, [ConstantUImm4AsmOperandClass]>;
def ConstantUImm3AsmOperandClass
: ConstantUImmAsmOperandClass<3, [ConstantSImm4AsmOperandClass]>;
def ConstantUImm2Plus1AsmOperandClass
: ConstantUImmAsmOperandClass<2, [ConstantUImm3AsmOperandClass], 1>;
def ConstantUImm2AsmOperandClass
: ConstantUImmAsmOperandClass<2, [ConstantUImm3AsmOperandClass]>;
def ConstantUImm1AsmOperandClass
: ConstantUImmAsmOperandClass<1, [ConstantUImm2AsmOperandClass]>;
def ConstantImmzAsmOperandClass : AsmOperandClass {
let Name = "ConstantImmz";
let RenderMethod = "addConstantUImmOperands<1>";
let PredicateMethod = "isConstantImmz";
let SuperClasses = [ConstantUImm1AsmOperandClass];
let DiagnosticType = "Immz";
}
def MipsJumpTargetAsmOperand : AsmOperandClass {
let Name = "JumpTarget";
let ParserMethod = "parseJumpTarget";
let PredicateMethod = "isImm";
let RenderMethod = "addImmOperands";
}
// Instruction operand types
def jmptarget : Operand<OtherVT> {
let EncoderMethod = "getJumpTargetOpValue";
let ParserMatchClass = MipsJumpTargetAsmOperand;
}
def brtarget : Operand<OtherVT> {
let EncoderMethod = "getBranchTargetOpValue";
let OperandType = "OPERAND_PCREL";
let DecoderMethod = "DecodeBranchTarget";
let ParserMatchClass = MipsJumpTargetAsmOperand;
}
def brtarget1SImm16 : Operand<OtherVT> {
let EncoderMethod = "getBranchTargetOpValue1SImm16";
let OperandType = "OPERAND_PCREL";
let DecoderMethod = "DecodeBranchTarget1SImm16";
let ParserMatchClass = MipsJumpTargetAsmOperand;
}
def calltarget : Operand<iPTR> {
let EncoderMethod = "getJumpTargetOpValue";
let ParserMatchClass = MipsJumpTargetAsmOperand;
}
def imm64: Operand<i64>;
def simm19_lsl2 : Operand<i32> {
let EncoderMethod = "getSimm19Lsl2Encoding";
let DecoderMethod = "DecodeSimm19Lsl2";
let ParserMatchClass = MipsJumpTargetAsmOperand;
}
def simm18_lsl3 : Operand<i32> {
let EncoderMethod = "getSimm18Lsl3Encoding";
let DecoderMethod = "DecodeSimm18Lsl3";
let ParserMatchClass = MipsJumpTargetAsmOperand;
}
// Zero
def uimmz : Operand<i32> {
let PrintMethod = "printUImm<0>";
let ParserMatchClass = ConstantImmzAsmOperandClass;
}
// size operand of ins instruction
def uimm_range_2_64 : Operand<i32> {
let PrintMethod = "printUImm<6, 2>";
let EncoderMethod = "getSizeInsEncoding";
let DecoderMethod = "DecodeInsSize";
let ParserMatchClass = ConstantUImm5_Range2_64AsmOperandClass;
}
// Unsigned Operands
foreach I = {1, 2, 3, 4, 5, 6, 7, 8, 10, 20, 26} in
def uimm # I : Operand<i32> {
let PrintMethod = "printUImm<" # I # ">";
let ParserMatchClass =
!cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass");
}
def uimm2_plus1 : Operand<i32> {
let PrintMethod = "printUImm<2, 1>";
let EncoderMethod = "getUImmWithOffsetEncoding<2, 1>";
let DecoderMethod = "DecodeUImmWithOffset<2, 1>";
let ParserMatchClass = ConstantUImm2Plus1AsmOperandClass;
}
def uimm5_plus1 : Operand<i32> {
let PrintMethod = "printUImm<5, 1>";
let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>";
let DecoderMethod = "DecodeUImmWithOffset<5, 1>";
let ParserMatchClass = ConstantUImm5Plus1AsmOperandClass;
}
def uimm5_plus32 : Operand<i32> {
let PrintMethod = "printUImm<5, 32>";
let ParserMatchClass = ConstantUImm5Plus32AsmOperandClass;
}
def uimm5_plus33 : Operand<i32> {
let PrintMethod = "printUImm<5, 33>";
let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>";
let DecoderMethod = "DecodeUImmWithOffset<5, 1>";
let ParserMatchClass = ConstantUImm5Plus33AsmOperandClass;
}
def uimm5_inssize_plus1 : Operand<i32> {
let PrintMethod = "printUImm<6>";
let ParserMatchClass = ConstantUImm5Plus1AsmOperandClass;
let EncoderMethod = "getSizeInsEncoding";
let DecoderMethod = "DecodeInsSize";
}
def uimm5_plus32_normalize : Operand<i32> {
let PrintMethod = "printUImm<5>";
let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass;
}
def uimm5_lsl2 : Operand<OtherVT> {
let EncoderMethod = "getUImm5Lsl2Encoding";
let DecoderMethod = "DecodeUImmWithOffsetAndScale<5, 0, 4>";
let ParserMatchClass = ConstantUImm5Lsl2AsmOperandClass;
}
def uimm5_plus32_normalize_64 : Operand<i64> {
let PrintMethod = "printUImm<5>";
let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass;
}
def uimm6_lsl2 : Operand<OtherVT> {
let EncoderMethod = "getUImm6Lsl2Encoding";
let DecoderMethod = "DecodeUImmWithOffsetAndScale<6, 0, 4>";
let ParserMatchClass = ConstantUImm6Lsl2AsmOperandClass;
}
foreach I = {16} in
def uimm # I : Operand<i32> {
let PrintMethod = "printUImm<" # I # ">";
let ParserMatchClass =
!cast<AsmOperandClass>("UImm" # I # "AsmOperandClass");
}
// Like uimm16_64 but coerces simm16 to uimm16.
def uimm16_relaxed : Operand<i32> {
let PrintMethod = "printUImm<16>";
let ParserMatchClass =
!cast<AsmOperandClass>("UImm16RelaxedAsmOperandClass");
}
foreach I = {5} in
def uimm # I # _64 : Operand<i64> {
let PrintMethod = "printUImm<" # I # ">";
let ParserMatchClass =
!cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass");
}
foreach I = {16} in
def uimm # I # _64 : Operand<i64> {
let PrintMethod = "printUImm<" # I # ">";
let ParserMatchClass =
!cast<AsmOperandClass>("UImm" # I # "AsmOperandClass");
}
// Like uimm16_64 but coerces simm16 to uimm16.
def uimm16_64_relaxed : Operand<i64> {
let PrintMethod = "printUImm<16>";
let ParserMatchClass =
!cast<AsmOperandClass>("UImm16RelaxedAsmOperandClass");
}
// Like uimm5 but reports a less confusing error for 32-63 when
// an instruction alias permits that.
def uimm5_report_uimm6 : Operand<i32> {
let PrintMethod = "printUImm<5>";
let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass;
}
// Like uimm5_64 but reports a less confusing error for 32-63 when
// an instruction alias permits that.
def uimm5_64_report_uimm6 : Operand<i64> {
let PrintMethod = "printUImm<5>";
let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass;
}
foreach I = {1, 2, 3, 4} in
def uimm # I # _ptr : Operand<iPTR> {
let PrintMethod = "printUImm<" # I # ">";
let ParserMatchClass =
!cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass");
}
foreach I = {1, 2, 3, 4, 5, 6, 8} in
def vsplat_uimm # I : Operand<vAny> {
let PrintMethod = "printUImm<" # I # ">";
let ParserMatchClass =
!cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass");
}
// Signed operands
foreach I = {4, 5, 6, 9, 10, 11} in
def simm # I : Operand<i32> {
let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ">";
let ParserMatchClass =
!cast<AsmOperandClass>("ConstantSImm" # I # "AsmOperandClass");
}
foreach I = {1, 2, 3} in
def simm10_lsl # I : Operand<i32> {
let DecoderMethod = "DecodeSImmWithOffsetAndScale<10, " # I # ">";
let ParserMatchClass =
!cast<AsmOperandClass>("ConstantSImm10Lsl" # I # "AsmOperandClass");
}
foreach I = {10} in
def simm # I # _64 : Operand<i64> {
let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ">";
let ParserMatchClass =
!cast<AsmOperandClass>("ConstantSImm" # I # "AsmOperandClass");
}
foreach I = {5, 10} in
def vsplat_simm # I : Operand<vAny> {
let ParserMatchClass =
!cast<AsmOperandClass>("ConstantSImm" # I # "AsmOperandClass");
}
def simm7_lsl2 : Operand<OtherVT> {
let EncoderMethod = "getSImm7Lsl2Encoding";
let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ", 0, 4>";
let ParserMatchClass = ConstantSImm7Lsl2AsmOperandClass;
}
foreach I = {16, 32} in
def simm # I : Operand<i32> {
let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ">";
let ParserMatchClass = !cast<AsmOperandClass>("SImm" # I # "AsmOperandClass");
}
// Like simm16 but coerces uimm16 to simm16.
def simm16_relaxed : Operand<i32> {
let DecoderMethod = "DecodeSImmWithOffsetAndScale<16>";
let ParserMatchClass = !cast<AsmOperandClass>("SImm16RelaxedAsmOperandClass");
}
def simm16_64 : Operand<i64> {
let DecoderMethod = "DecodeSImmWithOffsetAndScale<16>";
let ParserMatchClass = !cast<AsmOperandClass>("SImm16AsmOperandClass");
}
// Like simm32 but coerces uimm32 to simm32.
def simm32_relaxed : Operand<i32> {
let DecoderMethod = "DecodeSImmWithOffsetAndScale<32>";
let ParserMatchClass = !cast<AsmOperandClass>("SImm32RelaxedAsmOperandClass");
}
// This is almost the same as a uimm7 but 0x7f is interpreted as -1.
def li16_imm : Operand<i32> {
let DecoderMethod = "DecodeLi16Imm";
let ParserMatchClass = ConstantUImm7Sub1AsmOperandClass;
}
def MipsMemAsmOperand : AsmOperandClass {
let Name = "Mem";
let ParserMethod = "parseMemOperand";
}
def MipsMemSimm9AsmOperand : AsmOperandClass {
let Name = "MemOffsetSimm9";
let SuperClasses = [MipsMemAsmOperand];
let RenderMethod = "addMemOperands";
let ParserMethod = "parseMemOperand";
let PredicateMethod = "isMemWithSimmOffset<9>";
let DiagnosticType = "MemSImm9";
}
def MipsMemSimm10AsmOperand : AsmOperandClass {
let Name = "MemOffsetSimm10";
let SuperClasses = [MipsMemAsmOperand];
let RenderMethod = "addMemOperands";
let ParserMethod = "parseMemOperand";
let PredicateMethod = "isMemWithSimmOffset<10>";
let DiagnosticType = "MemSImm10";
}
foreach I = {1, 2, 3} in
def MipsMemSimm10Lsl # I # AsmOperand : AsmOperandClass {
let Name = "MemOffsetSimm10_" # I;
let SuperClasses = [MipsMemAsmOperand];
let RenderMethod = "addMemOperands";
let ParserMethod = "parseMemOperand";
let PredicateMethod = "isMemWithSimmOffset<10, " # I # ">";
let DiagnosticType = "MemSImm10Lsl" # I;
}
def MipsMemSimm11AsmOperand : AsmOperandClass {
let Name = "MemOffsetSimm11";
let SuperClasses = [MipsMemAsmOperand];
let RenderMethod = "addMemOperands";
let ParserMethod = "parseMemOperand";
let PredicateMethod = "isMemWithSimmOffset<11>";
let DiagnosticType = "MemSImm11";
}
def MipsMemSimm16AsmOperand : AsmOperandClass {
let Name = "MemOffsetSimm16";
let SuperClasses = [MipsMemAsmOperand];
let RenderMethod = "addMemOperands";
let ParserMethod = "parseMemOperand";
let PredicateMethod = "isMemWithSimmOffset<16>";
let DiagnosticType = "MemSImm16";
}
def MipsInvertedImmoperand : AsmOperandClass {
let Name = "InvNum";
let RenderMethod = "addImmOperands";
let ParserMethod = "parseInvNum";
}
def InvertedImOperand : Operand<i32> {
let ParserMatchClass = MipsInvertedImmoperand;
}
def InvertedImOperand64 : Operand<i64> {
let ParserMatchClass = MipsInvertedImmoperand;
}
class mem_generic : Operand<iPTR> {
let PrintMethod = "printMemOperand";
let MIOperandInfo = (ops ptr_rc, simm16);
let EncoderMethod = "getMemEncoding";
let ParserMatchClass = MipsMemAsmOperand;
let OperandType = "OPERAND_MEMORY";
}
// Address operand
def mem : mem_generic;
// MSA specific address operand
def mem_msa : mem_generic {
let MIOperandInfo = (ops ptr_rc, simm10);
let EncoderMethod = "getMSAMemEncoding";
}
def mem_simm9 : mem_generic {
let MIOperandInfo = (ops ptr_rc, simm9);
let EncoderMethod = "getMemEncoding";
let ParserMatchClass = MipsMemSimm9AsmOperand;
}
def mem_simm10 : mem_generic {
let MIOperandInfo = (ops ptr_rc, simm10);
let EncoderMethod = "getMemEncoding";
let ParserMatchClass = MipsMemSimm10AsmOperand;
}
foreach I = {1, 2, 3} in
def mem_simm10_lsl # I : mem_generic {
let MIOperandInfo = (ops ptr_rc, !cast<Operand>("simm10_lsl" # I));
let EncoderMethod = "getMemEncoding<" # I # ">";
let ParserMatchClass =
!cast<AsmOperandClass>("MipsMemSimm10Lsl" # I # "AsmOperand");
}
def mem_simm11 : mem_generic {
let MIOperandInfo = (ops ptr_rc, simm11);
let EncoderMethod = "getMemEncoding";
let ParserMatchClass = MipsMemSimm11AsmOperand;
}
def mem_simm16 : mem_generic {
let MIOperandInfo = (ops ptr_rc, simm16);
let EncoderMethod = "getMemEncoding";
let ParserMatchClass = MipsMemSimm16AsmOperand;
}
def mem_ea : Operand<iPTR> {
let PrintMethod = "printMemOperandEA";
let MIOperandInfo = (ops ptr_rc, simm16);
let EncoderMethod = "getMemEncoding";
let OperandType = "OPERAND_MEMORY";
}
def PtrRC : Operand<iPTR> {
let MIOperandInfo = (ops ptr_rc);
let DecoderMethod = "DecodePtrRegisterClass";
let ParserMatchClass = GPR32AsmOperand;
}
// size operand of ins instruction
def size_ins : Operand<i32> {
let EncoderMethod = "getSizeInsEncoding";
let DecoderMethod = "DecodeInsSize";
}
// Transformation Function - get the lower 16 bits.
def LO16 : SDNodeXForm<imm, [{
return getImm(N, N->getZExtValue() & 0xFFFF);
}]>;
// Transformation Function - get the higher 16 bits.
def HI16 : SDNodeXForm<imm, [{
return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);