-
Notifications
You must be signed in to change notification settings - Fork 10.8k
/
AVRInstrInfo.td
2580 lines (2277 loc) · 88.3 KB
/
AVRInstrInfo.td
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
//===-- AVRInstrInfo.td - AVR Instruction defs -------------*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file describes the AVR instructions in TableGen format.
//
//===----------------------------------------------------------------------===//
include "AVRInstrFormats.td"
//===----------------------------------------------------------------------===//
// AVR Type Profiles
//===----------------------------------------------------------------------===//
def SDT_AVRCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
def SDT_AVRCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
def SDT_AVRCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
def SDT_AVRWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
def SDT_AVRBrcond
: SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>;
def SDT_AVRCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
def SDT_AVRTst : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
def SDT_AVRSelectCC
: SDTypeProfile<1, 3,
[SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
//===----------------------------------------------------------------------===//
// AVR Specific Node Definitions
//===----------------------------------------------------------------------===//
def AVRretglue : SDNode<"AVRISD::RET_GLUE", SDTNone,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
def AVRretiglue : SDNode<"AVRISD::RETI_GLUE", SDTNone,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
def AVRcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AVRCallSeqStart,
[SDNPHasChain, SDNPOutGlue]>;
def AVRcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AVRCallSeqEnd,
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
def AVRcall : SDNode<"AVRISD::CALL", SDT_AVRCall,
[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>;
def AVRWrapper : SDNode<"AVRISD::WRAPPER", SDT_AVRWrapper>;
def AVRbrcond
: SDNode<"AVRISD::BRCOND", SDT_AVRBrcond, [SDNPHasChain, SDNPInGlue]>;
def AVRcmp : SDNode<"AVRISD::CMP", SDT_AVRCmp, [SDNPOutGlue]>;
def AVRcmpc : SDNode<"AVRISD::CMPC", SDT_AVRCmp, [SDNPInGlue, SDNPOutGlue]>;
def AVRtst : SDNode<"AVRISD::TST", SDT_AVRTst, [SDNPOutGlue]>;
def AVRselectcc : SDNode<"AVRISD::SELECT_CC", SDT_AVRSelectCC, [SDNPInGlue]>;
// Shift nodes.
def AVRlsl : SDNode<"AVRISD::LSL", SDTIntUnaryOp>;
def AVRlsr : SDNode<"AVRISD::LSR", SDTIntUnaryOp>;
def AVRrol : SDNode<"AVRISD::ROL", SDTIntUnaryOp>;
def AVRror : SDNode<"AVRISD::ROR", SDTIntUnaryOp>;
def AVRasr : SDNode<"AVRISD::ASR", SDTIntUnaryOp>;
def AVRlslhi : SDNode<"AVRISD::LSLHI", SDTIntUnaryOp>;
def AVRlsrlo : SDNode<"AVRISD::LSRLO", SDTIntUnaryOp>;
def AVRasrlo : SDNode<"AVRISD::ASRLO", SDTIntUnaryOp>;
def AVRlslbn : SDNode<"AVRISD::LSLBN", SDTIntBinOp>;
def AVRlsrbn : SDNode<"AVRISD::LSRBN", SDTIntBinOp>;
def AVRasrbn : SDNode<"AVRISD::ASRBN", SDTIntBinOp>;
def AVRlslwn : SDNode<"AVRISD::LSLWN", SDTIntBinOp>;
def AVRlsrwn : SDNode<"AVRISD::LSRWN", SDTIntBinOp>;
def AVRasrwn : SDNode<"AVRISD::ASRWN", SDTIntBinOp>;
def AVRlslw : SDNode<"AVRISD::LSLW", SDTIntShiftDOp>;
def AVRlsrw : SDNode<"AVRISD::LSRW", SDTIntShiftDOp>;
def AVRasrw : SDNode<"AVRISD::ASRW", SDTIntShiftDOp>;
// Pseudo shift nodes for non-constant shift amounts.
def AVRlslLoop : SDNode<"AVRISD::LSLLOOP", SDTIntShiftOp>;
def AVRlsrLoop : SDNode<"AVRISD::LSRLOOP", SDTIntShiftOp>;
def AVRrolLoop : SDNode<"AVRISD::ROLLOOP", SDTIntShiftOp>;
def AVRrorLoop : SDNode<"AVRISD::RORLOOP", SDTIntShiftOp>;
def AVRasrLoop : SDNode<"AVRISD::ASRLOOP", SDTIntShiftOp>;
// SWAP node.
def AVRSwap : SDNode<"AVRISD::SWAP", SDTIntUnaryOp>;
//===----------------------------------------------------------------------===//
// AVR Operands, Complex Patterns and Transformations Definitions.
//===----------------------------------------------------------------------===//
def imm8_neg_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(-N->getAPIntValue(), SDLoc(N), MVT::i8);
}]>;
def imm16_neg_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(-N->getAPIntValue(), SDLoc(N), MVT::i16);
}]>;
def imm0_63_neg : PatLeaf<(imm), [{
int64_t val = -N->getSExtValue();
return val >= 0 && val < 64;
}], imm16_neg_XFORM>;
def uimm6 : PatLeaf<(imm), [{ return isUInt<6>(N->getZExtValue()); }]>;
// imm_com8_XFORM - Return the complement of a imm_com8 value
def imm_com8_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(
~((uint8_t) N->getZExtValue()), SDLoc(N), MVT::i8);
}]>;
// imm_com8 - Match an immediate that is a complement
// of a 8-bit immediate.
// Note: this pattern doesn't require an encoder method and such, as it's
// only used on aliases (Pat<> and InstAlias<>). The actual encoding
// is handled by the destination instructions, which use imm_com8.
def imm_com8_asmoperand : AsmOperandClass { let Name = "ImmCom8"; }
def imm_com8 : Operand<i8> { let ParserMatchClass = imm_com8_asmoperand; }
def ioaddr_XFORM : SDNodeXForm<imm, [{
uint8_t offset = Subtarget->getIORegisterOffset();
return CurDAG->getTargetConstant(
uint8_t(N->getZExtValue()) - offset, SDLoc(N), MVT::i8);
}]>;
def iobitpos8_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(
Log2_32(uint8_t(N->getZExtValue())), SDLoc(N), MVT::i8);
}]>;
def iobitposn8_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(
Log2_32(uint8_t(~N->getZExtValue())), SDLoc(N), MVT::i8);
}]>;
def ioaddr8 : PatLeaf<(imm), [{
uint8_t offset = Subtarget->getIORegisterOffset();
uint64_t val = N->getZExtValue() - offset;
return val < 0x40;
}], ioaddr_XFORM>;
def lowioaddr8 : PatLeaf<(imm), [{
uint8_t offset = Subtarget->getIORegisterOffset();
uint64_t val = N->getZExtValue() - offset;
return val < 0x20;
}], ioaddr_XFORM>;
def ioaddr16 : PatLeaf<(imm), [{
uint8_t offset = Subtarget->getIORegisterOffset();
uint64_t val = N->getZExtValue() - offset;
return val < 0x3f;
}], ioaddr_XFORM>;
def iobitpos8 : PatLeaf<(imm), [{
return isPowerOf2_32(uint8_t(N->getZExtValue()));
}], iobitpos8_XFORM>;
def iobitposn8 : PatLeaf<(imm), [{
return isPowerOf2_32(uint8_t(~N->getZExtValue()));
}], iobitposn8_XFORM>;
def MemriAsmOperand : AsmOperandClass {
let Name = "Memri";
let ParserMethod = "parseMemriOperand";
}
/// Address operand for `reg+imm` used by STD and LDD.
def memri : Operand<iPTR> {
let MIOperandInfo = (ops PTRDISPREGS, i16imm);
let PrintMethod = "printMemri";
let EncoderMethod = "encodeMemri";
let DecoderMethod = "decodeMemri";
let ParserMatchClass = MemriAsmOperand;
}
// Address operand for `SP+imm` used by STD{W}SPQRr
def memspi : Operand<iPTR> {
let MIOperandInfo = (ops GPRSP, i16imm);
let PrintMethod = "printMemspi";
}
def relbrtarget_7 : Operand<OtherVT> {
let PrintMethod = "printPCRelImm";
let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_7_pcrel>";
}
def brtarget_13 : Operand<OtherVT> {
let PrintMethod = "printPCRelImm";
let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_13_pcrel>";
}
def rcalltarget_13 : Operand<i16> {
let PrintMethod = "printPCRelImm";
let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_13_pcrel>";
}
// The target of a 22 or 16-bit call/jmp instruction.
def call_target : Operand<iPTR> {
let EncoderMethod = "encodeCallTarget";
let DecoderMethod = "decodeCallTarget";
}
// A 16-bit address (which can lead to an R_AVR_16 relocation).
def imm16 : Operand<i16> { let EncoderMethod = "encodeImm<AVR::fixup_16, 2>"; }
// A 7-bit address (which can lead to an R_AVR_LDS_STS_16 relocation).
def imm7tiny : Operand<i16> {
let EncoderMethod = "encodeImm<AVR::fixup_lds_sts_16, 0>";
}
/// A 6-bit immediate used in the ADIW/SBIW instructions.
def imm_arith6 : Operand<i16> {
let EncoderMethod = "encodeImm<AVR::fixup_6_adiw, 0>";
}
/// An 8-bit immediate inside an instruction with the same format
/// as the `LDI` instruction (the `FRdK` format).
def imm_ldi8 : Operand<i8> {
let EncoderMethod = "encodeImm<AVR::fixup_ldi, 0>";
}
/// A 5-bit port number used in SBIC and friends (the `FIOBIT` format).
def imm_port5 : Operand<i8> {
let EncoderMethod = "encodeImm<AVR::fixup_port5, 0>";
}
/// A 6-bit port number used in the `IN` instruction and friends (the
/// `FIORdA` format.
def imm_port6 : Operand<i8> {
let EncoderMethod = "encodeImm<AVR::fixup_port6, 0>";
}
// Addressing mode pattern reg+imm6
def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], [SDNPWantRoot]>;
// AsmOperand class for a pointer register.
// Used with the LD/ST family of instructions.
// See FSTLD in AVRInstrFormats.td
def PtrRegAsmOperand : AsmOperandClass { let Name = "Reg"; }
// A special operand type for the LD/ST instructions.
// It converts the pointer register number into a two-bit field used in the
// instruction.
def LDSTPtrReg : Operand<i16> {
let MIOperandInfo = (ops PTRREGS);
let EncoderMethod = "encodeLDSTPtrReg";
let ParserMatchClass = PtrRegAsmOperand;
}
// A special operand type for the LDD/STD instructions.
// It behaves identically to the LD/ST version, except restricts
// the pointer registers to Y and Z.
def LDDSTDPtrReg : Operand<i16> {
let MIOperandInfo = (ops PTRDISPREGS);
let EncoderMethod = "encodeLDSTPtrReg";
let ParserMatchClass = PtrRegAsmOperand;
}
//===----------------------------------------------------------------------===//
// AVR predicates for subtarget features
//===----------------------------------------------------------------------===//
def HasSRAM : Predicate<"Subtarget->hasSRAM()">,
AssemblerPredicate<(all_of FeatureSRAM)>;
def HasJMPCALL : Predicate<"Subtarget->hasJMPCALL()">,
AssemblerPredicate<(all_of FeatureJMPCALL)>;
def HasIJMPCALL : Predicate<"Subtarget->hasIJMPCALL()">,
AssemblerPredicate<(all_of FeatureIJMPCALL)>;
def HasEIJMPCALL : Predicate<"Subtarget->hasEIJMPCALL()">,
AssemblerPredicate<(all_of FeatureEIJMPCALL)>;
def HasADDSUBIW : Predicate<"Subtarget->hasADDSUBIW()">,
AssemblerPredicate<(all_of FeatureADDSUBIW)>;
def HasSmallStack : Predicate<"Subtarget->HasSmallStack()">,
AssemblerPredicate<(all_of FeatureSmallStack)>;
def HasMOVW : Predicate<"Subtarget->hasMOVW()">,
AssemblerPredicate<(all_of FeatureMOVW)>;
def HasLPM : Predicate<"Subtarget->hasLPM()">,
AssemblerPredicate<(all_of FeatureLPM)>;
def HasLPMX : Predicate<"Subtarget->hasLPMX()">,
AssemblerPredicate<(all_of FeatureLPMX)>;
def HasELPM : Predicate<"Subtarget->hasELPM()">,
AssemblerPredicate<(all_of FeatureELPM)>;
def HasELPMX : Predicate<"Subtarget->hasELPMX()">,
AssemblerPredicate<(all_of FeatureELPMX)>;
def HasSPM : Predicate<"Subtarget->hasSPM()">,
AssemblerPredicate<(all_of FeatureSPM)>;
def HasSPMX : Predicate<"Subtarget->hasSPMX()">,
AssemblerPredicate<(all_of FeatureSPMX)>;
def HasDES : Predicate<"Subtarget->hasDES()">,
AssemblerPredicate<(all_of FeatureDES)>;
def SupportsRMW : Predicate<"Subtarget->supportsRMW()">,
AssemblerPredicate<(all_of FeatureRMW)>;
def SupportsMultiplication : Predicate<"Subtarget->supportsMultiplication()">,
AssemblerPredicate<(all_of FeatureMultiplication)>;
def HasBREAK : Predicate<"Subtarget->hasBREAK()">,
AssemblerPredicate<(all_of FeatureBREAK)>;
def HasTinyEncoding : Predicate<"Subtarget->hasTinyEncoding()">,
AssemblerPredicate<(all_of FeatureTinyEncoding)>;
def HasNonTinyEncoding : Predicate<"!Subtarget->hasTinyEncoding()">,
AssemblerPredicate<(any_of (not FeatureTinyEncoding))>;
// AVR specific condition code. These correspond to AVR_*_COND in
// AVRInstrInfo.td. They must be kept in synch.
def AVR_COND_EQ : PatLeaf<(i8 0)>;
def AVR_COND_NE : PatLeaf<(i8 1)>;
def AVR_COND_GE : PatLeaf<(i8 2)>;
def AVR_COND_LT : PatLeaf<(i8 3)>;
def AVR_COND_SH : PatLeaf<(i8 4)>;
def AVR_COND_LO : PatLeaf<(i8 5)>;
def AVR_COND_MI : PatLeaf<(i8 6)>;
def AVR_COND_PL : PatLeaf<(i8 7)>;
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// AVR Instruction list
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into
// a stack adjustment and the codegen must know that they may modify the stack
// pointer before prolog-epilog rewriting occurs.
// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
// sub / add which can clobber SREG.
let Defs = [SP, SREG], Uses = [SP] in {
def ADJCALLSTACKDOWN : Pseudo<(outs),
(ins i16imm
: $amt, i16imm
: $amt2),
"#ADJCALLSTACKDOWN", [(AVRcallseq_start timm
: $amt, timm
: $amt2)]>;
// R31R30 is used to update SP. It is normally free because it is a
// call-clobbered register but it is necessary to set it as a def as the
// register allocator might use it in rare cases (for rematerialization, it
// seems). hasSideEffects needs to be set to true so this instruction isn't
// considered dead.
let Defs = [R31R30], hasSideEffects = 1 in def ADJCALLSTACKUP
: Pseudo<(outs),
(ins i16imm
: $amt1, i16imm
: $amt2),
"#ADJCALLSTACKUP", [(AVRcallseq_end timm
: $amt1, timm
: $amt2)]>;
}
//===----------------------------------------------------------------------===//
// Addition
//===----------------------------------------------------------------------===//
let isCommutable = 1, Constraints = "$src = $rd", Defs = [SREG] in {
// ADD Rd, Rr
// Adds two 8-bit registers.
def ADDRdRr
: FRdRr<0b0000, 0b11,
(outs GPR8
: $rd),
(ins GPR8
: $src, GPR8
: $rr),
"add\t$rd, $rr",
[(set i8
: $rd, (add i8
: $src, i8
: $rr)),
(implicit SREG)]>;
// ADDW Rd+1:Rd, Rr+1:Rr
// Pseudo instruction to add four 8-bit registers as two 16-bit values.
//
// Expands to:
// add Rd, Rr
// adc Rd+1, Rr+1
def ADDWRdRr
: Pseudo<(outs DREGS
: $rd),
(ins DREGS
: $src, DREGS
: $rr),
"addw\t$rd, $rr",
[(set i16
: $rd, (add i16
: $src, i16
: $rr)),
(implicit SREG)]>;
// ADC Rd, Rr
// Adds two 8-bit registers with carry.
let Uses = [SREG] in def ADCRdRr
: FRdRr<0b0001, 0b11,
(outs GPR8
: $rd),
(ins GPR8
: $src, GPR8
: $rr),
"adc\t$rd, $rr",
[(set i8
: $rd, (adde i8
: $src, i8
: $rr)),
(implicit SREG)]>;
// ADCW Rd+1:Rd, Rr+1:Rr
// Pseudo instruction to add four 8-bit registers as two 16-bit values with
// carry.
//
// Expands to:
// adc Rd, Rr
// adc Rd+1, Rr+1
let Uses = [SREG] in def ADCWRdRr : Pseudo<(outs DREGS
: $rd),
(ins DREGS
: $src, DREGS
: $rr),
"adcw\t$rd, $rr", [
(set i16
: $rd, (adde i16
: $src, i16
: $rr)),
(implicit SREG)
]>;
// AIDW Rd, k
// Adds an immediate 6-bit value K to Rd, placing the result in Rd.
def ADIWRdK
: FWRdK<0b0,
(outs IWREGS
: $rd),
(ins IWREGS
: $src, imm_arith6
: $k),
"adiw\t$rd, $k",
[(set i16
: $rd, (add i16
: $src, uimm6
: $k)),
(implicit SREG)]>,
Requires<[HasADDSUBIW]>;
}
//===----------------------------------------------------------------------===//
// Subtraction
//===----------------------------------------------------------------------===//
let Constraints = "$src = $rd", Defs = [SREG] in {
// SUB Rd, Rr
// Subtracts the 8-bit value of Rr from Rd and places the value in Rd.
def SUBRdRr
: FRdRr<0b0001, 0b10,
(outs GPR8
: $rd),
(ins GPR8
: $src, GPR8
: $rr),
"sub\t$rd, $rr",
[(set i8
: $rd, (sub i8
: $src, i8
: $rr)),
(implicit SREG)]>;
// SUBW Rd+1:Rd, Rr+1:Rr
// Subtracts two 16-bit values and places the result into Rd.
//
// Expands to:
// sub Rd, Rr
// sbc Rd+1, Rr+1
def SUBWRdRr
: Pseudo<(outs DREGS
: $rd),
(ins DREGS
: $src, DREGS
: $rr),
"subw\t$rd, $rr",
[(set i16
: $rd, (sub i16
: $src, i16
: $rr)),
(implicit SREG)]>;
def SUBIRdK
: FRdK<0b0101,
(outs LD8
: $rd),
(ins LD8
: $src, imm_ldi8
: $k),
"subi\t$rd, $k",
[(set i8
: $rd, (sub i8
: $src, imm
: $k)),
(implicit SREG)]>;
// SUBIW Rd+1:Rd, K+1:K
//
// Expands to:
// subi Rd, K
// sbci Rd+1, K+1
def SUBIWRdK
: Pseudo<(outs DLDREGS
: $rd),
(ins DLDREGS
: $src, i16imm
: $rr),
"subiw\t$rd, $rr",
[(set i16
: $rd, (sub i16
: $src, imm
: $rr)),
(implicit SREG)]>;
def SBIWRdK
: FWRdK<0b1,
(outs IWREGS
: $rd),
(ins IWREGS
: $src, imm_arith6
: $k),
"sbiw\t$rd, $k",
[(set i16
: $rd, (sub i16
: $src, uimm6
: $k)),
(implicit SREG)]>,
Requires<[HasADDSUBIW]>;
// Subtract with carry operations which must read the carry flag in SREG.
let Uses = [SREG] in {
def SBCRdRr
: FRdRr<0b0000, 0b10,
(outs GPR8
: $rd),
(ins GPR8
: $src, GPR8
: $rr),
"sbc\t$rd, $rr",
[(set i8
: $rd, (sube i8
: $src, i8
: $rr)),
(implicit SREG)]>;
// SBCW Rd+1:Rd, Rr+1:Rr
//
// Expands to:
// sbc Rd, Rr
// sbc Rd+1, Rr+1
def SBCWRdRr : Pseudo<(outs DREGS
: $rd),
(ins DREGS
: $src, DREGS
: $rr),
"sbcw\t$rd, $rr", [
(set i16
: $rd, (sube i16
: $src, i16
: $rr)),
(implicit SREG)
]>;
def SBCIRdK
: FRdK<0b0100,
(outs LD8
: $rd),
(ins LD8
: $src, imm_ldi8
: $k),
"sbci\t$rd, $k",
[(set i8
: $rd, (sube i8
: $src, imm
: $k)),
(implicit SREG)]>;
// SBCIW Rd+1:Rd, K+1:K
// sbci Rd, K
// sbci Rd+1, K+1
def SBCIWRdK : Pseudo<(outs DLDREGS
: $rd),
(ins DLDREGS
: $src, i16imm
: $rr),
"sbciw\t$rd, $rr", [
(set i16
: $rd, (sube i16
: $src, imm
: $rr)),
(implicit SREG)
]>;
}
}
//===----------------------------------------------------------------------===//
// Increment and Decrement
//===----------------------------------------------------------------------===//
let Constraints = "$src = $rd", Defs = [SREG] in {
def INCRd
: FRd<0b1001, 0b0100011,
(outs GPR8
: $rd),
(ins GPR8
: $src),
"inc\t$rd", [(set i8
: $rd, (add i8
: $src, 1)),
(implicit SREG)]>;
def DECRd
: FRd<0b1001, 0b0101010,
(outs GPR8
: $rd),
(ins GPR8
: $src),
"dec\t$rd", [(set i8
: $rd, (add i8
: $src, -1)),
(implicit SREG)]>;
}
//===----------------------------------------------------------------------===//
// Multiplication
//===----------------------------------------------------------------------===//
let isCommutable = 1, Defs = [R1, R0, SREG] in {
// MUL Rd, Rr
// Multiplies Rd by Rr and places the result into R1:R0.
let usesCustomInserter = 1 in {
def MULRdRr : FRdRr<0b1001, 0b11, (outs),
(ins GPR8
: $rd, GPR8
: $rr),
"mul\t$rd, $rr",
[/*(set R1, R0, (smullohi i8:$rd, i8:$rr))*/]>,
Requires<[SupportsMultiplication]>;
def MULSRdRr : FMUL2RdRr<0, (outs),
(ins LD8
: $rd, LD8
: $rr),
"muls\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;
}
def MULSURdRr : FMUL2RdRr<1, (outs),
(ins LD8lo
: $rd, LD8lo
: $rr),
"mulsu\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;
def FMUL : FFMULRdRr<0b01, (outs),
(ins LD8lo
: $rd, LD8lo
: $rr),
"fmul\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;
def FMULS : FFMULRdRr<0b10, (outs),
(ins LD8lo
: $rd, LD8lo
: $rr),
"fmuls\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;
def FMULSU : FFMULRdRr<0b11, (outs),
(ins LD8lo
: $rd, LD8lo
: $rr),
"fmulsu\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;
}
let Defs =
[R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R1,
R0] in def DESK : FDES<(outs),
(ins i8imm
: $k),
"des\t$k", []>,
Requires<[HasDES]>;
//===----------------------------------------------------------------------===//
// Logic
//===----------------------------------------------------------------------===//
let Constraints = "$src = $rd", Defs = [SREG] in {
// Register-Register logic instructions (which have the
// property of commutativity).
let isCommutable = 1 in {
def ANDRdRr
: FRdRr<0b0010, 0b00,
(outs GPR8
: $rd),
(ins GPR8
: $src, GPR8
: $rr),
"and\t$rd, $rr",
[(set i8
: $rd, (and i8
: $src, i8
: $rr)),
(implicit SREG)]>;
// ANDW Rd+1:Rd, Rr+1:Rr
//
// Expands to:
// and Rd, Rr
// and Rd+1, Rr+1
def ANDWRdRr : Pseudo<(outs DREGS
: $rd),
(ins DREGS
: $src, DREGS
: $rr),
"andw\t$rd, $rr", [
(set i16
: $rd, (and i16
: $src, i16
: $rr)),
(implicit SREG)
]>;
def ORRdRr
: FRdRr<0b0010, 0b10,
(outs GPR8
: $rd),
(ins GPR8
: $src, GPR8
: $rr),
"or\t$rd, $rr",
[(set i8
: $rd, (or i8
: $src, i8
: $rr)),
(implicit SREG)]>;
// ORW Rd+1:Rd, Rr+1:Rr
//
// Expands to:
// or Rd, Rr
// or Rd+1, Rr+1
def ORWRdRr : Pseudo<(outs DREGS
: $rd),
(ins DREGS
: $src, DREGS
: $rr),
"orw\t$rd, $rr", [
(set i16
: $rd, (or i16
: $src, i16
: $rr)),
(implicit SREG)
]>;
def EORRdRr
: FRdRr<0b0010, 0b01,
(outs GPR8
: $rd),
(ins GPR8
: $src, GPR8
: $rr),
"eor\t$rd, $rr",
[(set i8
: $rd, (xor i8
: $src, i8
: $rr)),
(implicit SREG)]>;
// EORW Rd+1:Rd, Rr+1:Rr
//
// Expands to:
// eor Rd, Rr
// eor Rd+1, Rr+1
def EORWRdRr : Pseudo<(outs DREGS
: $rd),
(ins DREGS
: $src, DREGS
: $rr),
"eorw\t$rd, $rr", [
(set i16
: $rd, (xor i16
: $src, i16
: $rr)),
(implicit SREG)
]>;
}
def ANDIRdK
: FRdK<0b0111,
(outs LD8
: $rd),
(ins LD8
: $src, imm_ldi8
: $k),
"andi\t$rd, $k",
[(set i8
: $rd, (and i8
: $src, imm
: $k)),
(implicit SREG)]>;
// ANDI Rd+1:Rd, K+1:K
//
// Expands to:
// andi Rd, K
// andi Rd+1, K+1
def ANDIWRdK
: Pseudo<(outs DLDREGS
: $rd),
(ins DLDREGS
: $src, i16imm
: $k),
"andiw\t$rd, $k",
[(set i16
: $rd, (and i16
: $src, imm
: $k)),
(implicit SREG)]>;
def ORIRdK
: FRdK<0b0110,
(outs LD8
: $rd),
(ins LD8
: $src, imm_ldi8
: $k),
"ori\t$rd, $k",
[(set i8
: $rd, (or i8
: $src, imm
: $k)),
(implicit SREG)]>;
// ORIW Rd+1:Rd, K+1,K
//
// Expands to:
// ori Rd, K
// ori Rd+1, K+1
def ORIWRdK
: Pseudo<(outs DLDREGS
: $rd),
(ins DLDREGS
: $src, i16imm
: $rr),
"oriw\t$rd, $rr",
[(set i16
: $rd, (or i16
: $src, imm
: $rr)),
(implicit SREG)]>;
}
//===----------------------------------------------------------------------===//
// One's/Two's Complement
//===----------------------------------------------------------------------===//
let Constraints = "$src = $rd", Defs = [SREG] in {
def COMRd
: FRd<0b1001, 0b0100000,
(outs GPR8
: $rd),
(ins GPR8
: $src),
"com\t$rd", [(set i8
: $rd, (not i8
: $src)),
(implicit SREG)]>;
// COMW Rd+1:Rd
//
// Expands to:
// com Rd
// com Rd+1
def COMWRd : Pseudo<(outs DREGS
: $rd),
(ins DREGS
: $src),
"comw\t$rd",
[(set i16
: $rd, (not i16
: $src)),
(implicit SREG)]>;
def NEGRd
: FRd<0b1001, 0b0100001,
(outs GPR8
: $rd),
(ins GPR8
: $src),
"neg\t$rd", [(set i8
: $rd, (ineg i8
: $src)),
(implicit SREG)]>;
// NEGW Rd+1:Rd
//
// Expands to:
// neg Rd+1
// neg Rd
// sbc Rd+1, r1
let hasSideEffects=0 in
def NEGWRd : Pseudo<(outs DREGS:$rd),
(ins DREGS:$src, GPR8:$zero),
"negw\t$rd",
[]>;
}
// TST Rd
// Test for zero of minus.
// This operation is identical to a `Rd AND Rd`.
def : InstAlias<"tst\t$rd", (ANDRdRr GPR8 : $rd, GPR8 : $rd)>;
// SBR Rd, K
//
// Mnemonic alias to 'ORI Rd, K'. Same bit pattern, same operands,
// same everything.
def : InstAlias<"sbr\t$rd, $k",
(ORIRdK LD8
: $rd, imm_ldi8
: $k),
/* Disable display, so we don't override ORI */ 0>;
//===----------------------------------------------------------------------===//
// Jump instructions
//===----------------------------------------------------------------------===//
let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
def RJMPk : FBRk<0, (outs),
(ins brtarget_13
: $k),
"rjmp\t$k", [(br bb
: $k)]>;
let isIndirectBranch = 1,
Uses = [R31R30] in def IJMP
: F16<0b1001010000001001, (outs), (ins), "ijmp", []>,
Requires<[HasIJMPCALL]>;
let isIndirectBranch = 1,
Uses = [R31R30] in def EIJMP
: F16<0b1001010000011001, (outs), (ins), "eijmp", []>,
Requires<[HasEIJMPCALL]>;
def JMPk : F32BRk<0b110, (outs),
(ins call_target
: $k),
"jmp\t$k", []>,
Requires<[HasJMPCALL]>;
}
//===----------------------------------------------------------------------===//
// Call instructions
//===----------------------------------------------------------------------===//
let isCall = 1 in {
// SP is marked as a use to prevent stack-pointer assignments that appear
// immediately before calls from potentially appearing dead.
let Uses = [SP] in def RCALLk : FBRk<1, (outs), (ins rcalltarget_13:$k),
"rcall\t$k", [(AVRcall imm:$k)]>;
// SP is marked as a use to prevent stack-pointer assignments that appear
// immediately before calls from potentially appearing dead.
let Uses = [SP, R31R30] in def ICALL
: F16<0b1001010100001001, (outs), (ins variable_ops), "icall", []>,
Requires<[HasIJMPCALL]>;
// SP is marked as a use to prevent stack-pointer assignments that appear
// immediately before calls from potentially appearing dead.
let Uses = [SP, R31R30] in def EICALL
: F16<0b1001010100011001, (outs), (ins variable_ops), "eicall", []>,
Requires<[HasEIJMPCALL]>;
// SP is marked as a use to prevent stack-pointer assignments that appear
// immediately before calls from potentially appearing dead.
//
// TODO: the imm field can be either 16 or 22 bits in devices with more
// than 64k of ROM, fix it once we support the largest devices.
let Uses = [SP] in def CALLk : F32BRk<0b111, (outs), (ins call_target:$k),
"call\t$k", [(AVRcall imm:$k)]>,
Requires<[HasJMPCALL]>;
}
//===----------------------------------------------------------------------===//
// Return instructions.
//===----------------------------------------------------------------------===//