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riscv_vector.td
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riscv_vector.td
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//==--- riscv_vector.td - RISC-V V-ext Builtin function list --------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file defines the builtins for RISC-V V-extension. See:
//
// https://github.com/riscv/rvv-intrinsic-doc
//
//===----------------------------------------------------------------------===//
include "riscv_vector_common.td"
//===----------------------------------------------------------------------===//
// Basic classes with automatic codegen.
//===----------------------------------------------------------------------===//
class RVVOutBuiltin<string suffix, string prototype, string type_range>
: RVVBuiltin<suffix, prototype, type_range> {
let IntrinsicTypes = [-1];
}
class RVVOp0Builtin<string suffix, string prototype, string type_range>
: RVVBuiltin<suffix, prototype, type_range> {
let IntrinsicTypes = [0];
}
class RVVOutOp1Builtin<string suffix, string prototype, string type_range>
: RVVBuiltin<suffix, prototype, type_range> {
let IntrinsicTypes = [-1, 1];
}
class RVVOutOp0Op1Builtin<string suffix, string prototype, string type_range>
: RVVBuiltin<suffix, prototype, type_range> {
let IntrinsicTypes = [-1, 0, 1];
}
multiclass RVVBuiltinSet<string intrinsic_name, string type_range,
list<list<string>> suffixes_prototypes,
list<int> intrinsic_types> {
let IRName = intrinsic_name, MaskedIRName = intrinsic_name # "_mask",
IntrinsicTypes = intrinsic_types in {
foreach s_p = suffixes_prototypes in {
let Name = NAME # "_" # s_p[0] in {
defvar suffix = s_p[1];
defvar prototype = s_p[2];
def : RVVBuiltin<suffix, prototype, type_range>;
}
}
}
}
// IntrinsicTypes is output, op0, op1 [-1, 0, 1]
multiclass RVVOutOp0Op1BuiltinSet<string intrinsic_name, string type_range,
list<list<string>> suffixes_prototypes>
: RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes,
[-1, 0, 1]>;
multiclass RVVOutBuiltinSet<string intrinsic_name, string type_range,
list<list<string>> suffixes_prototypes>
: RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [-1]>;
multiclass RVVOp0BuiltinSet<string intrinsic_name, string type_range,
list<list<string>> suffixes_prototypes>
: RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [0]>;
// IntrinsicTypes is output, op1 [-1, 0]
multiclass RVVOutOp0BuiltinSet<string intrinsic_name, string type_range,
list<list<string>> suffixes_prototypes>
: RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [-1, 0]>;
// IntrinsicTypes is output, op1 [-1, 1]
multiclass RVVOutOp1BuiltinSet<string intrinsic_name, string type_range,
list<list<string>> suffixes_prototypes>
: RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [-1, 1]>;
multiclass RVVOp0Op1BuiltinSet<string intrinsic_name, string type_range,
list<list<string>> suffixes_prototypes>
: RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [0, 1]>;
multiclass RVVOutOp1Op2BuiltinSet<string intrinsic_name, string type_range,
list<list<string>> suffixes_prototypes>
: RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [-1, 1, 2]>;
multiclass RVVSignedBinBuiltinSet
: RVVOutOp1BuiltinSet<NAME, "csil",
[["vv", "v", "vvv"],
["vx", "v", "vve"]]>;
multiclass RVVUnsignedBinBuiltinSet
: RVVOutOp1BuiltinSet<NAME, "csil",
[["vv", "Uv", "UvUvUv"],
["vx", "Uv", "UvUvUe"]]>;
multiclass RVVIntBinBuiltinSet
: RVVSignedBinBuiltinSet,
RVVUnsignedBinBuiltinSet;
multiclass RVVSlideOneBuiltinSet
: RVVOutOp1BuiltinSet<NAME, "csil",
[["vx", "v", "vve"],
["vx", "Uv", "UvUve"]]>;
multiclass RVVSignedShiftBuiltinSet
: RVVOutOp1BuiltinSet<NAME, "csil",
[["vv", "v", "vvUv"],
["vx", "v", "vvz"]]>;
multiclass RVVUnsignedShiftBuiltinSet
: RVVOutOp1BuiltinSet<NAME, "csil",
[["vv", "Uv", "UvUvUv"],
["vx", "Uv", "UvUvz"]]>;
multiclass RVVShiftBuiltinSet
: RVVSignedShiftBuiltinSet,
RVVUnsignedShiftBuiltinSet;
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
multiclass RVVSignedNShiftBuiltinSet
: RVVOutOp0Op1BuiltinSet<NAME, "csil",
[["wv", "v", "vwUv"],
["wx", "v", "vwz"]]>;
multiclass RVVUnsignedNShiftBuiltinSet
: RVVOutOp0Op1BuiltinSet<NAME, "csil",
[["wv", "Uv", "UvUwUv"],
["wx", "Uv", "UvUwz"]]>;
}
multiclass RVVCarryinBuiltinSet
: RVVOutOp1BuiltinSet<NAME, "csil",
[["vvm", "v", "vvvm"],
["vxm", "v", "vvem"],
["vvm", "Uv", "UvUvUvm"],
["vxm", "Uv", "UvUvUem"]]>;
multiclass RVVCarryOutInBuiltinSet<string intrinsic_name>
: RVVOp0Op1BuiltinSet<intrinsic_name, "csil",
[["vvm", "vm", "mvvm"],
["vxm", "vm", "mvem"],
["vvm", "Uvm", "mUvUvm"],
["vxm", "Uvm", "mUvUem"]]>;
multiclass RVVSignedMaskOutBuiltinSet
: RVVOp0Op1BuiltinSet<NAME, "csil",
[["vv", "vm", "mvv"],
["vx", "vm", "mve"]]>;
multiclass RVVUnsignedMaskOutBuiltinSet
: RVVOp0Op1BuiltinSet<NAME, "csil",
[["vv", "Uvm", "mUvUv"],
["vx", "Uvm", "mUvUe"]]>;
multiclass RVVIntMaskOutBuiltinSet
: RVVSignedMaskOutBuiltinSet,
RVVUnsignedMaskOutBuiltinSet;
class RVVIntExt<string intrinsic_name, string suffix, string prototype,
string type_range>
: RVVBuiltin<suffix, prototype, type_range> {
let IRName = intrinsic_name;
let MaskedIRName = intrinsic_name # "_mask";
let OverloadedName = NAME;
let IntrinsicTypes = [-1, 0];
}
let HasMaskedOffOperand = false in {
multiclass RVVIntTerBuiltinSet {
defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
[["vv", "v", "vvvv"],
["vx", "v", "vvev"],
["vv", "Uv", "UvUvUvUv"],
["vx", "Uv", "UvUvUeUv"]]>;
}
multiclass RVVFloatingTerBuiltinSet {
defm "" : RVVOutOp1BuiltinSet<NAME, "xfd",
[["vv", "v", "vvvv"],
["vf", "v", "vvev"]]>;
}
}
let HasMaskedOffOperand = false, Log2LMUL = [-2, -1, 0, 1, 2] in {
multiclass RVVFloatingWidenTerBuiltinSet {
defm "" : RVVOutOp1Op2BuiltinSet<NAME, "xf",
[["vv", "w", "wwvv"],
["vf", "w", "wwev"]]>;
}
}
multiclass RVVFloatingBinBuiltinSet
: RVVOutOp1BuiltinSet<NAME, "xfd",
[["vv", "v", "vvv"],
["vf", "v", "vve"]]>;
multiclass RVVFloatingBinVFBuiltinSet
: RVVOutOp1BuiltinSet<NAME, "xfd",
[["vf", "v", "vve"]]>;
multiclass RVVFloatingMaskOutBuiltinSet
: RVVOp0Op1BuiltinSet<NAME, "xfd",
[["vv", "vm", "mvv"],
["vf", "vm", "mve"]]>;
multiclass RVVFloatingMaskOutVFBuiltinSet
: RVVOp0Op1BuiltinSet<NAME, "fd",
[["vf", "vm", "mve"]]>;
class RVVMaskBinBuiltin : RVVOutBuiltin<"m", "mmm", "c"> {
let Name = NAME # "_mm";
let HasMasked = false;
}
class RVVMaskUnaryBuiltin : RVVOutBuiltin<"m", "mm", "c"> {
let Name = NAME # "_m";
}
class RVVMaskNullaryBuiltin : RVVOutBuiltin<"m", "m", "c"> {
let Name = NAME # "_m";
let HasMasked = false;
let SupportOverloading = false;
}
class RVVMaskOp0Builtin<string prototype> : RVVOp0Builtin<"m", prototype, "c"> {
let Name = NAME # "_m";
let HasMaskedOffOperand = false;
}
let UnMaskedPolicyScheme = HasPolicyOperand,
HasMaskedOffOperand = false in {
multiclass RVVSlideUpBuiltinSet {
defm "" : RVVOutBuiltinSet<NAME, "csilxfd",
[["vx","v", "vvvz"]]>;
defm "" : RVVOutBuiltinSet<NAME, "csil",
[["vx","Uv", "UvUvUvz"]]>;
}
}
let UnMaskedPolicyScheme = HasPassthruOperand,
ManualCodegen = [{
if (IsMasked) {
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
if ((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA))
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
} else {
if (PolicyAttrs & RVV_VTA)
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
}
Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
IntrinsicTypes = {ResultType, Ops.back()->getType()};
}] in {
multiclass RVVSlideDownBuiltinSet {
defm "" : RVVOutBuiltinSet<NAME, "csilxfd",
[["vx","v", "vvz"]]>;
defm "" : RVVOutBuiltinSet<NAME, "csil",
[["vx","Uv", "UvUvz"]]>;
}
}
class RVVFloatingUnaryBuiltin<string builtin_suffix, string ir_suffix,
string prototype>
: RVVOutBuiltin<ir_suffix, prototype, "xfd"> {
let Name = NAME # "_" # builtin_suffix;
}
class RVVFloatingUnaryVVBuiltin : RVVFloatingUnaryBuiltin<"v", "v", "vv">;
class RVVConvBuiltin<string suffix, string prototype, string type_range,
string overloaded_name>
: RVVBuiltin<suffix, prototype, type_range> {
let IntrinsicTypes = [-1, 0];
let OverloadedName = overloaded_name;
}
class RVVConvToSignedBuiltin<string overloaded_name>
: RVVConvBuiltin<"Iv", "Ivv", "xfd", overloaded_name>;
class RVVConvToUnsignedBuiltin<string overloaded_name>
: RVVConvBuiltin<"Uv", "Uvv", "xfd", overloaded_name>;
class RVVConvToWidenSignedBuiltin<string overloaded_name>
: RVVConvBuiltin<"Iw", "Iwv", "xf", overloaded_name>;
class RVVConvToWidenUnsignedBuiltin<string overloaded_name>
: RVVConvBuiltin<"Uw", "Uwv", "xf", overloaded_name>;
class RVVConvToNarrowingSignedBuiltin<string overloaded_name>
: RVVConvBuiltin<"Iv", "IvFw", "csi", overloaded_name>;
class RVVConvToNarrowingUnsignedBuiltin<string overloaded_name>
: RVVConvBuiltin<"Uv", "UvFw", "csi", overloaded_name>;
let HasMaskedOffOperand = true in {
multiclass RVVSignedReductionBuiltin {
defm "" : RVVOutOp0BuiltinSet<NAME, "csil",
[["vs", "vSv", "SvvSv"]]>;
}
multiclass RVVUnsignedReductionBuiltin {
defm "" : RVVOutOp0BuiltinSet<NAME, "csil",
[["vs", "UvUSv", "USvUvUSv"]]>;
}
multiclass RVVFloatingReductionBuiltin {
defm "" : RVVOutOp0BuiltinSet<NAME, "xfd",
[["vs", "vSv", "SvvSv"]]>;
}
multiclass RVVFloatingWidenReductionBuiltin {
defm "" : RVVOutOp0BuiltinSet<NAME, "xf",
[["vs", "vSw", "SwvSw"]]>;
}
}
multiclass RVVIntReductionBuiltinSet
: RVVSignedReductionBuiltin,
RVVUnsignedReductionBuiltin;
// For widen operation which has different mangling name.
multiclass RVVWidenBuiltinSet<string intrinsic_name, string type_range,
list<list<string>> suffixes_prototypes> {
let Log2LMUL = [-3, -2, -1, 0, 1, 2],
IRName = intrinsic_name, MaskedIRName = intrinsic_name # "_mask" in {
foreach s_p = suffixes_prototypes in {
let Name = NAME # "_" # s_p[0],
OverloadedName = NAME # "_" # s_p[0] in {
defvar suffix = s_p[1];
defvar prototype = s_p[2];
def : RVVOutOp0Op1Builtin<suffix, prototype, type_range>;
}
}
}
}
// For widen operation with widen operand which has different mangling name.
multiclass RVVWidenWOp0BuiltinSet<string intrinsic_name, string type_range,
list<list<string>> suffixes_prototypes> {
let Log2LMUL = [-3, -2, -1, 0, 1, 2],
IRName = intrinsic_name, MaskedIRName = intrinsic_name # "_mask" in {
foreach s_p = suffixes_prototypes in {
let Name = NAME # "_" # s_p[0],
OverloadedName = NAME # "_" # s_p[0] in {
defvar suffix = s_p[1];
defvar prototype = s_p[2];
def : RVVOutOp1Builtin<suffix, prototype, type_range>;
}
}
}
}
multiclass RVVSignedWidenBinBuiltinSet
: RVVWidenBuiltinSet<NAME, "csi",
[["vv", "w", "wvv"],
["vx", "w", "wve"]]>;
multiclass RVVSignedWidenOp0BinBuiltinSet
: RVVWidenWOp0BuiltinSet<NAME # "_w", "csi",
[["wv", "w", "wwv"],
["wx", "w", "wwe"]]>;
multiclass RVVUnsignedWidenBinBuiltinSet
: RVVWidenBuiltinSet<NAME, "csi",
[["vv", "Uw", "UwUvUv"],
["vx", "Uw", "UwUvUe"]]>;
multiclass RVVUnsignedWidenOp0BinBuiltinSet
: RVVWidenWOp0BuiltinSet<NAME # "_w", "csi",
[["wv", "Uw", "UwUwUv"],
["wx", "Uw", "UwUwUe"]]>;
multiclass RVVFloatingWidenBinBuiltinSet
: RVVWidenBuiltinSet<NAME, "xf",
[["vv", "w", "wvv"],
["vf", "w", "wve"]]>;
multiclass RVVFloatingWidenOp0BinBuiltinSet
: RVVWidenWOp0BuiltinSet<NAME # "_w", "xf",
[["wv", "w", "wwv"],
["wf", "w", "wwe"]]>;
defvar TypeList = ["c","s","i","l","x","f","d"];
defvar EEWList = [["8", "(Log2EEW:3)"],
["16", "(Log2EEW:4)"],
["32", "(Log2EEW:5)"],
["64", "(Log2EEW:6)"]];
class IsFloat<string type> {
bit val = !or(!eq(type, "x"), !eq(type, "f"), !eq(type, "d"));
}
let SupportOverloading = false,
MaskedPolicyScheme = NonePolicy in {
class RVVVLEMaskBuiltin : RVVOutBuiltin<"m", "mPCUe", "c"> {
let Name = "vlm_v";
let IRName = "vlm";
let HasMasked = false;
}
}
let SupportOverloading = false,
UnMaskedPolicyScheme = HasPassthruOperand in {
multiclass RVVVLEBuiltin<list<string> types> {
let Name = NAME # "_v",
IRName = "vle",
MaskedIRName ="vle_mask" in {
foreach type = types in {
def : RVVOutBuiltin<"v", "vPCe", type>;
if !not(IsFloat<type>.val) then {
def : RVVOutBuiltin<"Uv", "UvPCUe", type>;
}
}
}
}
}
multiclass RVVVLEFFBuiltin<list<string> types> {
let Name = NAME # "_v",
IRName = "vleff",
MaskedIRName = "vleff_mask",
SupportOverloading = false,
UnMaskedPolicyScheme = HasPassthruOperand,
ManualCodegen = [{
{
if (IsMasked) {
// Move mask to right before vl.
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
if ((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA))
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
IntrinsicTypes = {ResultType, Ops[4]->getType()};
} else {
if (PolicyAttrs & RVV_VTA)
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
IntrinsicTypes = {ResultType, Ops[3]->getType()};
}
Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
Value *NewVL = Ops[2];
Ops.erase(Ops.begin() + 2);
llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0});
// Store new_vl.
clang::CharUnits Align;
if (IsMasked)
Align = CGM.getNaturalPointeeTypeAlignment(E->getArg(E->getNumArgs()-2)->getType());
else
Align = CGM.getNaturalPointeeTypeAlignment(E->getArg(1)->getType());
llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {1});
Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
return V;
}
}] in {
foreach type = types in {
def : RVVBuiltin<"v", "vPCePz", type>;
// Skip floating types for unsigned versions.
if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "UvPCUePz", type>;
}
}
}
}
multiclass RVVVLSEBuiltin<list<string> types> {
let Name = NAME # "_v",
IRName = "vlse",
MaskedIRName ="vlse_mask",
SupportOverloading = false,
UnMaskedPolicyScheme = HasPassthruOperand in {
foreach type = types in {
def : RVVOutBuiltin<"v", "vPCet", type>;
if !not(IsFloat<type>.val) then {
def : RVVOutBuiltin<"Uv", "UvPCUet", type>;
}
}
}
}
multiclass RVVIndexedLoad<string op> {
let UnMaskedPolicyScheme = HasPassthruOperand in {
foreach type = TypeList in {
foreach eew_list = EEWList[0-2] in {
defvar eew = eew_list[0];
defvar eew_type = eew_list[1];
let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask" in {
def: RVVOutOp1Builtin<"v", "vPCe" # eew_type # "Uv", type>;
if !not(IsFloat<type>.val) then {
def: RVVOutOp1Builtin<"Uv", "UvPCUe" # eew_type # "Uv", type>;
}
}
}
defvar eew64 = "64";
defvar eew64_type = "(Log2EEW:6)";
let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op # "_mask",
RequiredFeatures = ["RV64"] in {
def: RVVOutOp1Builtin<"v", "vPCe" # eew64_type # "Uv", type>;
if !not(IsFloat<type>.val) then {
def: RVVOutOp1Builtin<"Uv", "UvPCUe" # eew64_type # "Uv", type>;
}
}
}
}
}
let HasMaskedOffOperand = false,
MaskedPolicyScheme = NonePolicy,
ManualCodegen = [{
if (IsMasked) {
// Builtin: (mask, ptr, value, vl). Intrinsic: (value, ptr, mask, vl)
std::swap(Ops[0], Ops[2]);
} else {
// Builtin: (ptr, value, vl). Intrinsic: (value, ptr, vl)
std::swap(Ops[0], Ops[1]);
}
Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo());
if (IsMasked)
IntrinsicTypes = {Ops[0]->getType(), Ops[3]->getType()};
else
IntrinsicTypes = {Ops[0]->getType(), Ops[2]->getType()};
}] in {
class RVVVSEMaskBuiltin : RVVBuiltin<"m", "0PUem", "c"> {
let Name = "vsm_v";
let IRName = "vsm";
let HasMasked = false;
}
multiclass RVVVSEBuiltin<list<string> types> {
let Name = NAME # "_v",
IRName = "vse",
MaskedIRName = "vse_mask" in {
foreach type = types in {
def : RVVBuiltin<"v", "0Pev", type>;
if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "0PUeUv", type>;
}
}
}
}
}
multiclass RVVVSSEBuiltin<list<string> types> {
let Name = NAME # "_v",
IRName = "vsse",
MaskedIRName = "vsse_mask",
HasMaskedOffOperand = false,
MaskedPolicyScheme = NonePolicy,
ManualCodegen = [{
if (IsMasked) {
// Builtin: (mask, ptr, stride, value, vl). Intrinsic: (value, ptr, stride, mask, vl)
std::swap(Ops[0], Ops[3]);
} else {
// Builtin: (ptr, stride, value, vl). Intrinsic: (value, ptr, stride, vl)
std::rotate(Ops.begin(), Ops.begin() + 2, Ops.begin() + 3);
}
Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo());
if (IsMasked)
IntrinsicTypes = {Ops[0]->getType(), Ops[4]->getType()};
else
IntrinsicTypes = {Ops[0]->getType(), Ops[3]->getType()};
}] in {
foreach type = types in {
def : RVVBuiltin<"v", "0Petv", type>;
if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "0PUetUv", type>;
}
}
}
}
multiclass RVVIndexedStore<string op> {
let HasMaskedOffOperand = false,
MaskedPolicyScheme = NonePolicy,
ManualCodegen = [{
if (IsMasked) {
// Builtin: (mask, ptr, index, value, vl). Intrinsic: (value, ptr, index, mask, vl)
std::swap(Ops[0], Ops[3]);
} else {
// Builtin: (ptr, index, value, vl). Intrinsic: (value, ptr, index, vl)
std::rotate(Ops.begin(), Ops.begin() + 2, Ops.begin() + 3);
}
Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo());
if (IsMasked)
IntrinsicTypes = {Ops[0]->getType(), Ops[2]->getType(), Ops[4]->getType()};
else
IntrinsicTypes = {Ops[0]->getType(), Ops[2]->getType(), Ops[3]->getType()};
}] in {
foreach type = TypeList in {
foreach eew_list = EEWList[0-2] in {
defvar eew = eew_list[0];
defvar eew_type = eew_list[1];
let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask" in {
def : RVVBuiltin<"v", "0Pe" # eew_type # "Uvv", type>;
if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "0PUe" # eew_type # "UvUv", type>;
}
}
}
defvar eew64 = "64";
defvar eew64_type = "(Log2EEW:6)";
let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op # "_mask",
RequiredFeatures = ["RV64"] in {
def : RVVBuiltin<"v", "0Pe" # eew64_type # "Uvv", type>;
if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "0PUe" # eew64_type # "UvUv", type>;
}
}
}
}
}
defvar NFList = [2, 3, 4, 5, 6, 7, 8];
/*
A segment load builtin has different variants.
Therefore a segment unit-stride load builtin can have 4 variants,
1. When unmasked and the policies are all specified as agnostic:
(Address0, ..., Address{NF - 1}, Ptr, VL)
2. When masked and the policies are all specified as agnostic:
(Address0, ..., Address{NF - 1}, Mask, Ptr, VL)
3. When unmasked and one of the policies is specified as undisturbed:
(Address0, ..., Address{NF - 1}, Maskedoff0, ..., Maskedoff{NF - 1},
Ptr, VL)
4. When masked and one of the policies is specified as undisturbed:
(Address0, ..., Address{NF - 1}, Mask, Maskedoff0, ..., Maskedoff{NF - 1},
Ptr, VL)
Other variants of segment load builtin share the same structure, but they
have their own extra parameter.
The segment unit-stride fault-only-first load builtin has a 'NewVL'
operand after the 'Ptr' operand.
1. When unmasked and the policies are all specified as agnostic:
(Address0, ..., Address{NF - 1}, Ptr, NewVL, VL)
2. When masked and the policies are all specified as agnostic:
(Address0, ..., Address{NF - 1}, Mask, Ptr, NewVL, VL)
3. When unmasked and one of the policies is specified as undisturbed:
(Address0, ..., Address{NF - 1}, Maskedoff0, ..., Maskedoff{NF - 1},
Ptr, NewVL, VL)
4. When masked and one of the policies is specified as undisturbed:
(Address0, ..., Address{NF - 1}, Mask, Maskedoff0, ..., Maskedoff{NF - 1},
Ptr, NewVL, VL)
The segment strided load builtin has a 'Stride' operand after the 'Ptr'
operand.
1. When unmasked and the policies are all specified as agnostic:
(Address0, ..., Address{NF - 1}, Ptr, Stride, VL)
2. When masked and the policies are all specified as agnostic:
(Address0, ..., Address{NF - 1}, Mask, Ptr, Stride, VL)
3. When unmasked and one of the policies is specified as undisturbed:
(Address0, ..., Address{NF - 1}, Maskedoff0, ..., Maskedoff{NF - 1},
Ptr, Stride, VL)
4. When masked and one of the policies is specified as undisturbed:
(Address0, ..., Address{NF - 1}, Mask, Maskedoff0, ..., Maskedoff{NF - 1},
Ptr, Stride, VL)
The segment indexed load builtin has a 'Idx' operand after the 'Ptr' operand.
1. When unmasked and the policies are all specified as agnostic:
(Address0, ..., Address{NF - 1}, Ptr, Idx, VL)
2. When masked and the policies are all specified as agnostic:
(Address0, ..., Address{NF - 1}, Mask, Ptr, Idx, VL)
3. When unmasked and one of the policies is specified as undisturbed:
(Address0, ..., Address{NF - 1}, Maskedoff0, ..., Maskedoff{NF - 1},
Ptr, Idx, VL)
4. When masked and one of the policies is specified as undisturbed:
(Address0, ..., Address{NF - 1}, Mask, Maskedoff0, ..., Maskedoff{NF - 1},
Ptr, Idx, VL)
Segment load intrinsics has different variants similar to their builtins.
Segment unit-stride load intrinsic,
Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Mask, VL, Policy)
Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, VL)
Segment unit-stride fault-only-first load intrinsic,
Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Mask, VL, Policy)
Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, VL)
Segment strided load intrinsic,
Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Stride, Mask, VL, Policy)
Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, Stride, VL)
Segment indexed load intrinsic,
Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Index, Mask, VL, Policy)
Unmasked: (Vector0, ..., Vector{NF - 1}, Ptr, Index, VL)
The Vector(s) is poison when the policy behavior allows us to not care
about any masked-off elements.
*/
class PVString<int nf, bit signed> {
string S =
!cond(!eq(nf, 2): !if(signed, "PvPv", "PUvPUv"),
!eq(nf, 3): !if(signed, "PvPvPv", "PUvPUvPUv"),
!eq(nf, 4): !if(signed, "PvPvPvPv", "PUvPUvPUvPUv"),
!eq(nf, 5): !if(signed, "PvPvPvPvPv", "PUvPUvPUvPUvPUv"),
!eq(nf, 6): !if(signed, "PvPvPvPvPvPv", "PUvPUvPUvPUvPUvPUv"),
!eq(nf, 7): !if(signed, "PvPvPvPvPvPvPv", "PUvPUvPUvPUvPUvPUvPUv"),
!eq(nf, 8): !if(signed, "PvPvPvPvPvPvPvPv", "PUvPUvPUvPUvPUvPUvPUvPUv"));
}
multiclass RVVUnitStridedSegLoad<string op> {
foreach type = TypeList in {
defvar eew = !cond(!eq(type, "c") : "8",
!eq(type, "s") : "16",
!eq(type, "i") : "32",
!eq(type, "l") : "64",
!eq(type, "x") : "16",
!eq(type, "f") : "32",
!eq(type, "d") : "64");
foreach nf = NFList in {
let Name = op # nf # "e" # eew # "_v",
IRName = op # nf,
MaskedIRName = op # nf # "_mask",
NF = nf,
ManualCodegen = [{
{
ResultType = ConvertType(E->getArg(0)->getType()->getPointeeType());
IntrinsicTypes = {ResultType, Ops.back()->getType()};
SmallVector<llvm::Value*, 12> Operands;
// Please refer to comment under 'defvar NFList' in this file
if ((IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
(!IsMasked && PolicyAttrs & RVV_VTA))
Operands.append(NF, llvm::PoisonValue::get(ResultType));
else {
if (IsMasked)
Operands.append(Ops.begin() + NF + 1, Ops.begin() + 2 * NF + 1);
else // Unmasked
Operands.append(Ops.begin() + NF, Ops.begin() + 2 * NF);
}
unsigned PtrOperandIdx = IsMasked ?
((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ? NF + 1 : 2 * NF + 1 :
(PolicyAttrs & RVV_VTA) ? NF : 2 * NF;
Value *PtrOperand = Ops[PtrOperandIdx];
Value *VLOperand = Ops[PtrOperandIdx + 1];
Operands.push_back(PtrOperand);
if (IsMasked)
Operands.push_back(Ops[NF]);
Operands.push_back(VLOperand);
if (IsMasked)
Operands.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
llvm::Value *LoadValue = Builder.CreateCall(F, Operands, "");
clang::CharUnits Align =
CGM.getNaturalPointeeTypeAlignment(E->getArg(0)->getType());
llvm::Value *V;
for (unsigned I = 0; I < NF; ++I) {
llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {I});
V = Builder.CreateStore(Val, Address(Ops[I], Val->getType(), Align));
}
return V;
}
}] in {
defvar PV = PVString<nf, /*signed=*/true>.S;
defvar PUV = PVString<nf, /*signed=*/false>.S;
def : RVVBuiltin<"v", "0" # PV # "PCe", type>;
if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "0" # PUV # "PCUe", type>;
}
}
}
}
}
multiclass RVVUnitStridedSegLoadFF<string op> {
foreach type = TypeList in {
defvar eew = !cond(!eq(type, "c") : "8",
!eq(type, "s") : "16",
!eq(type, "i") : "32",
!eq(type, "l") : "64",
!eq(type, "x") : "16",
!eq(type, "f") : "32",
!eq(type, "d") : "64");
foreach nf = NFList in {
let Name = op # nf # "e" # eew # "ff_v",
IRName = op # nf # "ff",
MaskedIRName = op # nf # "ff_mask",
NF = nf,
ManualCodegen = [{
{
ResultType = ConvertType(E->getArg(0)->getType()->getPointeeType());
IntrinsicTypes = {ResultType, Ops.back()->getType()};
SmallVector<llvm::Value*, 12> Operands;
// Please refer to comment under 'defvar NFList' in this file
if ((IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
(!IsMasked && PolicyAttrs & RVV_VTA))
Operands.append(NF, llvm::PoisonValue::get(ResultType));
else {
if (IsMasked)
Operands.append(Ops.begin() + NF + 1, Ops.begin() + 2 * NF + 1);
else // Unmasked
Operands.append(Ops.begin() + NF, Ops.begin() + 2 * NF);
}
unsigned PtrOperandIdx = IsMasked ?
((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ? NF + 1 : 2 * NF + 1 :
(PolicyAttrs & RVV_VTA) ? NF : 2 * NF;
Value *PtrOperand = Ops[PtrOperandIdx];
Value *NewVLOperand = Ops[PtrOperandIdx + 1];
Value *VLOperand = Ops[PtrOperandIdx + 2];
Operands.push_back(PtrOperand);
if (IsMasked)
Operands.push_back(Ops[NF]);
Operands.push_back(VLOperand);
if (IsMasked)
Operands.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
llvm::Value *LoadValue = Builder.CreateCall(F, Operands, "");
clang::CharUnits Align =
CGM.getNaturalPointeeTypeAlignment(E->getArg(0)->getType());
for (unsigned I = 0; I < NF; ++I) {
llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {I});
Builder.CreateStore(Val, Address(Ops[I], Val->getType(), Align));
}
// Store new_vl.
llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {NF});
return Builder.CreateStore(Val, Address(NewVLOperand, Val->getType(), Align));
}
}] in {
defvar PV = PVString<nf, /*signed=*/true>.S;
defvar PUV = PVString<nf, /*signed=*/false>.S;
def : RVVBuiltin<"v", "0" # PV # "PCe" # "Pz", type>;
if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "0" # PUV # "PCUe" # "Pz", type>;
}
}
}
}
}
multiclass RVVStridedSegLoad<string op> {
foreach type = TypeList in {
defvar eew = !cond(!eq(type, "c") : "8",
!eq(type, "s") : "16",
!eq(type, "i") : "32",
!eq(type, "l") : "64",
!eq(type, "x") : "16",
!eq(type, "f") : "32",
!eq(type, "d") : "64");
foreach nf = NFList in {
let Name = op # nf # "e" # eew # "_v",
IRName = op # nf,
MaskedIRName = op # nf # "_mask",
NF = nf,
ManualCodegen = [{
{
ResultType = ConvertType(E->getArg(0)->getType()->getPointeeType());
IntrinsicTypes = {ResultType, Ops.back()->getType()};
SmallVector<llvm::Value*, 12> Operands;
// Please refer to comment under 'defvar NFList' in this file
if ((IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
(!IsMasked && PolicyAttrs & RVV_VTA))
Operands.append(NF, llvm::PoisonValue::get(ResultType));
else {
if (IsMasked)
Operands.append(Ops.begin() + NF + 1, Ops.begin() + 2 * NF + 1);
else // Unmasked
Operands.append(Ops.begin() + NF, Ops.begin() + 2 * NF);
}
unsigned PtrOperandIdx = IsMasked ?
((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ? NF + 1 : 2 * NF + 1 :
(PolicyAttrs & RVV_VTA) ? NF : 2 * NF;
Value *PtrOperand = Ops[PtrOperandIdx];
Value *StrideOperand = Ops[PtrOperandIdx + 1];
Value *VLOperand = Ops[PtrOperandIdx + 2];
Operands.push_back(PtrOperand);
Operands.push_back(StrideOperand);
if (IsMasked)
Operands.push_back(Ops[NF]);
Operands.push_back(VLOperand);
if (IsMasked)
Operands.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
llvm::Value *LoadValue = Builder.CreateCall(F, Operands, "");
clang::CharUnits Align =
CGM.getNaturalPointeeTypeAlignment(E->getArg(0)->getType());
llvm::Value *V;
for (unsigned I = 0; I < NF; ++I) {
llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {I});
V = Builder.CreateStore(Val, Address(Ops[I], Val->getType(), Align));
}
return V;
}
}] in {
defvar PV = PVString<nf, /*signed=*/true>.S;
defvar PUV = PVString<nf, /*signed=*/false>.S;
def : RVVBuiltin<"v", "0" # PV # "PCe" # "t", type>;
if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "0" # PUV # "PCUe" # "t", type>;
}
}
}
}
}
multiclass RVVIndexedSegLoad<string op> {
foreach type = TypeList in {
foreach eew_info = EEWList in {
defvar eew = eew_info[0];
defvar eew_type = eew_info[1];
foreach nf = NFList in {
let Name = op # nf # "ei" # eew # "_v",
IRName = op # nf,
MaskedIRName = op # nf # "_mask",
NF = nf,
ManualCodegen = [{
{
ResultType = ConvertType(E->getArg(0)->getType()->getPointeeType());
SmallVector<llvm::Value*, 12> Operands;
// Please refer to comment under 'defvar NFList' in this file
if ((IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
(!IsMasked && PolicyAttrs & RVV_VTA))
Operands.append(NF, llvm::PoisonValue::get(ResultType));
else {
if (IsMasked)
Operands.append(Ops.begin() + NF + 1, Ops.begin() + 2 * NF + 1);
else // Unmasked
Operands.append(Ops.begin() + NF, Ops.begin() + 2 * NF);
}
unsigned PtrOperandIdx = IsMasked ?
((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ? NF + 1 : 2 * NF + 1 :
(PolicyAttrs & RVV_VTA) ? NF : 2 * NF;
Value *PtrOperand = Ops[PtrOperandIdx];
Value *IndexOperand = Ops[PtrOperandIdx + 1];
Value *VLOperand = Ops[PtrOperandIdx + 2];
Operands.push_back(PtrOperand);
Operands.push_back(IndexOperand);
if (IsMasked)
Operands.push_back(Ops[NF]);
Operands.push_back(VLOperand);
if (IsMasked)
Operands.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
IntrinsicTypes = {ResultType, IndexOperand->getType(), Ops.back()->getType()};
llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
llvm::Value *LoadValue = Builder.CreateCall(F, Operands, "");
clang::CharUnits Align =
CGM.getNaturalPointeeTypeAlignment(E->getArg(0)->getType());
llvm::Value *V;
for (unsigned I = 0; I < NF; ++I) {
llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {I});
V = Builder.CreateStore(Val, Address(Ops[I], Val->getType(), Align));
}
return V;
}
}] in {
defvar PV = PVString<nf, /*signed=*/true>.S;
defvar PUV = PVString<nf, /*signed=*/false>.S;
def : RVVBuiltin<"v", "0" # PV # "PCe" # eew_type # "Uv", type>;
if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "0" # PUV # "PCUe" # eew_type # "Uv", type>;
}
}
}
}
}
}
class VString<int nf, bit signed> {
string S = !cond(!eq(nf, 2): !if(signed, "vv", "UvUv"),
!eq(nf, 3): !if(signed, "vvv", "UvUvUv"),
!eq(nf, 4): !if(signed, "vvvv", "UvUvUvUv"),
!eq(nf, 5): !if(signed, "vvvvv", "UvUvUvUvUv"),
!eq(nf, 6): !if(signed, "vvvvvv", "UvUvUvUvUvUv"),
!eq(nf, 7): !if(signed, "vvvvvvv", "UvUvUvUvUvUvUv"),
!eq(nf, 8): !if(signed, "vvvvvvvv", "UvUvUvUvUvUvUvUv"));
}
multiclass RVVUnitStridedSegStore<string op> {
foreach type = TypeList in {
defvar eew = !cond(!eq(type, "c") : "8",
!eq(type, "s") : "16",
!eq(type, "i") : "32",
!eq(type, "l") : "64",
!eq(type, "x") : "16",
!eq(type, "f") : "32",
!eq(type, "d") : "64");
foreach nf = NFList in {
let Name = op # nf # "e" # eew # "_v",
IRName = op # nf,
MaskedIRName = op # nf # "_mask",
NF = nf,
HasMaskedOffOperand = false,
MaskedPolicyScheme = NonePolicy,
ManualCodegen = [{
{
if (IsMasked) {
// Builtin: (mask, ptr, val0, val1, ..., vl)
// Intrinsic: (val0, val1, ..., ptr, mask, vl)
std::rotate(Ops.begin(), Ops.begin() + 2, Ops.end() - 1);
std::swap(Ops[NF], Ops[NF + 1]);
IntrinsicTypes = {Ops[0]->getType(), Ops[NF + 2]->getType()};
assert(Ops.size() == NF + 3);
} else {
// Builtin: (ptr, val0, val1, ..., vl)
// Intrinsic: (val0, val1, ..., ptr, vl)
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
IntrinsicTypes = {Ops[0]->getType(), Ops[NF + 1]->getType()};
assert(Ops.size() == NF + 2);
}
}