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AVRInstrInfo.td
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AVRInstrInfo.td
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//===-- AVRInstrInfo.td - AVR Instruction defs -------------*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file describes the AVR instructions in TableGen format.
//
//===----------------------------------------------------------------------===//
include "AVRInstrFormats.td"
//===----------------------------------------------------------------------===//
// AVR Type Profiles
//===----------------------------------------------------------------------===//
def SDT_AVRCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
def SDT_AVRCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
def SDT_AVRCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
def SDT_AVRWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
def SDT_AVRBrcond : SDTypeProfile<0, 2,
[SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>;
def SDT_AVRCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
def SDT_AVRTst : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
def SDT_AVRSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
//===----------------------------------------------------------------------===//
// AVR Specific Node Definitions
//===----------------------------------------------------------------------===//
def AVRretflag : SDNode<"AVRISD::RET_FLAG", SDTNone,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
def AVRretiflag : SDNode<"AVRISD::RETI_FLAG", SDTNone,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
def AVRcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AVRCallSeqStart,
[SDNPHasChain, SDNPOutGlue]>;
def AVRcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AVRCallSeqEnd,
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
def AVRcall : SDNode<"AVRISD::CALL", SDT_AVRCall,
[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>;
def AVRWrapper : SDNode<"AVRISD::WRAPPER", SDT_AVRWrapper>;
def AVRbrcond : SDNode<"AVRISD::BRCOND", SDT_AVRBrcond,
[SDNPHasChain, SDNPInGlue]>;
def AVRcmp : SDNode<"AVRISD::CMP", SDT_AVRCmp, [SDNPOutGlue]>;
def AVRcmpc : SDNode<"AVRISD::CMPC", SDT_AVRCmp, [SDNPInGlue, SDNPOutGlue]>;
def AVRtst : SDNode<"AVRISD::TST", SDT_AVRTst, [SDNPOutGlue]>;
def AVRselectcc: SDNode<"AVRISD::SELECT_CC", SDT_AVRSelectCC, [SDNPInGlue]>;
// Shift nodes.
def AVRlsl : SDNode<"AVRISD::LSL", SDTIntUnaryOp>;
def AVRlsl4 : SDNode<"AVRISD::LSL4", SDTIntUnaryOp>;
def AVRlsl8 : SDNode<"AVRISD::LSL8", SDTIntUnaryOp>;
def AVRlsl12 : SDNode<"AVRISD::LSL12", SDTIntUnaryOp>;
def AVRlsr : SDNode<"AVRISD::LSR", SDTIntUnaryOp>;
def AVRlsr4 : SDNode<"AVRISD::LSR4", SDTIntUnaryOp>;
def AVRlsr8 : SDNode<"AVRISD::LSR8", SDTIntUnaryOp>;
def AVRlsr12 : SDNode<"AVRISD::LSR12", SDTIntUnaryOp>;
def AVRrol : SDNode<"AVRISD::ROL", SDTIntUnaryOp>;
def AVRror : SDNode<"AVRISD::ROR", SDTIntUnaryOp>;
def AVRasr : SDNode<"AVRISD::ASR", SDTIntUnaryOp>;
def AVRasr8 : SDNode<"AVRISD::ASR8", SDTIntUnaryOp>;
def AVRlsl7 : SDNode<"AVRISD::LSL7", SDTIntUnaryOp>;
def AVRlsr7 : SDNode<"AVRISD::LSR7", SDTIntUnaryOp>;
def AVRasr7 : SDNode<"AVRISD::ASR7", SDTIntUnaryOp>;
// Pseudo shift nodes for non-constant shift amounts.
def AVRlslLoop : SDNode<"AVRISD::LSLLOOP", SDTIntShiftOp>;
def AVRlsrLoop : SDNode<"AVRISD::LSRLOOP", SDTIntShiftOp>;
def AVRrolLoop : SDNode<"AVRISD::ROLLOOP", SDTIntShiftOp>;
def AVRrorLoop : SDNode<"AVRISD::RORLOOP", SDTIntShiftOp>;
def AVRasrLoop : SDNode<"AVRISD::ASRLOOP", SDTIntShiftOp>;
// SWAP node.
def AVRSwap : SDNode<"AVRISD::SWAP", SDTIntUnaryOp>;
//===----------------------------------------------------------------------===//
// AVR Operands, Complex Patterns and Transformations Definitions.
//===----------------------------------------------------------------------===//
def imm8_neg_XFORM : SDNodeXForm<imm,
[{
return CurDAG->getTargetConstant(-N->getAPIntValue(), SDLoc(N), MVT::i8);
}]>;
def imm16_neg_XFORM : SDNodeXForm<imm,
[{
return CurDAG->getTargetConstant(-N->getAPIntValue(), SDLoc(N), MVT::i16);
}]>;
def imm0_63_neg : PatLeaf<(imm),
[{
int64_t val = -N->getSExtValue();
return val >= 0 && val < 64;
}], imm16_neg_XFORM>;
def uimm6 : PatLeaf<(imm), [{ return isUInt<6>(N->getZExtValue()); }]>;
// imm_com8_XFORM - Return the complement of a imm_com8 value
def imm_com8_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(~((uint8_t)N->getZExtValue()), SDLoc(N),
MVT::i8);
}]>;
// imm_com8 - Match an immediate that is a complement
// of a 8-bit immediate.
// Note: this pattern doesn't require an encoder method and such, as it's
// only used on aliases (Pat<> and InstAlias<>). The actual encoding
// is handled by the destination instructions, which use imm_com8.
def imm_com8_asmoperand : AsmOperandClass { let Name = "ImmCom8"; }
def imm_com8 : Operand<i8> {
let ParserMatchClass = imm_com8_asmoperand;
}
def ioaddr_XFORM : SDNodeXForm<imm,
[{
uint8_t offset = Subtarget->getIORegisterOffset();
return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()) - offset,
SDLoc(N), MVT::i8);
}]>;
def iobitpos8_XFORM : SDNodeXForm<imm,
[{
return CurDAG->getTargetConstant(Log2_32(uint8_t(N->getZExtValue())),
SDLoc(N), MVT::i8);
}]>;
def iobitposn8_XFORM : SDNodeXForm<imm,
[{
return CurDAG->getTargetConstant(Log2_32(uint8_t(~N->getZExtValue())),
SDLoc(N), MVT::i8);
}]>;
def ioaddr8 : PatLeaf<(imm),
[{
uint8_t offset = Subtarget->getIORegisterOffset();
uint64_t val = N->getZExtValue() - offset;
return val < 0x40;
}], ioaddr_XFORM>;
def lowioaddr8 : PatLeaf<(imm),
[{
uint8_t offset = Subtarget->getIORegisterOffset();
uint64_t val = N->getZExtValue() - offset;
return val < 0x20;
}], ioaddr_XFORM>;
def ioaddr16 : PatLeaf<(imm),
[{
uint8_t offset = Subtarget->getIORegisterOffset();
uint64_t val = N->getZExtValue() - offset;
return val < 0x3f;
}], ioaddr_XFORM>;
def iobitpos8 : PatLeaf<(imm),
[{
return isPowerOf2_32(uint8_t(N->getZExtValue()));
}], iobitpos8_XFORM>;
def iobitposn8 : PatLeaf<(imm),
[{
return isPowerOf2_32(uint8_t(~N->getZExtValue()));
}], iobitposn8_XFORM>;
def MemriAsmOperand : AsmOperandClass {
let Name = "Memri";
let ParserMethod = "parseMemriOperand";
}
/// Address operand for `reg+imm` used by STD and LDD.
def memri : Operand<iPTR>
{
let MIOperandInfo = (ops PTRDISPREGS, i16imm);
let PrintMethod = "printMemri";
let EncoderMethod = "encodeMemri";
let ParserMatchClass = MemriAsmOperand;
}
// Address operand for `SP+imm` used by STD{W}SPQRr
def memspi : Operand<iPTR>
{
let MIOperandInfo = (ops GPRSP, i16imm);
}
def relbrtarget_7 : Operand<OtherVT>
{
let PrintMethod = "printPCRelImm";
let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_7_pcrel>";
}
def brtarget_13 : Operand<OtherVT>
{
let PrintMethod = "printPCRelImm";
let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_13_pcrel>";
}
// The target of a 22 or 16-bit call/jmp instruction.
def call_target : Operand<iPTR>
{
let EncoderMethod = "encodeCallTarget";
let DecoderMethod = "decodeCallTarget";
}
// A 16-bit address (which can lead to an R_AVR_16 relocation).
def imm16 : Operand<i16>
{
let EncoderMethod = "encodeImm<AVR::fixup_16, 2>";
}
/// A 6-bit immediate used in the ADIW/SBIW instructions.
def imm_arith6 : Operand<i16>
{
let EncoderMethod = "encodeImm<AVR::fixup_6_adiw, 0>";
}
/// An 8-bit immediate inside an instruction with the same format
/// as the `LDI` instruction (the `FRdK` format).
def imm_ldi8 : Operand<i8>
{
let EncoderMethod = "encodeImm<AVR::fixup_ldi, 0>";
}
/// A 5-bit port number used in SBIC and friends (the `FIOBIT` format).
def imm_port5 : Operand<i8>
{
let EncoderMethod = "encodeImm<AVR::fixup_port5, 0>";
}
/// A 6-bit port number used in the `IN` instruction and friends (the
/// `FIORdA` format.
def imm_port6 : Operand<i8>
{
let EncoderMethod = "encodeImm<AVR::fixup_port6, 0>";
}
// Addressing mode pattern reg+imm6
def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], [SDNPWantRoot]>;
// AsmOperand class for a pointer register.
// Used with the LD/ST family of instructions.
// See FSTLD in AVRInstrFormats.td
def PtrRegAsmOperand : AsmOperandClass
{
let Name = "Reg";
}
// A special operand type for the LD/ST instructions.
// It converts the pointer register number into a two-bit field used in the
// instruction.
def LDSTPtrReg : Operand<i16>
{
let MIOperandInfo = (ops PTRREGS);
let EncoderMethod = "encodeLDSTPtrReg";
let ParserMatchClass = PtrRegAsmOperand;
}
// A special operand type for the LDD/STD instructions.
// It behaves identically to the LD/ST version, except restricts
// the pointer registers to Y and Z.
def LDDSTDPtrReg : Operand<i16>
{
let MIOperandInfo = (ops PTRDISPREGS);
let EncoderMethod = "encodeLDSTPtrReg";
let ParserMatchClass = PtrRegAsmOperand;
}
//===----------------------------------------------------------------------===//
// AVR predicates for subtarget features
//===----------------------------------------------------------------------===//
def HasSRAM : Predicate<"Subtarget->hasSRAM()">,
AssemblerPredicate<(all_of FeatureSRAM)>;
def HasJMPCALL : Predicate<"Subtarget->hasJMPCALL()">,
AssemblerPredicate<(all_of FeatureJMPCALL)>;
def HasIJMPCALL : Predicate<"Subtarget->hasIJMPCALL()">,
AssemblerPredicate<(all_of FeatureIJMPCALL)>;
def HasEIJMPCALL : Predicate<"Subtarget->hasEIJMPCALL()">,
AssemblerPredicate<(all_of FeatureEIJMPCALL)>;
def HasADDSUBIW : Predicate<"Subtarget->hasADDSUBIW()">,
AssemblerPredicate<(all_of FeatureADDSUBIW)>;
def HasSmallStack : Predicate<"Subtarget->HasSmallStack()">,
AssemblerPredicate<(all_of FeatureSmallStack)>;
def HasMOVW : Predicate<"Subtarget->hasMOVW()">,
AssemblerPredicate<(all_of FeatureMOVW)>;
def HasLPM : Predicate<"Subtarget->hasLPM()">,
AssemblerPredicate<(all_of FeatureLPM)>;
def HasLPMX : Predicate<"Subtarget->hasLPMX()">,
AssemblerPredicate<(all_of FeatureLPMX)>;
def HasELPM : Predicate<"Subtarget->hasELPM()">,
AssemblerPredicate<(all_of FeatureELPM)>;
def HasELPMX : Predicate<"Subtarget->hasELPMX()">,
AssemblerPredicate<(all_of FeatureELPMX)>;
def HasSPM : Predicate<"Subtarget->hasSPM()">,
AssemblerPredicate<(all_of FeatureSPM)>;
def HasSPMX : Predicate<"Subtarget->hasSPMX()">,
AssemblerPredicate<(all_of FeatureSPMX)>;
def HasDES : Predicate<"Subtarget->hasDES()">,
AssemblerPredicate<(all_of FeatureDES)>;
def SupportsRMW : Predicate<"Subtarget->supportsRMW()">,
AssemblerPredicate<(all_of FeatureRMW)>;
def SupportsMultiplication : Predicate<"Subtarget->supportsMultiplication()">,
AssemblerPredicate<(all_of FeatureMultiplication)>;
def HasBREAK : Predicate<"Subtarget->hasBREAK()">,
AssemblerPredicate<(all_of FeatureBREAK)>;
def HasTinyEncoding : Predicate<"Subtarget->hasTinyEncoding()">,
AssemblerPredicate<(all_of FeatureTinyEncoding)>;
// AVR specific condition code. These correspond to AVR_*_COND in
// AVRInstrInfo.td. They must be kept in synch.
def AVR_COND_EQ : PatLeaf<(i8 0)>;
def AVR_COND_NE : PatLeaf<(i8 1)>;
def AVR_COND_GE : PatLeaf<(i8 2)>;
def AVR_COND_LT : PatLeaf<(i8 3)>;
def AVR_COND_SH : PatLeaf<(i8 4)>;
def AVR_COND_LO : PatLeaf<(i8 5)>;
def AVR_COND_MI : PatLeaf<(i8 6)>;
def AVR_COND_PL : PatLeaf<(i8 7)>;
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// AVR Instruction list
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into
// a stack adjustment and the codegen must know that they may modify the stack
// pointer before prolog-epilog rewriting occurs.
// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
// sub / add which can clobber SREG.
let Defs = [SP, SREG],
Uses = [SP] in
{
def ADJCALLSTACKDOWN : Pseudo<(outs),
(ins i16imm:$amt, i16imm:$amt2),
"#ADJCALLSTACKDOWN",
[(AVRcallseq_start timm:$amt, timm:$amt2)]>;
// R31R30 is used to update SP, since it is a scratch reg and this instruction
// is placed after the function call then R31R30 should be always free.
//let Defs = [R31R30],
//Uses = [R31R30] in
//:TODO: if we enable this, the pseudo is killed because it looks dead
def ADJCALLSTACKUP : Pseudo<(outs),
(ins i16imm:$amt1, i16imm:$amt2),
"#ADJCALLSTACKUP",
[(AVRcallseq_end timm:$amt1, timm:$amt2)]>;
}
//===----------------------------------------------------------------------===//
// Addition
//===----------------------------------------------------------------------===//
let isCommutable = 1,
Constraints = "$src = $rd",
Defs = [SREG] in
{
// ADD Rd, Rr
// Adds two 8-bit registers.
def ADDRdRr : FRdRr<0b0000,
0b11,
(outs GPR8:$rd),
(ins GPR8:$src, GPR8:$rr),
"add\t$rd, $rr",
[(set i8:$rd, (add i8:$src, i8:$rr)),
(implicit SREG)]>;
// ADDW Rd+1:Rd, Rr+1:Rr
// Pseudo instruction to add four 8-bit registers as two 16-bit values.
//
// Expands to:
// add Rd, Rr
// adc Rd+1, Rr+1
def ADDWRdRr : Pseudo<(outs DREGS:$rd),
(ins DREGS:$src, DREGS:$rr),
"addw\t$rd, $rr",
[(set i16:$rd, (add i16:$src, i16:$rr)),
(implicit SREG)]>;
// ADC Rd, Rr
// Adds two 8-bit registers with carry.
let Uses = [SREG] in
def ADCRdRr : FRdRr<0b0001,
0b11,
(outs GPR8:$rd),
(ins GPR8:$src, GPR8:$rr),
"adc\t$rd, $rr",
[(set i8:$rd, (adde i8:$src, i8:$rr)),
(implicit SREG)]>;
// ADCW Rd+1:Rd, Rr+1:Rr
// Pseudo instruction to add four 8-bit registers as two 16-bit values with
// carry.
//
// Expands to:
// adc Rd, Rr
// adc Rd+1, Rr+1
let Uses = [SREG] in
def ADCWRdRr : Pseudo<(outs DREGS:$rd),
(ins DREGS:$src, DREGS:$rr),
"adcw\t$rd, $rr",
[(set i16:$rd, (adde i16:$src, i16:$rr)),
(implicit SREG)]>;
// AIDW Rd, k
// Adds an immediate 6-bit value K to Rd, placing the result in Rd.
def ADIWRdK : FWRdK<0b0,
(outs IWREGS:$rd),
(ins IWREGS:$src, imm_arith6:$k),
"adiw\t$rd, $k",
[(set i16:$rd, (add i16:$src, uimm6:$k)),
(implicit SREG)]>,
Requires<[HasADDSUBIW]>;
}
//===----------------------------------------------------------------------===//
// Subtraction
//===----------------------------------------------------------------------===//
let Constraints = "$src = $rd",
Defs = [SREG] in
{
// SUB Rd, Rr
// Subtracts the 8-bit value of Rr from Rd and places the value in Rd.
def SUBRdRr : FRdRr<0b0001,
0b10,
(outs GPR8:$rd),
(ins GPR8:$src, GPR8:$rr),
"sub\t$rd, $rr",
[(set i8:$rd, (sub i8:$src, i8:$rr)),
(implicit SREG)]>;
// SUBW Rd+1:Rd, Rr+1:Rr
// Subtracts two 16-bit values and places the result into Rd.
//
// Expands to:
// sub Rd, Rr
// sbc Rd+1, Rr+1
def SUBWRdRr : Pseudo<(outs DREGS:$rd),
(ins DREGS:$src, DREGS:$rr),
"subw\t$rd, $rr",
[(set i16:$rd, (sub i16:$src, i16:$rr)),
(implicit SREG)]>;
def SUBIRdK : FRdK<0b0101,
(outs LD8:$rd),
(ins LD8:$src, imm_ldi8:$k),
"subi\t$rd, $k",
[(set i8:$rd, (sub i8:$src, imm:$k)),
(implicit SREG)]>;
// SUBIW Rd+1:Rd, K+1:K
//
// Expands to:
// subi Rd, K
// sbci Rd+1, K+1
def SUBIWRdK : Pseudo<(outs DLDREGS:$rd),
(ins DLDREGS:$src, i16imm:$rr),
"subiw\t$rd, $rr",
[(set i16:$rd, (sub i16:$src, imm:$rr)),
(implicit SREG)]>;
def SBIWRdK : FWRdK<0b1,
(outs IWREGS:$rd),
(ins IWREGS:$src, imm_arith6:$k),
"sbiw\t$rd, $k",
[(set i16:$rd, (sub i16:$src, uimm6:$k)),
(implicit SREG)]>,
Requires<[HasADDSUBIW]>;
// Subtract with carry operations which must read the carry flag in SREG.
let Uses = [SREG] in
{
def SBCRdRr : FRdRr<0b0000,
0b10,
(outs GPR8:$rd),
(ins GPR8:$src, GPR8:$rr),
"sbc\t$rd, $rr",
[(set i8:$rd, (sube i8:$src, i8:$rr)),
(implicit SREG)]>;
// SBCW Rd+1:Rd, Rr+1:Rr
//
// Expands to:
// sbc Rd, Rr
// sbc Rd+1, Rr+1
def SBCWRdRr : Pseudo<(outs DREGS:$rd),
(ins DREGS:$src, DREGS:$rr),
"sbcw\t$rd, $rr",
[(set i16:$rd, (sube i16:$src, i16:$rr)),
(implicit SREG)]>;
def SBCIRdK : FRdK<0b0100,
(outs LD8:$rd),
(ins LD8:$src, imm_ldi8:$k),
"sbci\t$rd, $k",
[(set i8:$rd, (sube i8:$src, imm:$k)),
(implicit SREG)]>;
// SBCIW Rd+1:Rd, K+1:K
// sbci Rd, K
// sbci Rd+1, K+1
def SBCIWRdK : Pseudo<(outs DLDREGS:$rd),
(ins DLDREGS:$src, i16imm:$rr),
"sbciw\t$rd, $rr",
[(set i16:$rd, (sube i16:$src, imm:$rr)),
(implicit SREG)]>;
}
}
//===----------------------------------------------------------------------===//
// Increment and Decrement
//===----------------------------------------------------------------------===//
let Constraints = "$src = $rd",
Defs = [SREG] in
{
def INCRd : FRd<0b1001,
0b0100011,
(outs GPR8:$rd),
(ins GPR8:$src),
"inc\t$rd",
[(set i8:$rd, (add i8:$src, 1)), (implicit SREG)]>;
def DECRd : FRd<0b1001,
0b0101010,
(outs GPR8:$rd),
(ins GPR8:$src),
"dec\t$rd",
[(set i8:$rd, (add i8:$src, -1)), (implicit SREG)]>;
}
//===----------------------------------------------------------------------===//
// Multiplication
//===----------------------------------------------------------------------===//
let isCommutable = 1,
Defs = [R1, R0, SREG] in
{
// MUL Rd, Rr
// Multiplies Rd by Rr and places the result into R1:R0.
let usesCustomInserter = 1 in {
def MULRdRr : FRdRr<0b1001, 0b11,
(outs),
(ins GPR8:$lhs, GPR8:$rhs),
"mul\t$lhs, $rhs",
[/*(set R1, R0, (smullohi i8:$lhs, i8:$rhs))*/]>,
Requires<[SupportsMultiplication]>;
def MULSRdRr : FMUL2RdRr<0,
(outs),
(ins LD8:$lhs, LD8:$rhs),
"muls\t$lhs, $rhs",
[]>,
Requires<[SupportsMultiplication]>;
}
def MULSURdRr : FMUL2RdRr<1,
(outs),
(ins LD8lo:$lhs, LD8lo:$rhs),
"mulsu\t$lhs, $rhs",
[]>,
Requires<[SupportsMultiplication]>;
def FMUL : FFMULRdRr<0b01,
(outs),
(ins LD8lo:$lhs, LD8lo:$rhs),
"fmul\t$lhs, $rhs",
[]>,
Requires<[SupportsMultiplication]>;
def FMULS : FFMULRdRr<0b10,
(outs),
(ins LD8lo:$lhs, LD8lo:$rhs),
"fmuls\t$lhs, $rhs",
[]>,
Requires<[SupportsMultiplication]>;
def FMULSU : FFMULRdRr<0b11,
(outs),
(ins LD8lo:$lhs, LD8lo:$rhs),
"fmulsu\t$lhs, $rhs",
[]>,
Requires<[SupportsMultiplication]>;
}
let Defs = [R15, R14, R13, R12, R11, R10, R9,
R8, R7, R6, R5, R4, R3, R2, R1, R0] in
def DESK : FDES<(outs),
(ins i8imm:$k),
"des\t$k",
[]>,
Requires<[HasDES]>;
//===----------------------------------------------------------------------===//
// Logic
//===----------------------------------------------------------------------===//
let Constraints = "$src = $rd",
Defs = [SREG] in
{
// Register-Register logic instructions (which have the
// property of commutativity).
let isCommutable = 1 in
{
def ANDRdRr : FRdRr<0b0010,
0b00,
(outs GPR8:$rd),
(ins GPR8:$src, GPR8:$rr),
"and\t$rd, $rr",
[(set i8:$rd, (and i8:$src, i8:$rr)),
(implicit SREG)]>;
// ANDW Rd+1:Rd, Rr+1:Rr
//
// Expands to:
// and Rd, Rr
// and Rd+1, Rr+1
def ANDWRdRr : Pseudo<(outs DREGS:$rd),
(ins DREGS:$src, DREGS:$rr),
"andw\t$rd, $rr",
[(set i16:$rd, (and i16:$src, i16:$rr)),
(implicit SREG)]>;
def ORRdRr : FRdRr<0b0010,
0b10,
(outs GPR8:$rd),
(ins GPR8:$src, GPR8:$rr),
"or\t$rd, $rr",
[(set i8:$rd, (or i8:$src, i8:$rr)),
(implicit SREG)]>;
// ORW Rd+1:Rd, Rr+1:Rr
//
// Expands to:
// or Rd, Rr
// or Rd+1, Rr+1
def ORWRdRr : Pseudo<(outs DREGS:$rd),
(ins DREGS:$src, DREGS:$rr),
"orw\t$rd, $rr",
[(set i16:$rd, (or i16:$src, i16:$rr)),
(implicit SREG)]>;
def EORRdRr : FRdRr<0b0010,
0b01,
(outs GPR8:$rd),
(ins GPR8:$src, GPR8:$rr),
"eor\t$rd, $rr",
[(set i8:$rd, (xor i8:$src, i8:$rr)),
(implicit SREG)]>;
// EORW Rd+1:Rd, Rr+1:Rr
//
// Expands to:
// eor Rd, Rr
// eor Rd+1, Rr+1
def EORWRdRr : Pseudo<(outs DREGS:$rd),
(ins DREGS:$src, DREGS:$rr),
"eorw\t$rd, $rr",
[(set i16:$rd, (xor i16:$src, i16:$rr)),
(implicit SREG)]>;
}
def ANDIRdK : FRdK<0b0111,
(outs LD8:$rd),
(ins LD8:$src, imm_ldi8:$k),
"andi\t$rd, $k",
[(set i8:$rd, (and i8:$src, imm:$k)),
(implicit SREG)]>;
// ANDI Rd+1:Rd, K+1:K
//
// Expands to:
// andi Rd, K
// andi Rd+1, K+1
def ANDIWRdK : Pseudo<(outs DLDREGS:$rd),
(ins DLDREGS:$src, i16imm:$k),
"andiw\t$rd, $k",
[(set i16:$rd, (and i16:$src, imm:$k)),
(implicit SREG)]>;
def ORIRdK : FRdK<0b0110,
(outs LD8:$rd),
(ins LD8:$src, imm_ldi8:$k),
"ori\t$rd, $k",
[(set i8:$rd, (or i8:$src, imm:$k)),
(implicit SREG)]>;
// ORIW Rd+1:Rd, K+1,K
//
// Expands to:
// ori Rd, K
// ori Rd+1, K+1
def ORIWRdK : Pseudo<(outs DLDREGS:$rd),
(ins DLDREGS:$src, i16imm:$rr),
"oriw\t$rd, $rr",
[(set i16:$rd, (or i16:$src, imm:$rr)),
(implicit SREG)]>;
}
//===----------------------------------------------------------------------===//
// One's/Two's Complement
//===----------------------------------------------------------------------===//
let Constraints = "$src = $rd",
Defs = [SREG] in
{
def COMRd : FRd<0b1001,
0b0100000,
(outs GPR8:$rd),
(ins GPR8:$src),
"com\t$rd",
[(set i8:$rd, (not i8:$src)), (implicit SREG)]>;
// COMW Rd+1:Rd
//
// Expands to:
// com Rd
// com Rd+1
def COMWRd : Pseudo<(outs DREGS:$rd),
(ins DREGS:$src),
"comw\t$rd",
[(set i16:$rd, (not i16:$src)), (implicit SREG)]>;
def NEGRd : FRd<0b1001,
0b0100001,
(outs GPR8:$rd),
(ins GPR8:$src),
"neg\t$rd",
[(set i8:$rd, (ineg i8:$src)), (implicit SREG)]>;
// NEGW Rd+1:Rd
//
// Expands to:
// neg Rd+1
// neg Rd
// sbc Rd+1, r1
def NEGWRd : Pseudo<(outs DREGS:$rd),
(ins DREGS:$src),
"negw\t$rd",
[(set i16:$rd, (ineg i16:$src)), (implicit SREG)]>;
}
// TST Rd
// Test for zero of minus.
// This operation is identical to a `Rd AND Rd`.
def : InstAlias<"tst\t$rd", (ANDRdRr GPR8:$rd, GPR8:$rd)>;
// SBR Rd, K
//
// Mnemonic alias to 'ORI Rd, K'. Same bit pattern, same operands,
// same everything.
def : InstAlias<"sbr\t$rd, $k",
(ORIRdK LD8:$rd, imm_ldi8:$k),
/* Disable display, so we don't override ORI */ 0>;
//===----------------------------------------------------------------------===//
// Jump instructions
//===----------------------------------------------------------------------===//
let isBarrier = 1,
isBranch = 1,
isTerminator = 1 in
{
def RJMPk : FBRk<0,
(outs),
(ins brtarget_13:$target),
"rjmp\t$target",
[(br bb:$target)]>;
let isIndirectBranch = 1,
Uses = [R31R30] in
def IJMP : F16<0b1001010000001001,
(outs),
(ins),
"ijmp",
[]>,
Requires<[HasIJMPCALL]>;
let isIndirectBranch = 1,
Uses = [R31R30] in
def EIJMP : F16<0b1001010000011001,
(outs),
(ins),
"eijmp",
[]>,
Requires<[HasEIJMPCALL]>;
def JMPk : F32BRk<0b110,
(outs),
(ins call_target:$k),
"jmp\t$k",
[]>,
Requires<[HasJMPCALL]>;
}
//===----------------------------------------------------------------------===//
// Call instructions
//===----------------------------------------------------------------------===//
let isCall = 1 in
{
// SP is marked as a use to prevent stack-pointer assignments that appear
// immediately before calls from potentially appearing dead.
let Uses = [SP] in
def RCALLk : FBRk<1,
(outs),
(ins brtarget_13:$target),
"rcall\t$target",
[]>;
// SP is marked as a use to prevent stack-pointer assignments that appear
// immediately before calls from potentially appearing dead.
let Uses = [SP, R31R30] in
def ICALL : F16<0b1001010100001001,
(outs),
(ins variable_ops),
"icall",
[]>,
Requires<[HasIJMPCALL]>;
// SP is marked as a use to prevent stack-pointer assignments that appear
// immediately before calls from potentially appearing dead.
let Uses = [SP, R31R30] in
def EICALL : F16<0b1001010100011001,
(outs),
(ins variable_ops),
"eicall",
[]>,
Requires<[HasEIJMPCALL]>;
// SP is marked as a use to prevent stack-pointer assignments that appear
// immediately before calls from potentially appearing dead.
//
//:TODO: the imm field can be either 16 or 22 bits in devices with more
// than 64k of ROM, fix it once we support the largest devices.
let Uses = [SP] in
def CALLk : F32BRk<0b111,
(outs),
(ins call_target:$k),
"call\t$k",
[(AVRcall imm:$k)]>,
Requires<[HasJMPCALL]>;
}
//===----------------------------------------------------------------------===//
// Return instructions.
//===----------------------------------------------------------------------===//
let isTerminator = 1,
isReturn = 1,
isBarrier = 1 in
{
def RET : F16<0b1001010100001000,
(outs),
(ins),
"ret",
[(AVRretflag)]>;
def RETI : F16<0b1001010100011000,
(outs),
(ins),
"reti",
[(AVRretiflag)]>;
}
//===----------------------------------------------------------------------===//
// Compare operations.
//===----------------------------------------------------------------------===//
let Defs = [SREG] in
{
// CPSE Rd, Rr
// Compare Rd and Rr, skipping the next instruction if they are equal.
let isBarrier = 1,
isBranch = 1,
isTerminator = 1 in
def CPSE : FRdRr<0b0001,
0b00,
(outs),
(ins GPR8:$rd, GPR8:$rr),
"cpse\t$rd, $rr",
[]>;
def CPRdRr : FRdRr<0b0001,
0b01,
(outs),
(ins GPR8:$rd, GPR8:$rr),
"cp\t$rd, $rr",
[(AVRcmp i8:$rd, i8:$rr), (implicit SREG)]>;
// CPW Rd+1:Rd, Rr+1:Rr
//
// Expands to:
// cp Rd, Rr
// cpc Rd+1, Rr+1
def CPWRdRr : Pseudo<(outs),
(ins DREGS:$src, DREGS:$src2),
"cpw\t$src, $src2",
[(AVRcmp i16:$src, i16:$src2), (implicit SREG)]>;
let Uses = [SREG] in
def CPCRdRr : FRdRr<0b0000,
0b01,
(outs),
(ins GPR8:$rd, GPR8:$rr),
"cpc\t$rd, $rr",
[(AVRcmpc i8:$rd, i8:$rr), (implicit SREG)]>;
// CPCW Rd+1:Rd. Rr+1:Rr
//
// Expands to:
// cpc Rd, Rr
// cpc Rd+1, Rr+1
let Uses = [SREG] in
def CPCWRdRr : Pseudo<(outs),
(ins DREGS:$src, DREGS:$src2),
"cpcw\t$src, $src2",
[(AVRcmpc i16:$src, i16:$src2), (implicit SREG)]>;
// CPI Rd, K
// Compares a register with an 8 bit immediate.
def CPIRdK : FRdK<0b0011,
(outs),
(ins LD8:$rd, imm_ldi8:$k),
"cpi\t$rd, $k",
[(AVRcmp i8:$rd, imm:$k), (implicit SREG)]>;
}
//===----------------------------------------------------------------------===//
// Register conditional skipping/branching operations.
//===----------------------------------------------------------------------===//
let isBranch = 1,
isTerminator = 1 in
{
// Conditional skipping on GPR register bits, and
// conditional skipping on IO register bits.
let isBarrier = 1 in
{
def SBRCRrB : FRdB<0b10,
(outs),
(ins GPR8:$rr, i8imm:$b),
"sbrc\t$rr, $b",
[]>;
def SBRSRrB : FRdB<0b11,
(outs),
(ins GPR8:$rr, i8imm:$b),
"sbrs\t$rr, $b",
[]>;
def SBICAb : FIOBIT<0b01,
(outs),
(ins imm_port5:$a, i8imm:$b),
"sbic\t$a, $b",
[]>;
def SBISAb : FIOBIT<0b11,
(outs),
(ins imm_port5:$a, i8imm:$b),
"sbis\t$a, $b",
[]>;
}
// Relative branches on status flag bits.
let Uses = [SREG] in
{
// BRBS s, k
// Branch if `s` flag in status register is set.
def BRBSsk : FSK<0,
(outs),
(ins i8imm:$s, relbrtarget_7:$k),
"brbs\t$s, $k",
[]>;
// BRBC s, k
// Branch if `s` flag in status register is clear.
def BRBCsk : FSK<1,
(outs),
(ins i8imm:$s, relbrtarget_7:$k),
"brbc\t$s, $k",