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Registers.hpp
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Registers.hpp
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//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//
// Models register sets for supported processors.
//
//===----------------------------------------------------------------------===//
#ifndef __REGISTERS_HPP__
#define __REGISTERS_HPP__
#include <stdint.h>
#include <string.h>
#include "cet_unwind.h"
#include "config.h"
#include "libunwind.h"
namespace libunwind {
// For emulating 128-bit registers
struct v128 { uint32_t vec[4]; };
enum {
REGISTERS_X86,
REGISTERS_X86_64,
REGISTERS_PPC,
REGISTERS_PPC64,
REGISTERS_ARM64,
REGISTERS_ARM,
REGISTERS_OR1K,
REGISTERS_MIPS_O32,
REGISTERS_MIPS_NEWABI,
REGISTERS_SPARC,
REGISTERS_SPARC64,
REGISTERS_HEXAGON,
REGISTERS_RISCV,
REGISTERS_VE,
REGISTERS_S390X,
REGISTERS_LOONGARCH,
};
#if defined(_LIBUNWIND_TARGET_I386)
class _LIBUNWIND_HIDDEN Registers_x86;
extern "C" void __libunwind_Registers_x86_jumpto(Registers_x86 *);
#if defined(_LIBUNWIND_USE_CET)
extern "C" void *__libunwind_cet_get_jump_target() {
return reinterpret_cast<void *>(&__libunwind_Registers_x86_jumpto);
}
#endif
/// Registers_x86 holds the register state of a thread in a 32-bit intel
/// process.
class _LIBUNWIND_HIDDEN Registers_x86 {
public:
Registers_x86();
Registers_x86(const void *registers);
bool validRegister(int num) const;
uint32_t getRegister(int num) const;
void setRegister(int num, uint32_t value);
bool validFloatRegister(int) const { return false; }
double getFloatRegister(int num) const;
void setFloatRegister(int num, double value);
bool validVectorRegister(int) const { return false; }
v128 getVectorRegister(int num) const;
void setVectorRegister(int num, v128 value);
static const char *getRegisterName(int num);
void jumpto() { __libunwind_Registers_x86_jumpto(this); }
static constexpr int lastDwarfRegNum() {
return _LIBUNWIND_HIGHEST_DWARF_REGISTER_X86;
}
static int getArch() { return REGISTERS_X86; }
uint32_t getSP() const { return _registers.__esp; }
void setSP(uint32_t value) { _registers.__esp = value; }
uint32_t getIP() const { return _registers.__eip; }
void setIP(uint32_t value) { _registers.__eip = value; }
uint32_t getEBP() const { return _registers.__ebp; }
void setEBP(uint32_t value) { _registers.__ebp = value; }
uint32_t getEBX() const { return _registers.__ebx; }
void setEBX(uint32_t value) { _registers.__ebx = value; }
uint32_t getECX() const { return _registers.__ecx; }
void setECX(uint32_t value) { _registers.__ecx = value; }
uint32_t getEDX() const { return _registers.__edx; }
void setEDX(uint32_t value) { _registers.__edx = value; }
uint32_t getESI() const { return _registers.__esi; }
void setESI(uint32_t value) { _registers.__esi = value; }
uint32_t getEDI() const { return _registers.__edi; }
void setEDI(uint32_t value) { _registers.__edi = value; }
private:
struct GPRs {
unsigned int __eax;
unsigned int __ebx;
unsigned int __ecx;
unsigned int __edx;
unsigned int __edi;
unsigned int __esi;
unsigned int __ebp;
unsigned int __esp;
unsigned int __ss;
unsigned int __eflags;
unsigned int __eip;
unsigned int __cs;
unsigned int __ds;
unsigned int __es;
unsigned int __fs;
unsigned int __gs;
};
GPRs _registers;
};
inline Registers_x86::Registers_x86(const void *registers) {
static_assert((check_fit<Registers_x86, unw_context_t>::does_fit),
"x86 registers do not fit into unw_context_t");
memcpy(&_registers, registers, sizeof(_registers));
}
inline Registers_x86::Registers_x86() {
memset(&_registers, 0, sizeof(_registers));
}
inline bool Registers_x86::validRegister(int regNum) const {
if (regNum == UNW_REG_IP)
return true;
if (regNum == UNW_REG_SP)
return true;
if (regNum < 0)
return false;
if (regNum > 7)
return false;
return true;
}
inline uint32_t Registers_x86::getRegister(int regNum) const {
switch (regNum) {
case UNW_REG_IP:
return _registers.__eip;
case UNW_REG_SP:
return _registers.__esp;
case UNW_X86_EAX:
return _registers.__eax;
case UNW_X86_ECX:
return _registers.__ecx;
case UNW_X86_EDX:
return _registers.__edx;
case UNW_X86_EBX:
return _registers.__ebx;
#if !defined(__APPLE__)
case UNW_X86_ESP:
#else
case UNW_X86_EBP:
#endif
return _registers.__ebp;
#if !defined(__APPLE__)
case UNW_X86_EBP:
#else
case UNW_X86_ESP:
#endif
return _registers.__esp;
case UNW_X86_ESI:
return _registers.__esi;
case UNW_X86_EDI:
return _registers.__edi;
}
_LIBUNWIND_ABORT("unsupported x86 register");
}
inline void Registers_x86::setRegister(int regNum, uint32_t value) {
switch (regNum) {
case UNW_REG_IP:
_registers.__eip = value;
return;
case UNW_REG_SP:
_registers.__esp = value;
return;
case UNW_X86_EAX:
_registers.__eax = value;
return;
case UNW_X86_ECX:
_registers.__ecx = value;
return;
case UNW_X86_EDX:
_registers.__edx = value;
return;
case UNW_X86_EBX:
_registers.__ebx = value;
return;
#if !defined(__APPLE__)
case UNW_X86_ESP:
#else
case UNW_X86_EBP:
#endif
_registers.__ebp = value;
return;
#if !defined(__APPLE__)
case UNW_X86_EBP:
#else
case UNW_X86_ESP:
#endif
_registers.__esp = value;
return;
case UNW_X86_ESI:
_registers.__esi = value;
return;
case UNW_X86_EDI:
_registers.__edi = value;
return;
}
_LIBUNWIND_ABORT("unsupported x86 register");
}
inline const char *Registers_x86::getRegisterName(int regNum) {
switch (regNum) {
case UNW_REG_IP:
return "ip";
case UNW_REG_SP:
return "esp";
case UNW_X86_EAX:
return "eax";
case UNW_X86_ECX:
return "ecx";
case UNW_X86_EDX:
return "edx";
case UNW_X86_EBX:
return "ebx";
case UNW_X86_EBP:
return "ebp";
case UNW_X86_ESP:
return "esp";
case UNW_X86_ESI:
return "esi";
case UNW_X86_EDI:
return "edi";
default:
return "unknown register";
}
}
inline double Registers_x86::getFloatRegister(int) const {
_LIBUNWIND_ABORT("no x86 float registers");
}
inline void Registers_x86::setFloatRegister(int, double) {
_LIBUNWIND_ABORT("no x86 float registers");
}
inline v128 Registers_x86::getVectorRegister(int) const {
_LIBUNWIND_ABORT("no x86 vector registers");
}
inline void Registers_x86::setVectorRegister(int, v128) {
_LIBUNWIND_ABORT("no x86 vector registers");
}
#endif // _LIBUNWIND_TARGET_I386
#if defined(_LIBUNWIND_TARGET_X86_64)
/// Registers_x86_64 holds the register state of a thread in a 64-bit intel
/// process.
class _LIBUNWIND_HIDDEN Registers_x86_64;
extern "C" void __libunwind_Registers_x86_64_jumpto(Registers_x86_64 *);
#if defined(_LIBUNWIND_USE_CET)
extern "C" void *__libunwind_cet_get_jump_target() {
return reinterpret_cast<void *>(&__libunwind_Registers_x86_64_jumpto);
}
#endif
class _LIBUNWIND_HIDDEN Registers_x86_64 {
public:
Registers_x86_64();
Registers_x86_64(const void *registers);
bool validRegister(int num) const;
uint64_t getRegister(int num) const;
void setRegister(int num, uint64_t value);
bool validFloatRegister(int) const { return false; }
double getFloatRegister(int num) const;
void setFloatRegister(int num, double value);
bool validVectorRegister(int) const;
v128 getVectorRegister(int num) const;
void setVectorRegister(int num, v128 value);
static const char *getRegisterName(int num);
void jumpto() { __libunwind_Registers_x86_64_jumpto(this); }
static constexpr int lastDwarfRegNum() {
return _LIBUNWIND_HIGHEST_DWARF_REGISTER_X86_64;
}
static int getArch() { return REGISTERS_X86_64; }
uint64_t getSP() const { return _registers.__rsp; }
void setSP(uint64_t value) { _registers.__rsp = value; }
uint64_t getIP() const { return _registers.__rip; }
void setIP(uint64_t value) { _registers.__rip = value; }
uint64_t getRBP() const { return _registers.__rbp; }
void setRBP(uint64_t value) { _registers.__rbp = value; }
uint64_t getRBX() const { return _registers.__rbx; }
void setRBX(uint64_t value) { _registers.__rbx = value; }
uint64_t getR12() const { return _registers.__r12; }
void setR12(uint64_t value) { _registers.__r12 = value; }
uint64_t getR13() const { return _registers.__r13; }
void setR13(uint64_t value) { _registers.__r13 = value; }
uint64_t getR14() const { return _registers.__r14; }
void setR14(uint64_t value) { _registers.__r14 = value; }
uint64_t getR15() const { return _registers.__r15; }
void setR15(uint64_t value) { _registers.__r15 = value; }
private:
struct GPRs {
uint64_t __rax;
uint64_t __rbx;
uint64_t __rcx;
uint64_t __rdx;
uint64_t __rdi;
uint64_t __rsi;
uint64_t __rbp;
uint64_t __rsp;
uint64_t __r8;
uint64_t __r9;
uint64_t __r10;
uint64_t __r11;
uint64_t __r12;
uint64_t __r13;
uint64_t __r14;
uint64_t __r15;
uint64_t __rip;
uint64_t __rflags;
uint64_t __cs;
uint64_t __fs;
uint64_t __gs;
#if defined(_WIN64)
uint64_t __padding; // 16-byte align
#endif
};
GPRs _registers;
#if defined(_WIN64)
v128 _xmm[16];
#endif
};
inline Registers_x86_64::Registers_x86_64(const void *registers) {
static_assert((check_fit<Registers_x86_64, unw_context_t>::does_fit),
"x86_64 registers do not fit into unw_context_t");
memcpy(&_registers, registers, sizeof(_registers));
}
inline Registers_x86_64::Registers_x86_64() {
memset(&_registers, 0, sizeof(_registers));
}
inline bool Registers_x86_64::validRegister(int regNum) const {
if (regNum == UNW_REG_IP)
return true;
if (regNum == UNW_REG_SP)
return true;
if (regNum < 0)
return false;
if (regNum > 16)
return false;
return true;
}
inline uint64_t Registers_x86_64::getRegister(int regNum) const {
switch (regNum) {
case UNW_REG_IP:
case UNW_X86_64_RIP:
return _registers.__rip;
case UNW_REG_SP:
return _registers.__rsp;
case UNW_X86_64_RAX:
return _registers.__rax;
case UNW_X86_64_RDX:
return _registers.__rdx;
case UNW_X86_64_RCX:
return _registers.__rcx;
case UNW_X86_64_RBX:
return _registers.__rbx;
case UNW_X86_64_RSI:
return _registers.__rsi;
case UNW_X86_64_RDI:
return _registers.__rdi;
case UNW_X86_64_RBP:
return _registers.__rbp;
case UNW_X86_64_RSP:
return _registers.__rsp;
case UNW_X86_64_R8:
return _registers.__r8;
case UNW_X86_64_R9:
return _registers.__r9;
case UNW_X86_64_R10:
return _registers.__r10;
case UNW_X86_64_R11:
return _registers.__r11;
case UNW_X86_64_R12:
return _registers.__r12;
case UNW_X86_64_R13:
return _registers.__r13;
case UNW_X86_64_R14:
return _registers.__r14;
case UNW_X86_64_R15:
return _registers.__r15;
}
_LIBUNWIND_ABORT("unsupported x86_64 register");
}
inline void Registers_x86_64::setRegister(int regNum, uint64_t value) {
switch (regNum) {
case UNW_REG_IP:
case UNW_X86_64_RIP:
_registers.__rip = value;
return;
case UNW_REG_SP:
_registers.__rsp = value;
return;
case UNW_X86_64_RAX:
_registers.__rax = value;
return;
case UNW_X86_64_RDX:
_registers.__rdx = value;
return;
case UNW_X86_64_RCX:
_registers.__rcx = value;
return;
case UNW_X86_64_RBX:
_registers.__rbx = value;
return;
case UNW_X86_64_RSI:
_registers.__rsi = value;
return;
case UNW_X86_64_RDI:
_registers.__rdi = value;
return;
case UNW_X86_64_RBP:
_registers.__rbp = value;
return;
case UNW_X86_64_RSP:
_registers.__rsp = value;
return;
case UNW_X86_64_R8:
_registers.__r8 = value;
return;
case UNW_X86_64_R9:
_registers.__r9 = value;
return;
case UNW_X86_64_R10:
_registers.__r10 = value;
return;
case UNW_X86_64_R11:
_registers.__r11 = value;
return;
case UNW_X86_64_R12:
_registers.__r12 = value;
return;
case UNW_X86_64_R13:
_registers.__r13 = value;
return;
case UNW_X86_64_R14:
_registers.__r14 = value;
return;
case UNW_X86_64_R15:
_registers.__r15 = value;
return;
}
_LIBUNWIND_ABORT("unsupported x86_64 register");
}
inline const char *Registers_x86_64::getRegisterName(int regNum) {
switch (regNum) {
case UNW_REG_IP:
case UNW_X86_64_RIP:
return "rip";
case UNW_REG_SP:
return "rsp";
case UNW_X86_64_RAX:
return "rax";
case UNW_X86_64_RDX:
return "rdx";
case UNW_X86_64_RCX:
return "rcx";
case UNW_X86_64_RBX:
return "rbx";
case UNW_X86_64_RSI:
return "rsi";
case UNW_X86_64_RDI:
return "rdi";
case UNW_X86_64_RBP:
return "rbp";
case UNW_X86_64_RSP:
return "rsp";
case UNW_X86_64_R8:
return "r8";
case UNW_X86_64_R9:
return "r9";
case UNW_X86_64_R10:
return "r10";
case UNW_X86_64_R11:
return "r11";
case UNW_X86_64_R12:
return "r12";
case UNW_X86_64_R13:
return "r13";
case UNW_X86_64_R14:
return "r14";
case UNW_X86_64_R15:
return "r15";
case UNW_X86_64_XMM0:
return "xmm0";
case UNW_X86_64_XMM1:
return "xmm1";
case UNW_X86_64_XMM2:
return "xmm2";
case UNW_X86_64_XMM3:
return "xmm3";
case UNW_X86_64_XMM4:
return "xmm4";
case UNW_X86_64_XMM5:
return "xmm5";
case UNW_X86_64_XMM6:
return "xmm6";
case UNW_X86_64_XMM7:
return "xmm7";
case UNW_X86_64_XMM8:
return "xmm8";
case UNW_X86_64_XMM9:
return "xmm9";
case UNW_X86_64_XMM10:
return "xmm10";
case UNW_X86_64_XMM11:
return "xmm11";
case UNW_X86_64_XMM12:
return "xmm12";
case UNW_X86_64_XMM13:
return "xmm13";
case UNW_X86_64_XMM14:
return "xmm14";
case UNW_X86_64_XMM15:
return "xmm15";
default:
return "unknown register";
}
}
inline double Registers_x86_64::getFloatRegister(int) const {
_LIBUNWIND_ABORT("no x86_64 float registers");
}
inline void Registers_x86_64::setFloatRegister(int, double) {
_LIBUNWIND_ABORT("no x86_64 float registers");
}
inline bool Registers_x86_64::validVectorRegister(int regNum) const {
#if defined(_WIN64)
if (regNum < UNW_X86_64_XMM0)
return false;
if (regNum > UNW_X86_64_XMM15)
return false;
return true;
#else
(void)regNum; // suppress unused parameter warning
return false;
#endif
}
inline v128 Registers_x86_64::getVectorRegister(int regNum) const {
#if defined(_WIN64)
assert(validVectorRegister(regNum));
return _xmm[regNum - UNW_X86_64_XMM0];
#else
(void)regNum; // suppress unused parameter warning
_LIBUNWIND_ABORT("no x86_64 vector registers");
#endif
}
inline void Registers_x86_64::setVectorRegister(int regNum, v128 value) {
#if defined(_WIN64)
assert(validVectorRegister(regNum));
_xmm[regNum - UNW_X86_64_XMM0] = value;
#else
(void)regNum; (void)value; // suppress unused parameter warnings
_LIBUNWIND_ABORT("no x86_64 vector registers");
#endif
}
#endif // _LIBUNWIND_TARGET_X86_64
#if defined(_LIBUNWIND_TARGET_PPC)
/// Registers_ppc holds the register state of a thread in a 32-bit PowerPC
/// process.
class _LIBUNWIND_HIDDEN Registers_ppc {
public:
Registers_ppc();
Registers_ppc(const void *registers);
bool validRegister(int num) const;
uint32_t getRegister(int num) const;
void setRegister(int num, uint32_t value);
bool validFloatRegister(int num) const;
double getFloatRegister(int num) const;
void setFloatRegister(int num, double value);
bool validVectorRegister(int num) const;
v128 getVectorRegister(int num) const;
void setVectorRegister(int num, v128 value);
static const char *getRegisterName(int num);
void jumpto();
static constexpr int lastDwarfRegNum() {
return _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC;
}
static int getArch() { return REGISTERS_PPC; }
uint64_t getSP() const { return _registers.__r1; }
void setSP(uint32_t value) { _registers.__r1 = value; }
uint64_t getIP() const { return _registers.__srr0; }
void setIP(uint32_t value) { _registers.__srr0 = value; }
uint64_t getCR() const { return _registers.__cr; }
void setCR(uint32_t value) { _registers.__cr = value; }
private:
struct ppc_thread_state_t {
unsigned int __srr0; /* Instruction address register (PC) */
unsigned int __srr1; /* Machine state register (supervisor) */
unsigned int __r0;
unsigned int __r1;
unsigned int __r2;
unsigned int __r3;
unsigned int __r4;
unsigned int __r5;
unsigned int __r6;
unsigned int __r7;
unsigned int __r8;
unsigned int __r9;
unsigned int __r10;
unsigned int __r11;
unsigned int __r12;
unsigned int __r13;
unsigned int __r14;
unsigned int __r15;
unsigned int __r16;
unsigned int __r17;
unsigned int __r18;
unsigned int __r19;
unsigned int __r20;
unsigned int __r21;
unsigned int __r22;
unsigned int __r23;
unsigned int __r24;
unsigned int __r25;
unsigned int __r26;
unsigned int __r27;
unsigned int __r28;
unsigned int __r29;
unsigned int __r30;
unsigned int __r31;
unsigned int __cr; /* Condition register */
unsigned int __xer; /* User's integer exception register */
unsigned int __lr; /* Link register */
unsigned int __ctr; /* Count register */
unsigned int __mq; /* MQ register (601 only) */
unsigned int __vrsave; /* Vector Save Register */
};
struct ppc_float_state_t {
double __fpregs[32];
unsigned int __fpscr_pad; /* fpscr is 64 bits, 32 bits of rubbish */
unsigned int __fpscr; /* floating point status register */
};
ppc_thread_state_t _registers;
ppc_float_state_t _floatRegisters;
v128 _vectorRegisters[32]; // offset 424
};
inline Registers_ppc::Registers_ppc(const void *registers) {
static_assert((check_fit<Registers_ppc, unw_context_t>::does_fit),
"ppc registers do not fit into unw_context_t");
memcpy(&_registers, static_cast<const uint8_t *>(registers),
sizeof(_registers));
static_assert(sizeof(ppc_thread_state_t) == 160,
"expected float register offset to be 160");
memcpy(&_floatRegisters,
static_cast<const uint8_t *>(registers) + sizeof(ppc_thread_state_t),
sizeof(_floatRegisters));
static_assert(sizeof(ppc_thread_state_t) + sizeof(ppc_float_state_t) == 424,
"expected vector register offset to be 424 bytes");
memcpy(_vectorRegisters,
static_cast<const uint8_t *>(registers) + sizeof(ppc_thread_state_t) +
sizeof(ppc_float_state_t),
sizeof(_vectorRegisters));
}
inline Registers_ppc::Registers_ppc() {
memset(&_registers, 0, sizeof(_registers));
memset(&_floatRegisters, 0, sizeof(_floatRegisters));
memset(&_vectorRegisters, 0, sizeof(_vectorRegisters));
}
inline bool Registers_ppc::validRegister(int regNum) const {
if (regNum == UNW_REG_IP)
return true;
if (regNum == UNW_REG_SP)
return true;
if (regNum == UNW_PPC_VRSAVE)
return true;
if (regNum < 0)
return false;
if (regNum <= UNW_PPC_R31)
return true;
if (regNum == UNW_PPC_MQ)
return true;
if (regNum == UNW_PPC_LR)
return true;
if (regNum == UNW_PPC_CTR)
return true;
if ((UNW_PPC_CR0 <= regNum) && (regNum <= UNW_PPC_CR7))
return true;
return false;
}
inline uint32_t Registers_ppc::getRegister(int regNum) const {
switch (regNum) {
case UNW_REG_IP:
return _registers.__srr0;
case UNW_REG_SP:
return _registers.__r1;
case UNW_PPC_R0:
return _registers.__r0;
case UNW_PPC_R1:
return _registers.__r1;
case UNW_PPC_R2:
return _registers.__r2;
case UNW_PPC_R3:
return _registers.__r3;
case UNW_PPC_R4:
return _registers.__r4;
case UNW_PPC_R5:
return _registers.__r5;
case UNW_PPC_R6:
return _registers.__r6;
case UNW_PPC_R7:
return _registers.__r7;
case UNW_PPC_R8:
return _registers.__r8;
case UNW_PPC_R9:
return _registers.__r9;
case UNW_PPC_R10:
return _registers.__r10;
case UNW_PPC_R11:
return _registers.__r11;
case UNW_PPC_R12:
return _registers.__r12;
case UNW_PPC_R13:
return _registers.__r13;
case UNW_PPC_R14:
return _registers.__r14;
case UNW_PPC_R15:
return _registers.__r15;
case UNW_PPC_R16:
return _registers.__r16;
case UNW_PPC_R17:
return _registers.__r17;
case UNW_PPC_R18:
return _registers.__r18;
case UNW_PPC_R19:
return _registers.__r19;
case UNW_PPC_R20:
return _registers.__r20;
case UNW_PPC_R21:
return _registers.__r21;
case UNW_PPC_R22:
return _registers.__r22;
case UNW_PPC_R23:
return _registers.__r23;
case UNW_PPC_R24:
return _registers.__r24;
case UNW_PPC_R25:
return _registers.__r25;
case UNW_PPC_R26:
return _registers.__r26;
case UNW_PPC_R27:
return _registers.__r27;
case UNW_PPC_R28:
return _registers.__r28;
case UNW_PPC_R29:
return _registers.__r29;
case UNW_PPC_R30:
return _registers.__r30;
case UNW_PPC_R31:
return _registers.__r31;
case UNW_PPC_LR:
return _registers.__lr;
case UNW_PPC_CR0:
return (_registers.__cr & 0xF0000000);
case UNW_PPC_CR1:
return (_registers.__cr & 0x0F000000);
case UNW_PPC_CR2:
return (_registers.__cr & 0x00F00000);
case UNW_PPC_CR3:
return (_registers.__cr & 0x000F0000);
case UNW_PPC_CR4:
return (_registers.__cr & 0x0000F000);
case UNW_PPC_CR5:
return (_registers.__cr & 0x00000F00);
case UNW_PPC_CR6:
return (_registers.__cr & 0x000000F0);
case UNW_PPC_CR7:
return (_registers.__cr & 0x0000000F);
case UNW_PPC_VRSAVE:
return _registers.__vrsave;
}
_LIBUNWIND_ABORT("unsupported ppc register");
}
inline void Registers_ppc::setRegister(int regNum, uint32_t value) {
//fprintf(stderr, "Registers_ppc::setRegister(%d, 0x%08X)\n", regNum, value);
switch (regNum) {
case UNW_REG_IP:
_registers.__srr0 = value;
return;
case UNW_REG_SP:
_registers.__r1 = value;
return;
case UNW_PPC_R0:
_registers.__r0 = value;
return;
case UNW_PPC_R1:
_registers.__r1 = value;
return;
case UNW_PPC_R2:
_registers.__r2 = value;
return;
case UNW_PPC_R3:
_registers.__r3 = value;
return;
case UNW_PPC_R4:
_registers.__r4 = value;
return;
case UNW_PPC_R5:
_registers.__r5 = value;
return;
case UNW_PPC_R6:
_registers.__r6 = value;
return;
case UNW_PPC_R7:
_registers.__r7 = value;
return;
case UNW_PPC_R8:
_registers.__r8 = value;
return;
case UNW_PPC_R9:
_registers.__r9 = value;
return;
case UNW_PPC_R10:
_registers.__r10 = value;
return;
case UNW_PPC_R11:
_registers.__r11 = value;
return;
case UNW_PPC_R12:
_registers.__r12 = value;
return;
case UNW_PPC_R13:
_registers.__r13 = value;
return;
case UNW_PPC_R14:
_registers.__r14 = value;
return;
case UNW_PPC_R15:
_registers.__r15 = value;
return;
case UNW_PPC_R16:
_registers.__r16 = value;
return;
case UNW_PPC_R17:
_registers.__r17 = value;
return;
case UNW_PPC_R18:
_registers.__r18 = value;
return;
case UNW_PPC_R19:
_registers.__r19 = value;
return;
case UNW_PPC_R20:
_registers.__r20 = value;
return;
case UNW_PPC_R21:
_registers.__r21 = value;
return;
case UNW_PPC_R22:
_registers.__r22 = value;
return;
case UNW_PPC_R23:
_registers.__r23 = value;
return;
case UNW_PPC_R24:
_registers.__r24 = value;
return;
case UNW_PPC_R25:
_registers.__r25 = value;
return;
case UNW_PPC_R26:
_registers.__r26 = value;
return;
case UNW_PPC_R27:
_registers.__r27 = value;
return;
case UNW_PPC_R28:
_registers.__r28 = value;
return;
case UNW_PPC_R29:
_registers.__r29 = value;
return;
case UNW_PPC_R30:
_registers.__r30 = value;
return;
case UNW_PPC_R31:
_registers.__r31 = value;
return;
case UNW_PPC_MQ:
_registers.__mq = value;
return;
case UNW_PPC_LR:
_registers.__lr = value;
return;
case UNW_PPC_CTR:
_registers.__ctr = value;
return;
case UNW_PPC_CR0:
_registers.__cr &= 0x0FFFFFFF;
_registers.__cr |= (value & 0xF0000000);
return;
case UNW_PPC_CR1:
_registers.__cr &= 0xF0FFFFFF;
_registers.__cr |= (value & 0x0F000000);
return;
case UNW_PPC_CR2:
_registers.__cr &= 0xFF0FFFFF;
_registers.__cr |= (value & 0x00F00000);
return;
case UNW_PPC_CR3:
_registers.__cr &= 0xFFF0FFFF;
_registers.__cr |= (value & 0x000F0000);
return;
case UNW_PPC_CR4:
_registers.__cr &= 0xFFFF0FFF;
_registers.__cr |= (value & 0x0000F000);
return;
case UNW_PPC_CR5:
_registers.__cr &= 0xFFFFF0FF;
_registers.__cr |= (value & 0x00000F00);
return;
case UNW_PPC_CR6:
_registers.__cr &= 0xFFFFFF0F;
_registers.__cr |= (value & 0x000000F0);
return;
case UNW_PPC_CR7:
_registers.__cr &= 0xFFFFFFF0;
_registers.__cr |= (value & 0x0000000F);
return;
case UNW_PPC_VRSAVE:
_registers.__vrsave = value;
return;
// not saved
return;
case UNW_PPC_XER:
_registers.__xer = value;
return;
case UNW_PPC_AP:
case UNW_PPC_VSCR:
case UNW_PPC_SPEFSCR:
// not saved
return;
}
_LIBUNWIND_ABORT("unsupported ppc register");
}
inline bool Registers_ppc::validFloatRegister(int regNum) const {
if (regNum < UNW_PPC_F0)
return false;
if (regNum > UNW_PPC_F31)
return false;
return true;
}
inline double Registers_ppc::getFloatRegister(int regNum) const {
assert(validFloatRegister(regNum));
return _floatRegisters.__fpregs[regNum - UNW_PPC_F0];
}
inline void Registers_ppc::setFloatRegister(int regNum, double value) {
assert(validFloatRegister(regNum));
_floatRegisters.__fpregs[regNum - UNW_PPC_F0] = value;
}
inline bool Registers_ppc::validVectorRegister(int regNum) const {