/
variable_elem_vec_extracts.ll
150 lines (146 loc) · 4.5 KB
/
variable_elem_vec_extracts.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -ppc-late-peephole=true < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-BE
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-P7
; Function Attrs: norecurse nounwind readnone
define signext i32 @geti(<4 x i32> %a, i32 signext %b) {
; CHECK-LABEL: geti:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li 3, 2
; CHECK-NEXT: andc 3, 3, 5
; CHECK-NEXT: sldi 3, 3, 2
; CHECK-NEXT: lvsl 3, 0, 3
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: vperm 2, 2, 2, 3
; CHECK-NEXT: sldi 3, 3, 5
; CHECK-NEXT: mfvsrd 4, 34
; CHECK-NEXT: srd 3, 4, 3
; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: geti:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: andi. 4, 5, 2
; CHECK-BE-NEXT: li 3, 1
; CHECK-BE-NEXT: sldi 4, 4, 2
; CHECK-BE-NEXT: andc 3, 3, 5
; CHECK-BE-NEXT: lvsl 3, 0, 4
; CHECK-BE-NEXT: sldi 3, 3, 5
; CHECK-BE-NEXT: vperm 2, 2, 2, 3
; CHECK-BE-NEXT: mfvsrd 4, 34
; CHECK-BE-NEXT: srd 3, 4, 3
; CHECK-BE-NEXT: extsw 3, 3
; CHECK-BE-NEXT: blr
;
; CHECK-P7-LABEL: geti:
; CHECK-P7: # %bb.0: # %entry
; CHECK-P7-NEXT: addi 3, 1, -16
; CHECK-P7-NEXT: rlwinm 4, 5, 2, 28, 29
; CHECK-P7-NEXT: stxvw4x 34, 0, 3
; CHECK-P7-NEXT: lwax 3, 3, 4
; CHECK-P7-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %a, i32 %b
ret i32 %vecext
}
; Function Attrs: norecurse nounwind readnone
define i64 @getl(<2 x i64> %a, i32 signext %b) {
; CHECK-LABEL: getl:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: andc 3, 3, 5
; CHECK-NEXT: sldi 3, 3, 3
; CHECK-NEXT: lvsl 3, 0, 3
; CHECK-NEXT: vperm 2, 2, 2, 3
; CHECK-NEXT: mfvsrd 3, 34
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: getl:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: andi. 3, 5, 1
; CHECK-BE-NEXT: sldi 3, 3, 3
; CHECK-BE-NEXT: lvsl 3, 0, 3
; CHECK-BE-NEXT: vperm 2, 2, 2, 3
; CHECK-BE-NEXT: mfvsrd 3, 34
; CHECK-BE-NEXT: blr
;
; CHECK-P7-LABEL: getl:
; CHECK-P7: # %bb.0: # %entry
; CHECK-P7-NEXT: addi 3, 1, -16
; CHECK-P7-NEXT: rlwinm 4, 5, 3, 28, 28
; CHECK-P7-NEXT: stxvd2x 34, 0, 3
; CHECK-P7-NEXT: ldx 3, 3, 4
; CHECK-P7-NEXT: blr
entry:
%vecext = extractelement <2 x i64> %a, i32 %b
ret i64 %vecext
}
; Function Attrs: norecurse nounwind readnone
define float @getf(<4 x float> %a, i32 signext %b) {
; CHECK-LABEL: getf:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xori 3, 5, 3
; CHECK-NEXT: sldi 3, 3, 2
; CHECK-NEXT: lvsl 3, 0, 3
; CHECK-NEXT: vperm 2, 2, 2, 3
; CHECK-NEXT: xscvspdpn 1, 34
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: getf:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sldi 3, 5, 2
; CHECK-BE-NEXT: lvsl 3, 0, 3
; CHECK-BE-NEXT: vperm 2, 2, 2, 3
; CHECK-BE-NEXT: xscvspdpn 1, 34
; CHECK-BE-NEXT: blr
;
; CHECK-P7-LABEL: getf:
; CHECK-P7: # %bb.0: # %entry
; CHECK-P7-NEXT: addi 3, 1, -16
; CHECK-P7-NEXT: rlwinm 4, 5, 2, 28, 29
; CHECK-P7-NEXT: stxvw4x 34, 0, 3
; CHECK-P7-NEXT: lfsx 1, 3, 4
; CHECK-P7-NEXT: blr
entry:
%vecext = extractelement <4 x float> %a, i32 %b
ret float %vecext
}
; Function Attrs: norecurse nounwind readnone
define double @getd(<2 x double> %a, i32 signext %b) {
; CHECK-LABEL: getd:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: andc 3, 3, 5
; CHECK-NEXT: sldi 3, 3, 3
; CHECK-NEXT: lvsl 3, 0, 3
; CHECK-NEXT: vperm 2, 2, 2, 3
; CHECK-NEXT: xxlor 1, 34, 34
; CHECK-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: getd:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: andi. 3, 5, 1
; CHECK-BE-NEXT: sldi 3, 3, 3
; CHECK-BE-NEXT: lvsl 3, 0, 3
; CHECK-BE-NEXT: vperm 2, 2, 2, 3
; CHECK-BE-NEXT: xxlor 1, 34, 34
; CHECK-BE-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; CHECK-BE-NEXT: blr
;
; CHECK-P7-LABEL: getd:
; CHECK-P7: # %bb.0: # %entry
; CHECK-P7-NEXT: andi. 3, 5, 1
; CHECK-P7-NEXT: sldi 3, 3, 3
; CHECK-P7-NEXT: lvsl 3, 0, 3
; CHECK-P7-NEXT: vperm 2, 2, 2, 3
; CHECK-P7-NEXT: xxlor 1, 34, 34
; CHECK-P7-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; CHECK-P7-NEXT: blr
entry:
%vecext = extractelement <2 x double> %a, i32 %b
ret double %vecext
}