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X86MCCodeEmitter.cpp
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X86MCCodeEmitter.cpp
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//===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file implements the X86MCCodeEmitter class.
//
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/X86BaseInfo.h"
#include "MCTargetDesc/X86FixupKinds.h"
#include "MCTargetDesc/X86MCTargetDesc.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCFixup.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include <cassert>
#include <cstdint>
#include <cstdlib>
using namespace llvm;
#define DEBUG_TYPE "mccodeemitter"
namespace {
enum PrefixKind { None, REX, XOP, VEX2, VEX3, EVEX };
static void emitByte(uint8_t C, raw_ostream &OS) { OS << static_cast<char>(C); }
class X86OpcodePrefixHelper {
// REX (1 byte)
// +-----+ +------+
// | 40H | | WRXB |
// +-----+ +------+
// XOP (3-byte)
// +-----+ +--------------+ +-------------------+
// | 8Fh | | RXB | m-mmmm | | W | vvvv | L | pp |
// +-----+ +--------------+ +-------------------+
// VEX2 (2 bytes)
// +-----+ +-------------------+
// | C5h | | R | vvvv | L | pp |
// +-----+ +-------------------+
// VEX3 (3 bytes)
// +-----+ +--------------+ +-------------------+
// | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
// +-----+ +--------------+ +-------------------+
// VEX_R: opcode externsion equivalent to REX.R in
// 1's complement (inverted) form
//
// 1: Same as REX_R=0 (must be 1 in 32-bit mode)
// 0: Same as REX_R=1 (64 bit mode only)
// VEX_X: equivalent to REX.X, only used when a
// register is used for index in SIB Byte.
//
// 1: Same as REX.X=0 (must be 1 in 32-bit mode)
// 0: Same as REX.X=1 (64-bit mode only)
// VEX_B:
// 1: Same as REX_B=0 (ignored in 32-bit mode)
// 0: Same as REX_B=1 (64 bit mode only)
// VEX_W: opcode specific (use like REX.W, or used for
// opcode extension, or ignored, depending on the opcode byte)
// VEX_5M (VEX m-mmmmm field):
//
// 0b00000: Reserved for future use
// 0b00001: implied 0F leading opcode
// 0b00010: implied 0F 38 leading opcode bytes
// 0b00011: implied 0F 3A leading opcode bytes
// 0b00100: Reserved for future use
// 0b00101: VEX MAP5
// 0b00110: VEX MAP6
// 0b00111-0b11111: Reserved for future use
// 0b01000: XOP map select - 08h instructions with imm byte
// 0b01001: XOP map select - 09h instructions with no imm byte
// 0b01010: XOP map select - 0Ah instructions with imm dword
// VEX_4V (VEX vvvv field): a register specifier
// (in 1's complement form) or 1111 if unused.
// VEX_PP: opcode extension providing equivalent
// functionality of a SIMD prefix
// 0b00: None
// 0b01: 66
// 0b10: F3
// 0b11: F2
// EVEX (4 bytes)
// +-----+ +--------------+ +-------------------+ +------------------------+
// | 62h | | RXBR' | 00mm | | W | vvvv | 1 | pp | | z | L'L | b | v' | aaa |
// +-----+ +--------------+ +-------------------+ +------------------------+
// EVEX_L2/VEX_L (Vector Length):
// L2 L
// 0 0: scalar or 128-bit vector
// 0 1: 256-bit vector
// 1 0: 512-bit vector
private:
unsigned W : 1;
unsigned R : 1;
unsigned X : 1;
unsigned B : 1;
unsigned VEX_4V : 4;
unsigned VEX_L : 1;
unsigned VEX_PP : 2;
unsigned VEX_5M : 5;
unsigned EVEX_R2 : 1;
unsigned EVEX_z : 1;
unsigned EVEX_L2 : 1;
unsigned EVEX_b : 1;
unsigned EVEX_V2 : 1;
unsigned EVEX_aaa : 3;
PrefixKind Kind = None;
const MCRegisterInfo &MRI;
unsigned getRegEncoding(const MCInst &MI, unsigned OpNum) const {
return MRI.getEncodingValue(MI.getOperand(OpNum).getReg());
}
void setR(unsigned Encoding) { R = Encoding >> 3 & 1; }
void setR2(unsigned Encoding) { EVEX_R2 = Encoding >> 4 & 1; }
void set4V(unsigned Encoding) { VEX_4V = Encoding & 0xf; }
void setV2(unsigned Encoding) { EVEX_V2 = Encoding >> 4 & 1; }
public:
void setW(bool V) { W = V; }
void setR(const MCInst &MI, unsigned OpNum) {
setR(getRegEncoding(MI, OpNum));
}
void setX(const MCInst &MI, unsigned OpNum, unsigned Shift = 3) {
X = getRegEncoding(MI, OpNum) >> Shift & 1;
}
void setB(const MCInst &MI, unsigned OpNum) {
B = getRegEncoding(MI, OpNum) >> 3 & 1;
}
void set4V(const MCInst &MI, unsigned OpNum) {
set4V(getRegEncoding(MI, OpNum));
}
void setL(bool V) { VEX_L = V; }
void setPP(unsigned V) { VEX_PP = V; }
void set5M(unsigned V) { VEX_5M = V; }
void setR2(const MCInst &MI, unsigned OpNum) {
setR2(getRegEncoding(MI, OpNum));
}
void setRR2(const MCInst &MI, unsigned OpNum) {
unsigned Encoding = getRegEncoding(MI, OpNum);
setR(Encoding);
setR2(Encoding);
}
void setZ(bool V) { EVEX_z = V; }
void setL2(bool V) { EVEX_L2 = V; }
void setEVEX_b(bool V) { EVEX_b = V; }
void setV2(const MCInst &MI, unsigned OpNum) {
setV2(getRegEncoding(MI, OpNum));
}
void set4VV2(const MCInst &MI, unsigned OpNum) {
unsigned Encoding = getRegEncoding(MI, OpNum);
set4V(Encoding);
setV2(Encoding);
}
void setAAA(const MCInst &MI, unsigned OpNum) {
EVEX_aaa = getRegEncoding(MI, OpNum);
}
X86OpcodePrefixHelper(const MCRegisterInfo &MRI)
: W(0), R(0), X(0), B(0), VEX_4V(0), VEX_L(0), VEX_PP(0), VEX_5M(0),
EVEX_R2(0), EVEX_z(0), EVEX_L2(0), EVEX_b(0), EVEX_V2(0), EVEX_aaa(0),
MRI(MRI) {}
void setLowerBound(PrefixKind K) { Kind = K; }
PrefixKind determineOptimalKind() {
switch (Kind) {
case None:
Kind = (W | R | X | B) ? REX : None;
break;
case REX:
case XOP:
case VEX3:
case EVEX:
break;
case VEX2:
Kind = (W | X | B | (VEX_5M != 1)) ? VEX3 : VEX2;
break;
}
return Kind;
}
void emit(raw_ostream &OS) const {
uint8_t FirstPayload =
((~R) & 0x1) << 7 | ((~X) & 0x1) << 6 | ((~B) & 0x1) << 5;
uint8_t LastPayload = ((~VEX_4V) & 0xf) << 3 | VEX_L << 2 | VEX_PP;
switch (Kind) {
case None:
return;
case REX:
emitByte(0x40 | W << 3 | R << 2 | X << 1 | B, OS);
return;
case VEX2:
emitByte(0xC5, OS);
emitByte(((~R) & 1) << 7 | LastPayload, OS);
return;
case VEX3:
case XOP:
emitByte(Kind == VEX3 ? 0xC4 : 0x8F, OS);
emitByte(FirstPayload | VEX_5M, OS);
emitByte(W << 7 | LastPayload, OS);
return;
case EVEX:
assert(VEX_5M & 0x7 &&
"More than 3 significant bits in VEX.m-mmmm fields for EVEX!");
emitByte(0x62, OS);
emitByte(FirstPayload | ((~EVEX_R2) & 0x1) << 4 | VEX_5M, OS);
emitByte(W << 7 | ((~VEX_4V) & 0xf) << 3 | 1 << 2 | VEX_PP, OS);
emitByte(EVEX_z << 7 | EVEX_L2 << 6 | VEX_L << 5 | EVEX_b << 4 |
((~EVEX_V2) & 0x1) << 3 | EVEX_aaa,
OS);
return;
}
}
};
class X86MCCodeEmitter : public MCCodeEmitter {
const MCInstrInfo &MCII;
MCContext &Ctx;
public:
X86MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
: MCII(mcii), Ctx(ctx) {}
X86MCCodeEmitter(const X86MCCodeEmitter &) = delete;
X86MCCodeEmitter &operator=(const X86MCCodeEmitter &) = delete;
~X86MCCodeEmitter() override = default;
void emitPrefix(const MCInst &MI, raw_ostream &OS,
const MCSubtargetInfo &STI) const override;
void encodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override;
private:
unsigned getX86RegNum(const MCOperand &MO) const;
unsigned getX86RegEncoding(const MCInst &MI, unsigned OpNum) const;
void emitImmediate(const MCOperand &Disp, SMLoc Loc, unsigned ImmSize,
MCFixupKind FixupKind, uint64_t StartByte, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups, int ImmOffset = 0) const;
void emitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
raw_ostream &OS) const;
void emitSIBByte(unsigned SS, unsigned Index, unsigned Base,
raw_ostream &OS) const;
void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField,
uint64_t TSFlags, PrefixKind Kind, uint64_t StartByte,
raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI,
bool ForceSIB = false) const;
PrefixKind emitPrefixImpl(unsigned &CurOp, const MCInst &MI,
const MCSubtargetInfo &STI, raw_ostream &OS) const;
PrefixKind emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
raw_ostream &OS) const;
void emitSegmentOverridePrefix(unsigned SegOperand, const MCInst &MI,
raw_ostream &OS) const;
PrefixKind emitOpcodePrefix(int MemOperand, const MCInst &MI,
const MCSubtargetInfo &STI,
raw_ostream &OS) const;
PrefixKind emitREXPrefix(int MemOperand, const MCInst &MI,
const MCSubtargetInfo &STI, raw_ostream &OS) const;
};
} // end anonymous namespace
static uint8_t modRMByte(unsigned Mod, unsigned RegOpcode, unsigned RM) {
assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
return RM | (RegOpcode << 3) | (Mod << 6);
}
static void emitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) {
// Output the constant in little endian byte order.
for (unsigned i = 0; i != Size; ++i) {
emitByte(Val & 255, OS);
Val >>= 8;
}
}
/// Determine if this immediate can fit in a disp8 or a compressed disp8 for
/// EVEX instructions. \p will be set to the value to pass to the ImmOffset
/// parameter of emitImmediate.
static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset) {
bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
int CD8_Scale =
(TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift;
if (!HasEVEX || CD8_Scale == 0)
return isInt<8>(Value);
assert(isPowerOf2_32(CD8_Scale) && "Unexpected CD8 scale!");
if (Value & (CD8_Scale - 1)) // Unaligned offset
return false;
int CDisp8 = Value / CD8_Scale;
if (!isInt<8>(CDisp8))
return false;
// ImmOffset will be added to Value in emitImmediate leaving just CDisp8.
ImmOffset = CDisp8 - Value;
return true;
}
/// \returns the appropriate fixup kind to use for an immediate in an
/// instruction with the specified TSFlags.
static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
unsigned Size = X86II::getSizeOfImm(TSFlags);
bool isPCRel = X86II::isImmPCRel(TSFlags);
if (X86II::isImmSigned(TSFlags)) {
switch (Size) {
default:
llvm_unreachable("Unsupported signed fixup size!");
case 4:
return MCFixupKind(X86::reloc_signed_4byte);
}
}
return MCFixup::getKindForSize(Size, isPCRel);
}
enum GlobalOffsetTableExprKind { GOT_None, GOT_Normal, GOT_SymDiff };
/// Check if this expression starts with _GLOBAL_OFFSET_TABLE_ and if it is
/// of the form _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on
/// ELF i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that
/// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start of a
/// binary expression.
static GlobalOffsetTableExprKind
startsWithGlobalOffsetTable(const MCExpr *Expr) {
const MCExpr *RHS = nullptr;
if (Expr->getKind() == MCExpr::Binary) {
const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
Expr = BE->getLHS();
RHS = BE->getRHS();
}
if (Expr->getKind() != MCExpr::SymbolRef)
return GOT_None;
const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
const MCSymbol &S = Ref->getSymbol();
if (S.getName() != "_GLOBAL_OFFSET_TABLE_")
return GOT_None;
if (RHS && RHS->getKind() == MCExpr::SymbolRef)
return GOT_SymDiff;
return GOT_Normal;
}
static bool hasSecRelSymbolRef(const MCExpr *Expr) {
if (Expr->getKind() == MCExpr::SymbolRef) {
const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
return Ref->getKind() == MCSymbolRefExpr::VK_SECREL;
}
return false;
}
static bool isPCRel32Branch(const MCInst &MI, const MCInstrInfo &MCII) {
unsigned Opcode = MI.getOpcode();
const MCInstrDesc &Desc = MCII.get(Opcode);
if ((Opcode != X86::CALL64pcrel32 && Opcode != X86::JMP_4 &&
Opcode != X86::JCC_4) ||
getImmFixupKind(Desc.TSFlags) != FK_PCRel_4)
return false;
unsigned CurOp = X86II::getOperandBias(Desc);
const MCOperand &Op = MI.getOperand(CurOp);
if (!Op.isExpr())
return false;
const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(Op.getExpr());
return Ref && Ref->getKind() == MCSymbolRefExpr::VK_None;
}
unsigned X86MCCodeEmitter::getX86RegNum(const MCOperand &MO) const {
return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
}
unsigned X86MCCodeEmitter::getX86RegEncoding(const MCInst &MI,
unsigned OpNum) const {
return Ctx.getRegisterInfo()->getEncodingValue(MI.getOperand(OpNum).getReg());
}
void X86MCCodeEmitter::emitImmediate(const MCOperand &DispOp, SMLoc Loc,
unsigned Size, MCFixupKind FixupKind,
uint64_t StartByte, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
int ImmOffset) const {
const MCExpr *Expr = nullptr;
if (DispOp.isImm()) {
// If this is a simple integer displacement that doesn't require a
// relocation, emit it now.
if (FixupKind != FK_PCRel_1 && FixupKind != FK_PCRel_2 &&
FixupKind != FK_PCRel_4) {
emitConstant(DispOp.getImm() + ImmOffset, Size, OS);
return;
}
Expr = MCConstantExpr::create(DispOp.getImm(), Ctx);
} else {
Expr = DispOp.getExpr();
}
// If we have an immoffset, add it to the expression.
if ((FixupKind == FK_Data_4 || FixupKind == FK_Data_8 ||
FixupKind == MCFixupKind(X86::reloc_signed_4byte))) {
GlobalOffsetTableExprKind Kind = startsWithGlobalOffsetTable(Expr);
if (Kind != GOT_None) {
assert(ImmOffset == 0);
if (Size == 8) {
FixupKind = MCFixupKind(X86::reloc_global_offset_table8);
} else {
assert(Size == 4);
FixupKind = MCFixupKind(X86::reloc_global_offset_table);
}
if (Kind == GOT_Normal)
ImmOffset = static_cast<int>(OS.tell() - StartByte);
} else if (Expr->getKind() == MCExpr::SymbolRef) {
if (hasSecRelSymbolRef(Expr)) {
FixupKind = MCFixupKind(FK_SecRel_4);
}
} else if (Expr->getKind() == MCExpr::Binary) {
const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr *>(Expr);
if (hasSecRelSymbolRef(Bin->getLHS()) ||
hasSecRelSymbolRef(Bin->getRHS())) {
FixupKind = MCFixupKind(FK_SecRel_4);
}
}
}
// If the fixup is pc-relative, we need to bias the value to be relative to
// the start of the field, not the end of the field.
if (FixupKind == FK_PCRel_4 ||
FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load) ||
FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax) ||
FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax_rex) ||
FixupKind == MCFixupKind(X86::reloc_branch_4byte_pcrel)) {
ImmOffset -= 4;
// If this is a pc-relative load off _GLOBAL_OFFSET_TABLE_:
// leaq _GLOBAL_OFFSET_TABLE_(%rip), %r15
// this needs to be a GOTPC32 relocation.
if (startsWithGlobalOffsetTable(Expr) != GOT_None)
FixupKind = MCFixupKind(X86::reloc_global_offset_table);
}
if (FixupKind == FK_PCRel_2)
ImmOffset -= 2;
if (FixupKind == FK_PCRel_1)
ImmOffset -= 1;
if (ImmOffset)
Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(ImmOffset, Ctx),
Ctx);
// Emit a symbolic constant as a fixup and 4 zeros.
Fixups.push_back(MCFixup::create(static_cast<uint32_t>(OS.tell() - StartByte),
Expr, FixupKind, Loc));
emitConstant(0, Size, OS);
}
void X86MCCodeEmitter::emitRegModRMByte(const MCOperand &ModRMReg,
unsigned RegOpcodeFld,
raw_ostream &OS) const {
emitByte(modRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)), OS);
}
void X86MCCodeEmitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base,
raw_ostream &OS) const {
// SIB byte is in the same format as the modRMByte.
emitByte(modRMByte(SS, Index, Base), OS);
}
void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op,
unsigned RegOpcodeField,
uint64_t TSFlags, PrefixKind Kind,
uint64_t StartByte, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI,
bool ForceSIB) const {
const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp);
const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg);
const MCOperand &Scale = MI.getOperand(Op + X86::AddrScaleAmt);
const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg);
unsigned BaseReg = Base.getReg();
// Handle %rip relative addressing.
if (BaseReg == X86::RIP ||
BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode
assert(STI.hasFeature(X86::Is64Bit) &&
"Rip-relative addressing requires 64-bit mode");
assert(IndexReg.getReg() == 0 && !ForceSIB &&
"Invalid rip-relative address");
emitByte(modRMByte(0, RegOpcodeField, 5), OS);
unsigned Opcode = MI.getOpcode();
unsigned FixupKind = [&]() {
// Enable relaxed relocation only for a MCSymbolRefExpr. We cannot use a
// relaxed relocation if an offset is present (e.g. x@GOTPCREL+4).
if (!(Disp.isExpr() && isa<MCSymbolRefExpr>(Disp.getExpr())))
return X86::reloc_riprel_4byte;
// Certain loads for GOT references can be relocated against the symbol
// directly if the symbol ends up in the same linkage unit.
switch (Opcode) {
default:
return X86::reloc_riprel_4byte;
case X86::MOV64rm:
// movq loads is a subset of reloc_riprel_4byte_relax_rex. It is a
// special case because COFF and Mach-O don't support ELF's more
// flexible R_X86_64_REX_GOTPCRELX relaxation.
assert(Kind == REX);
return X86::reloc_riprel_4byte_movq_load;
case X86::ADC32rm:
case X86::ADD32rm:
case X86::AND32rm:
case X86::CMP32rm:
case X86::MOV32rm:
case X86::OR32rm:
case X86::SBB32rm:
case X86::SUB32rm:
case X86::TEST32mr:
case X86::XOR32rm:
case X86::CALL64m:
case X86::JMP64m:
case X86::TAILJMPm64:
case X86::TEST64mr:
case X86::ADC64rm:
case X86::ADD64rm:
case X86::AND64rm:
case X86::CMP64rm:
case X86::OR64rm:
case X86::SBB64rm:
case X86::SUB64rm:
case X86::XOR64rm:
return Kind == REX ? X86::reloc_riprel_4byte_relax_rex
: X86::reloc_riprel_4byte_relax;
}
}();
// rip-relative addressing is actually relative to the *next* instruction.
// Since an immediate can follow the mod/rm byte for an instruction, this
// means that we need to bias the displacement field of the instruction with
// the size of the immediate field. If we have this case, add it into the
// expression to emit.
// Note: rip-relative addressing using immediate displacement values should
// not be adjusted, assuming it was the user's intent.
int ImmSize = !Disp.isImm() && X86II::hasImm(TSFlags)
? X86II::getSizeOfImm(TSFlags)
: 0;
emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), StartByte, OS,
Fixups, -ImmSize);
return;
}
unsigned BaseRegNo = BaseReg ? getX86RegNum(Base) : -1U;
// 16-bit addressing forms of the ModR/M byte have a different encoding for
// the R/M field and are far more limited in which registers can be used.
if (X86_MC::is16BitMemOperand(MI, Op, STI)) {
if (BaseReg) {
// For 32-bit addressing, the row and column values in Table 2-2 are
// basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with
// some special cases. And getX86RegNum reflects that numbering.
// For 16-bit addressing it's more fun, as shown in the SDM Vol 2A,
// Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only
// use SI/DI/BP/BX, which have "row" values 4-7 in no particular order,
// while values 0-3 indicate the allowed combinations (base+index) of
// those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI.
//
// R16Table[] is a lookup from the normal RegNo, to the row values from
// Table 2-1 for 16-bit addressing modes. Where zero means disallowed.
static const unsigned R16Table[] = {0, 0, 0, 7, 0, 6, 4, 5};
unsigned RMfield = R16Table[BaseRegNo];
assert(RMfield && "invalid 16-bit base register");
if (IndexReg.getReg()) {
unsigned IndexReg16 = R16Table[getX86RegNum(IndexReg)];
assert(IndexReg16 && "invalid 16-bit index register");
// We must have one of SI/DI (4,5), and one of BP/BX (6,7).
assert(((IndexReg16 ^ RMfield) & 2) &&
"invalid 16-bit base/index register combination");
assert(Scale.getImm() == 1 &&
"invalid scale for 16-bit memory reference");
// Allow base/index to appear in either order (although GAS doesn't).
if (IndexReg16 & 2)
RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
else
RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
}
if (Disp.isImm() && isInt<8>(Disp.getImm())) {
if (Disp.getImm() == 0 && RMfield != 6) {
// There is no displacement; just the register.
emitByte(modRMByte(0, RegOpcodeField, RMfield), OS);
return;
}
// Use the [REG]+disp8 form, including for [BP] which cannot be encoded.
emitByte(modRMByte(1, RegOpcodeField, RMfield), OS);
emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, OS, Fixups);
return;
}
// This is the [REG]+disp16 case.
emitByte(modRMByte(2, RegOpcodeField, RMfield), OS);
} else {
assert(IndexReg.getReg() == 0 && "Unexpected index register!");
// There is no BaseReg; this is the plain [disp16] case.
emitByte(modRMByte(0, RegOpcodeField, 6), OS);
}
// Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases.
emitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, StartByte, OS, Fixups);
return;
}
// Check for presence of {disp8} or {disp32} pseudo prefixes.
bool UseDisp8 = MI.getFlags() & X86::IP_USE_DISP8;
bool UseDisp32 = MI.getFlags() & X86::IP_USE_DISP32;
// We only allow no displacement if no pseudo prefix is present.
bool AllowNoDisp = !UseDisp8 && !UseDisp32;
// Disp8 is allowed unless the {disp32} prefix is present.
bool AllowDisp8 = !UseDisp32;
// Determine whether a SIB byte is needed.
if (// The SIB byte must be used if there is an index register or the
// encoding requires a SIB byte.
!ForceSIB && IndexReg.getReg() == 0 &&
// The SIB byte must be used if the base is ESP/RSP/R12, all of which
// encode to an R/M value of 4, which indicates that a SIB byte is
// present.
BaseRegNo != N86::ESP &&
// If there is no base register and we're in 64-bit mode, we need a SIB
// byte to emit an addr that is just 'disp32' (the non-RIP relative form).
(!STI.hasFeature(X86::Is64Bit) || BaseReg != 0)) {
if (BaseReg == 0) { // [disp32] in X86-32 mode
emitByte(modRMByte(0, RegOpcodeField, 5), OS);
emitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, StartByte, OS, Fixups);
return;
}
// If the base is not EBP/ESP/R12/R13 and there is no displacement, use
// simple indirect register encoding, this handles addresses like [EAX].
// The encoding for [EBP] or[R13] with no displacement means [disp32] so we
// handle it by emitting a displacement of 0 later.
if (BaseRegNo != N86::EBP) {
if (Disp.isImm() && Disp.getImm() == 0 && AllowNoDisp) {
emitByte(modRMByte(0, RegOpcodeField, BaseRegNo), OS);
return;
}
// If the displacement is @tlscall, treat it as a zero.
if (Disp.isExpr()) {
auto *Sym = dyn_cast<MCSymbolRefExpr>(Disp.getExpr());
if (Sym && Sym->getKind() == MCSymbolRefExpr::VK_TLSCALL) {
// This is exclusively used by call *a@tlscall(base). The relocation
// (R_386_TLSCALL or R_X86_64_TLSCALL) applies to the beginning.
Fixups.push_back(MCFixup::create(0, Sym, FK_NONE, MI.getLoc()));
emitByte(modRMByte(0, RegOpcodeField, BaseRegNo), OS);
return;
}
}
}
// Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
// Including a compressed disp8 for EVEX instructions that support it.
// This also handles the 0 displacement for [EBP] or [R13]. We can't use
// disp8 if the {disp32} pseudo prefix is present.
if (Disp.isImm() && AllowDisp8) {
int ImmOffset = 0;
if (isDispOrCDisp8(TSFlags, Disp.getImm(), ImmOffset)) {
emitByte(modRMByte(1, RegOpcodeField, BaseRegNo), OS);
emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, OS, Fixups,
ImmOffset);
return;
}
}
// Otherwise, emit the most general non-SIB encoding: [REG+disp32].
// Displacement may be 0 for [EBP] or [R13] case if {disp32} pseudo prefix
// prevented using disp8 above.
emitByte(modRMByte(2, RegOpcodeField, BaseRegNo), OS);
unsigned Opcode = MI.getOpcode();
unsigned FixupKind = Opcode == X86::MOV32rm ? X86::reloc_signed_4byte_relax
: X86::reloc_signed_4byte;
emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), StartByte, OS,
Fixups);
return;
}
// We need a SIB byte, so start by outputting the ModR/M byte first
assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP &&
"Cannot use ESP as index reg!");
bool ForceDisp32 = false;
bool ForceDisp8 = false;
int ImmOffset = 0;
if (BaseReg == 0) {
// If there is no base register, we emit the special case SIB byte with
// MOD=0, BASE=5, to JUST get the index, scale, and displacement.
BaseRegNo = 5;
emitByte(modRMByte(0, RegOpcodeField, 4), OS);
ForceDisp32 = true;
} else if (Disp.isImm() && Disp.getImm() == 0 && AllowNoDisp &&
// Base reg can't be EBP/RBP/R13 as that would end up with '5' as
// the base field, but that is the magic [*] nomenclature that
// indicates no base when mod=0. For these cases we'll emit a 0
// displacement instead.
BaseRegNo != N86::EBP) {
// Emit no displacement ModR/M byte
emitByte(modRMByte(0, RegOpcodeField, 4), OS);
} else if (Disp.isImm() && AllowDisp8 &&
isDispOrCDisp8(TSFlags, Disp.getImm(), ImmOffset)) {
// Displacement fits in a byte or matches an EVEX compressed disp8, use
// disp8 encoding. This also handles EBP/R13 base with 0 displacement unless
// {disp32} pseudo prefix was used.
emitByte(modRMByte(1, RegOpcodeField, 4), OS);
ForceDisp8 = true;
} else {
// Otherwise, emit the normal disp32 encoding.
emitByte(modRMByte(2, RegOpcodeField, 4), OS);
ForceDisp32 = true;
}
// Calculate what the SS field value should be...
static const unsigned SSTable[] = {~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3};
unsigned SS = SSTable[Scale.getImm()];
unsigned IndexRegNo = IndexReg.getReg() ? getX86RegNum(IndexReg) : 4;
emitSIBByte(SS, IndexRegNo, BaseRegNo, OS);
// Do we need to output a displacement?
if (ForceDisp8)
emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, OS, Fixups,
ImmOffset);
else if (ForceDisp32)
emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
StartByte, OS, Fixups);
}
/// Emit all instruction prefixes.
///
/// \returns one of the REX, XOP, VEX2, VEX3, EVEX if any of them is used,
/// otherwise returns None.
PrefixKind X86MCCodeEmitter::emitPrefixImpl(unsigned &CurOp, const MCInst &MI,
const MCSubtargetInfo &STI,
raw_ostream &OS) const {
uint64_t TSFlags = MCII.get(MI.getOpcode()).TSFlags;
// Determine where the memory operand starts, if present.
int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
// Emit segment override opcode prefix as needed.
if (MemoryOperand != -1) {
MemoryOperand += CurOp;
emitSegmentOverridePrefix(MemoryOperand + X86::AddrSegmentReg, MI, OS);
}
// Emit the repeat opcode prefix as needed.
unsigned Flags = MI.getFlags();
if (TSFlags & X86II::REP || Flags & X86::IP_HAS_REPEAT)
emitByte(0xF3, OS);
if (Flags & X86::IP_HAS_REPEAT_NE)
emitByte(0xF2, OS);
// Emit the address size opcode prefix as needed.
if (X86_MC::needsAddressSizeOverride(MI, STI, MemoryOperand, TSFlags) ||
Flags & X86::IP_HAS_AD_SIZE)
emitByte(0x67, OS);
uint64_t Form = TSFlags & X86II::FormMask;
switch (Form) {
default:
break;
case X86II::RawFrmDstSrc: {
// Emit segment override opcode prefix as needed (not for %ds).
if (MI.getOperand(2).getReg() != X86::DS)
emitSegmentOverridePrefix(2, MI, OS);
CurOp += 3; // Consume operands.
break;
}
case X86II::RawFrmSrc: {
// Emit segment override opcode prefix as needed (not for %ds).
if (MI.getOperand(1).getReg() != X86::DS)
emitSegmentOverridePrefix(1, MI, OS);
CurOp += 2; // Consume operands.
break;
}
case X86II::RawFrmDst: {
++CurOp; // Consume operand.
break;
}
case X86II::RawFrmMemOffs: {
// Emit segment override opcode prefix as needed.
emitSegmentOverridePrefix(1, MI, OS);
break;
}
}
// REX prefix is optional, but if used must be immediately before the opcode
// Encoding type for this instruction.
return (TSFlags & X86II::EncodingMask)
? emitVEXOpcodePrefix(MemoryOperand, MI, OS)
: emitOpcodePrefix(MemoryOperand, MI, STI, OS);
}
// AVX instructions are encoded using an encoding scheme that combines
// prefix bytes, opcode extension field, operand encoding fields, and vector
// length encoding capability into a new prefix, referred to as VEX.
// The majority of the AVX-512 family of instructions (operating on
// 512/256/128-bit vector register operands) are encoded using a new prefix
// (called EVEX).
// XOP is a revised subset of what was originally intended as SSE5. It was
// changed to be similar but not overlapping with AVX.
/// Emit XOP, VEX2, VEX3 or EVEX prefix.
/// \returns the used prefix.
PrefixKind X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand,
const MCInst &MI,
raw_ostream &OS) const {
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
uint64_t TSFlags = Desc.TSFlags;
assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX.");
X86OpcodePrefixHelper Prefix(*Ctx.getRegisterInfo());
switch (TSFlags & X86II::EncodingMask) {
default:
break;
case X86II::XOP:
Prefix.setLowerBound(XOP);
break;
case X86II::VEX:
// VEX can be 2 byte or 3 byte, not determined yet if not explicit
Prefix.setLowerBound(MI.getFlags() & X86::IP_USE_VEX3 ? VEX3 : VEX2);
break;
case X86II::EVEX:
Prefix.setLowerBound(EVEX);
break;
}
Prefix.setW(TSFlags & X86II::VEX_W);
bool HasEVEX_K = TSFlags & X86II::EVEX_K;
bool HasVEX_4V = TSFlags & X86II::VEX_4V;
bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
switch (TSFlags & X86II::OpMapMask) {
default:
llvm_unreachable("Invalid prefix!");
case X86II::TB:
Prefix.set5M(0x1); // 0F
break;
case X86II::T8:
Prefix.set5M(0x2); // 0F 38
break;
case X86II::TA:
Prefix.set5M(0x3); // 0F 3A
break;
case X86II::XOP8:
Prefix.set5M(0x8);
break;
case X86II::XOP9:
Prefix.set5M(0x9);
break;
case X86II::XOPA:
Prefix.set5M(0xA);
break;
case X86II::T_MAP5:
Prefix.set5M(0x5);
break;
case X86II::T_MAP6:
Prefix.set5M(0x6);
break;
}
Prefix.setL(TSFlags & X86II::VEX_L);
Prefix.setL2(TSFlags & X86II::EVEX_L2);
switch (TSFlags & X86II::OpPrefixMask) {
case X86II::PD:
Prefix.setPP(0x1); // 66
break;
case X86II::XS:
Prefix.setPP(0x2); // F3
break;
case X86II::XD:
Prefix.setPP(0x3); // F2
break;
}
Prefix.setZ(HasEVEX_K && (TSFlags & X86II::EVEX_Z));
Prefix.setEVEX_b(TSFlags & X86II::EVEX_B);
bool EncodeRC = false;
uint8_t EVEX_rc = 0;
unsigned CurOp = X86II::getOperandBias(Desc);
switch (TSFlags & X86II::FormMask) {
default:
llvm_unreachable("Unexpected form in emitVEXOpcodePrefix!");
case X86II::MRMDestMem4VOp3CC: {
// MemAddr, src1(ModR/M), src2(VEX_4V)
Prefix.setB(MI, MemOperand + X86::AddrBaseReg);
Prefix.setX(MI, MemOperand + X86::AddrIndexReg);
CurOp += X86::AddrNumOperands;
Prefix.setR(MI, ++CurOp);
Prefix.set4V(MI, CurOp++);
break;
}
case X86II::MRM_C0:
case X86II::RawFrm:
case X86II::PrefixByte:
break;
case X86II::MRMDestMemFSIB:
case X86II::MRMDestMem: {
// MRMDestMem instructions forms:
// MemAddr, src1(ModR/M)
// MemAddr, src1(VEX_4V), src2(ModR/M)
// MemAddr, src1(ModR/M), imm8
//
Prefix.setB(MI, MemOperand + X86::AddrBaseReg);
Prefix.setX(MI, MemOperand + X86::AddrIndexReg);
if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV.
Prefix.setV2(MI, MemOperand + X86::AddrIndexReg);
CurOp += X86::AddrNumOperands;
if (HasEVEX_K)
Prefix.setAAA(MI, CurOp++);
if (HasVEX_4V)
Prefix.set4VV2(MI, CurOp++);
Prefix.setRR2(MI, CurOp++);
break;
}
case X86II::MRMSrcMemFSIB:
case X86II::MRMSrcMem: {
// MRMSrcMem instructions forms:
// src1(ModR/M), MemAddr
// src1(ModR/M), src2(VEX_4V), MemAddr
// src1(ModR/M), MemAddr, imm8
// src1(ModR/M), MemAddr, src2(Imm[7:4])
//
// FMA4:
// dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4])
Prefix.setRR2(MI, CurOp++);
if (HasEVEX_K)
Prefix.setAAA(MI, CurOp++);
if (HasVEX_4V)
Prefix.set4VV2(MI, CurOp++);
Prefix.setB(MI, MemOperand + X86::AddrBaseReg);
Prefix.setX(MI, MemOperand + X86::AddrIndexReg);
if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV.
Prefix.setV2(MI, MemOperand + X86::AddrIndexReg);
break;