/
AMDGPU.td
1501 lines (1249 loc) · 44.3 KB
/
AMDGPU.td
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===------------------------------------------------------------===//
include "llvm/TableGen/SearchableTable.td"
include "llvm/Target/Target.td"
include "AMDGPUFeatures.td"
def p0 : PtrValueType<i64, 0>;
def p1 : PtrValueType<i64, 1>;
def p2 : PtrValueType<i32, 2>;
def p3 : PtrValueType<i32, 3>;
def p4 : PtrValueType<i64, 4>;
def p5 : PtrValueType<i32, 5>;
def p6 : PtrValueType<i32, 6>;
class BoolToList<bit Value> {
list<int> ret = !if(Value, [1]<int>, []<int>);
}
//===------------------------------------------------------------===//
// Subtarget Features (device properties)
//===------------------------------------------------------------===//
def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
"FastFMAF32",
"true",
"Assuming f32 fma is at least as fast as mul + add"
>;
def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
"FastDenormalF32",
"true",
"Enabling denormals does not cause f32 instructions to run at f64 rates"
>;
def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
"MIMG_R128",
"true",
"Support 128-bit texture resources"
>;
def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
"HalfRate64Ops",
"true",
"Most fp64 instructions are half rate instead of quarter"
>;
def FullRate64Ops : SubtargetFeature<"full-rate-64-ops",
"FullRate64Ops",
"true",
"Most fp64 instructions are full rate"
>;
def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
"FlatAddressSpace",
"true",
"Support flat address space"
>;
def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
"FlatInstOffsets",
"true",
"Flat instructions have immediate offset addressing mode"
>;
def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
"FlatGlobalInsts",
"true",
"Have global_* flat memory instructions"
>;
def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
"FlatScratchInsts",
"true",
"Have scratch_* flat memory instructions"
>;
def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
"ScalarFlatScratchInsts",
"true",
"Have s_scratch_* flat memory instructions"
>;
def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
"AddNoCarryInsts",
"true",
"Have VALU add/sub instructions without carry out"
>;
def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
"UnalignedBufferAccess",
"true",
"Hardware supports unaligned global loads and stores"
>;
def FeatureTrapHandler: SubtargetFeature<"trap-handler",
"TrapHandler",
"true",
"Trap handler support"
>;
def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
"UnalignedScratchAccess",
"true",
"Support unaligned scratch loads and stores"
>;
def FeatureUnalignedDSAccess : SubtargetFeature<"unaligned-ds-access",
"UnalignedDSAccess",
"true",
"Hardware supports unaligned local and region loads and stores"
>;
def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
"HasApertureRegs",
"true",
"Has Memory Aperture Base and Size Registers"
>;
def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
"HasMadMixInsts",
"true",
"Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
>;
def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
"HasFmaMixInsts",
"true",
"Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
>;
def FeatureSupportsXNACK : SubtargetFeature<"xnack-support",
"SupportsXNACK",
"true",
"Hardware supports XNACK"
>;
// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
// XNACK. The current default kernel driver setting is:
// - graphics ring: XNACK disabled
// - compute ring: XNACK enabled
//
// If XNACK is enabled, the VMEM latency can be worse.
// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
def FeatureXNACK : SubtargetFeature<"xnack",
"EnableXNACK",
"true",
"Enable XNACK support"
>;
def FeatureTgSplit : SubtargetFeature<"tgsplit",
"EnableTgSplit",
"true",
"Enable threadgroup split execution"
>;
def FeatureCuMode : SubtargetFeature<"cumode",
"EnableCuMode",
"true",
"Enable CU wavefront execution mode"
>;
def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
"SGPRInitBug",
"true",
"VI SGPR initialization bug requiring a fixed SGPR allocation size"
>;
def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
"LDSMisalignedBug",
"true",
"Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode"
>;
def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
"HasMFMAInlineLiteralBug",
"true",
"MFMA cannot use inline literal as SrcC"
>;
def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
"HasVcmpxPermlaneHazard",
"true",
"TODO: describe me"
>;
def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
"HasVMEMtoScalarWriteHazard",
"true",
"VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
>;
def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
"HasSMEMtoVectorWriteHazard",
"true",
"s_load_dword followed by v_cmp page faults"
>;
def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
"HasInstFwdPrefetchBug",
"true",
"S_INST_PREFETCH instruction causes shader to hang"
>;
def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
"HasVcmpxExecWARHazard",
"true",
"V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
>;
def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
"HasLdsBranchVmemWARHazard",
"true",
"Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
>;
def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
"HasNSAtoVMEMBug",
"true",
"MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
>;
def FeatureNSAClauseBug : SubtargetFeature<"nsa-clause-bug",
"HasNSAClauseBug",
"true",
"MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
>;
def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
"HasFlatSegmentOffsetBug",
"true",
"GFX10 bug where inst_offset is ignored when flat instructions access global memory"
>;
def FeatureNegativeScratchOffsetBug : SubtargetFeature<"negative-scratch-offset-bug",
"NegativeScratchOffsetBug",
"true",
"Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9"
>;
def FeatureNegativeUnalignedScratchOffsetBug : SubtargetFeature<"negative-unaligned-scratch-offset-bug",
"NegativeUnalignedScratchOffsetBug",
"true",
"Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of 4 read wrong memory on GFX10"
>;
def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
"HasOffset3fBug",
"true",
"Branch offset of 3f hardware bug"
>;
def FeatureImageStoreD16Bug : SubtargetFeature<"image-store-d16-bug",
"HasImageStoreD16Bug",
"true",
"Image Store D16 hardware bug"
>;
def FeatureImageGather4D16Bug : SubtargetFeature<"image-gather4-d16-bug",
"HasImageGather4D16Bug",
"true",
"Image Gather4 D16 hardware bug"
>;
class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
"ldsbankcount"#Value,
"LDSBankCount",
!cast<string>(Value),
"The number of LDS banks per compute unit."
>;
def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
"GCN3Encoding",
"true",
"Encoding format for VI"
>;
def FeatureCIInsts : SubtargetFeature<"ci-insts",
"CIInsts",
"true",
"Additional instructions for CI+"
>;
def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
"GFX8Insts",
"true",
"Additional instructions for GFX8+"
>;
def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
"GFX9Insts",
"true",
"Additional instructions for GFX9+"
>;
def FeatureGFX90AInsts : SubtargetFeature<"gfx90a-insts",
"GFX90AInsts",
"true",
"Additional instructions for GFX90A+"
>;
def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
"GFX10Insts",
"true",
"Additional instructions for GFX10+"
>;
def FeatureGFX10_3Insts : SubtargetFeature<"gfx10-3-insts",
"GFX10_3Insts",
"true",
"Additional instructions for GFX10.3"
>;
def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
"GFX7GFX8GFX9Insts",
"true",
"Instructions shared in GFX7, GFX8, GFX9"
>;
def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
"HasSMemRealTime",
"true",
"Has s_memrealtime instruction"
>;
def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
"HasInv2PiInlineImm",
"true",
"Has 1 / (2 * pi) as inline immediate"
>;
def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
"Has16BitInsts",
"true",
"Has i16/f16 instructions"
>;
def FeatureVOP3P : SubtargetFeature<"vop3p",
"HasVOP3PInsts",
"true",
"Has VOP3P packed instructions"
>;
def FeatureMovrel : SubtargetFeature<"movrel",
"HasMovrel",
"true",
"Has v_movrel*_b32 instructions"
>;
def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
"HasVGPRIndexMode",
"true",
"Has VGPR mode register indexing"
>;
def FeatureScalarStores : SubtargetFeature<"scalar-stores",
"HasScalarStores",
"true",
"Has store scalar memory instructions"
>;
def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
"HasScalarAtomics",
"true",
"Has atomic scalar memory instructions"
>;
def FeatureSDWA : SubtargetFeature<"sdwa",
"HasSDWA",
"true",
"Support SDWA (Sub-DWORD Addressing) extension"
>;
def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
"HasSDWAOmod",
"true",
"Support OMod with SDWA (Sub-DWORD Addressing) extension"
>;
def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
"HasSDWAScalar",
"true",
"Support scalar register with SDWA (Sub-DWORD Addressing) extension"
>;
def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
"HasSDWASdst",
"true",
"Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
>;
def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
"HasSDWAMac",
"true",
"Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
>;
def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
"HasSDWAOutModsVOPC",
"true",
"Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
>;
def FeatureDPP : SubtargetFeature<"dpp",
"HasDPP",
"true",
"Support DPP (Data Parallel Primitives) extension"
>;
// DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
def FeatureDPP8 : SubtargetFeature<"dpp8",
"HasDPP8",
"true",
"Support DPP8 (Data Parallel Primitives) extension"
>;
def Feature64BitDPP : SubtargetFeature<"dpp-64bit",
"Has64BitDPP",
"true",
"Support DPP (Data Parallel Primitives) extension"
>;
def FeaturePackedFP32Ops : SubtargetFeature<"packed-fp32-ops",
"HasPackedFP32Ops",
"true",
"Support packed fp32 instructions"
>;
def FeatureR128A16 : SubtargetFeature<"r128-a16",
"HasR128A16",
"true",
"Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
>;
def FeatureGFX10A16 : SubtargetFeature<"a16",
"HasGFX10A16",
"true",
"Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
>;
def FeatureG16 : SubtargetFeature<"g16",
"HasG16",
"true",
"Support G16 for 16-bit gradient image operands"
>;
def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
"HasNSAEncoding",
"true",
"Support NSA encoding for image instructions"
>;
def FeatureExtendedImageInsts : SubtargetFeature<"extended-image-insts",
"HasExtendedImageInsts",
"true",
"Support mips != 0, lod != 0, gather4, and get_lod"
>;
def FeatureGFX10_AEncoding : SubtargetFeature<"gfx10_a-encoding",
"GFX10_AEncoding",
"true",
"Has BVH ray tracing instructions"
>;
def FeatureGFX10_BEncoding : SubtargetFeature<"gfx10_b-encoding",
"GFX10_BEncoding",
"true",
"Encoding format GFX10_B"
>;
def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
"HasIntClamp",
"true",
"Support clamp for integer destination"
>;
def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
"HasUnpackedD16VMem",
"true",
"Has unpacked d16 vmem instructions"
>;
def FeatureDLInsts : SubtargetFeature<"dl-insts",
"HasDLInsts",
"true",
"Has v_fmac_f32 and v_xnor_b32 instructions"
>;
def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
"HasDot1Insts",
"true",
"Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
>;
def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
"HasDot2Insts",
"true",
"Has v_dot2_i32_i16, v_dot2_u32_u16 instructions"
>;
def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
"HasDot3Insts",
"true",
"Has v_dot8c_i32_i4 instruction"
>;
def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
"HasDot4Insts",
"true",
"Has v_dot2c_i32_i16 instruction"
>;
def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
"HasDot5Insts",
"true",
"Has v_dot2c_f32_f16 instruction"
>;
def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
"HasDot6Insts",
"true",
"Has v_dot4c_i32_i8 instruction"
>;
def FeatureDot7Insts : SubtargetFeature<"dot7-insts",
"HasDot7Insts",
"true",
"Has v_dot2_f32_f16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
>;
def FeatureMAIInsts : SubtargetFeature<"mai-insts",
"HasMAIInsts",
"true",
"Has mAI instructions"
>;
def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
"HasPkFmacF16Inst",
"true",
"Has v_pk_fmac_f16 instruction"
>;
def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
"HasAtomicFaddInsts",
"true",
"Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
"global_atomic_pk_add_f16 instructions",
[FeatureFlatGlobalInsts]
>;
def FeatureSupportsSRAMECC : SubtargetFeature<"sramecc-support",
"SupportsSRAMECC",
"true",
"Hardware supports SRAMECC"
>;
def FeatureSRAMECC : SubtargetFeature<"sramecc",
"EnableSRAMECC",
"true",
"Enable SRAMECC"
>;
def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
"HasNoSdstCMPX",
"true",
"V_CMPX does not write VCC/SGPR in addition to EXEC"
>;
def FeatureVscnt : SubtargetFeature<"vscnt",
"HasVscnt",
"true",
"Has separate store vscnt counter"
>;
def FeatureGetWaveIdInst : SubtargetFeature<"get-wave-id-inst",
"HasGetWaveIdInst",
"true",
"Has s_get_waveid_in_workgroup instruction"
>;
def FeatureSMemTimeInst : SubtargetFeature<"s-memtime-inst",
"HasSMemTimeInst",
"true",
"Has s_memtime instruction"
>;
def FeatureShaderCyclesRegister : SubtargetFeature<"shader-cycles-register",
"HasShaderCyclesRegister",
"true",
"Has SHADER_CYCLES hardware register"
>;
def FeatureMadMacF32Insts : SubtargetFeature<"mad-mac-f32-insts",
"HasMadMacF32Insts",
"true",
"Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions"
>;
def FeatureDsSrc2Insts : SubtargetFeature<"ds-src2-insts",
"HasDsSrc2Insts",
"true",
"Has ds_*_src2 instructions"
>;
def FeatureRegisterBanking : SubtargetFeature<"register-banking",
"HasRegisterBanking",
"true",
"Has register banking"
>;
def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
"HasVOP3Literal",
"true",
"Can use one literal in VOP3"
>;
def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
"HasNoDataDepHazard",
"true",
"Does not need SW waitstates"
>;
//===------------------------------------------------------------===//
// Subtarget Features (options and debugging)
//===------------------------------------------------------------===//
class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
"max-private-element-size-"#size,
"MaxPrivateElementSize",
!cast<string>(size),
"Maximum private access size may be "#size
>;
def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
def FeatureDumpCode : SubtargetFeature <"DumpCode",
"DumpCode",
"true",
"Dump MachineInstrs in the CodeEmitter"
>;
def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
"DumpCode",
"true",
"Dump MachineInstrs in the CodeEmitter"
>;
// XXX - This should probably be removed once enabled by default
def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
"EnableLoadStoreOpt",
"true",
"Enable SI load/store optimizer pass"
>;
// Performance debugging feature. Allow using DS instruction immediate
// offsets even if the base pointer can't be proven to be base. On SI,
// base pointer values that won't give the same result as a 16-bit add
// are not safe to fold, but this will override the conservative test
// for the base pointer.
def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
"unsafe-ds-offset-folding",
"EnableUnsafeDSOffsetFolding",
"true",
"Force using DS instruction immediate offsets on SI"
>;
def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
"EnableSIScheduler",
"true",
"Enable SI Machine Scheduler"
>;
def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
"EnableDS128",
"true",
"Use ds_{read|write}_b128"
>;
// Sparse texture support requires that all result registers are zeroed when
// PRTStrictNull is set to true. This feature is turned on for all architectures
// but is enabled as a feature in case there are situations where PRTStrictNull
// is disabled by the driver.
def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
"EnablePRTStrictNull",
"true",
"Enable zeroing of result registers for sparse texture fetches"
>;
// Unless +-flat-for-global is specified, turn on FlatForGlobal for
// all OS-es on VI and newer hardware to avoid assertion failures due
// to missing ADDR64 variants of MUBUF instructions.
// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
// instructions.
def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
"FlatForGlobal",
"true",
"Force to generate flat instruction for global"
>;
def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
"auto-waitcnt-before-barrier",
"AutoWaitcntBeforeBarrier",
"true",
"Hardware automatically inserts waitcnt before barrier"
>;
def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
"HasTrigReducedRange",
"true",
"Requires use of fract on arguments to trig instructions"
>;
// Alignment enforcement is controlled by a configuration register:
// SH_MEM_CONFIG.alignment_mode
def FeatureUnalignedAccessMode : SubtargetFeature<"unaligned-access-mode",
"UnalignedAccessMode",
"true",
"Enable unaligned global, local and region loads and stores if the hardware"
" supports it"
>;
def FeaturePackedTID : SubtargetFeature<"packed-tid",
"HasPackedTID",
"true",
"Workitem IDs are packed into v0 at kernel launch"
>;
def FeatureArchitectedFlatScratch : SubtargetFeature<"architected-flat-scratch",
"HasArchitectedFlatScratch",
"true",
"Flat Scratch register is a readonly SPI initialized architected register"
>;
// Dummy feature used to disable assembler instructions.
def FeatureDisable : SubtargetFeature<"",
"FeatureDisable","true",
"Dummy feature to disable assembler instructions"
>;
class GCNSubtargetFeatureGeneration <string Value,
string FeatureName,
list<SubtargetFeature> Implies> :
SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
"southern-islands",
[FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts,
FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,
FeatureTrigReducedRange, FeatureExtendedImageInsts
]
>;
def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
"sea-islands",
[FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
FeatureWavefrontSize64, FeatureFlatAddressSpace,
FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureUnalignedBufferAccess
]
>;
def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
"volcanic-islands",
[FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
FeatureWavefrontSize64, FeatureFlatAddressSpace,
FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
FeatureScalarStores, FeatureInv2PiInlineImm,
FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureFastDenormalF32,
FeatureUnalignedBufferAccess
]
>;
def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
"gfx9",
[FeatureFP64, FeatureLocalMemorySize65536,
FeatureWavefrontSize64, FeatureFlatAddressSpace,
FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureSupportsXNACK,
FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess,
FeatureNegativeScratchOffsetBug
]
>;
def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
"gfx10",
[FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
FeatureFlatAddressSpace,
FeatureCIInsts, Feature16BitInsts,
FeatureSMemRealTime, FeatureInv2PiInlineImm,
FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
FeatureVOP3Literal, FeatureDPP8, FeatureExtendedImageInsts,
FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
FeatureGFX10A16, FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureG16,
FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess
]
>;
class FeatureSet<list<SubtargetFeature> Features_> {
list<SubtargetFeature> Features = Features_;
}
def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
FeatureFastFMAF32,
HalfRate64Ops,
FeatureLDSBankCount32]>;
def FeatureISAVersion6_0_1 : FeatureSet<
[FeatureSouthernIslands,
FeatureLDSBankCount32]>;
def FeatureISAVersion6_0_2 : FeatureSet<
[FeatureSouthernIslands,
FeatureLDSBankCount32]>;
def FeatureISAVersion7_0_0 : FeatureSet<
[FeatureSeaIslands,
FeatureLDSBankCount32]>;
def FeatureISAVersion7_0_1 : FeatureSet<
[FeatureSeaIslands,
HalfRate64Ops,
FeatureLDSBankCount32,
FeatureFastFMAF32]>;
def FeatureISAVersion7_0_2 : FeatureSet<
[FeatureSeaIslands,
FeatureLDSBankCount16,
FeatureFastFMAF32]>;
def FeatureISAVersion7_0_3 : FeatureSet<
[FeatureSeaIslands,
FeatureLDSBankCount16]>;
def FeatureISAVersion7_0_4 : FeatureSet<
[FeatureSeaIslands,
FeatureLDSBankCount32]>;
def FeatureISAVersion7_0_5 : FeatureSet<
[FeatureSeaIslands,
FeatureLDSBankCount16]>;
def FeatureISAVersion8_0_1 : FeatureSet<
[FeatureVolcanicIslands,
FeatureFastFMAF32,
HalfRate64Ops,
FeatureLDSBankCount32,
FeatureSupportsXNACK,
FeatureUnpackedD16VMem]>;
def FeatureISAVersion8_0_2 : FeatureSet<
[FeatureVolcanicIslands,
FeatureLDSBankCount32,
FeatureSGPRInitBug,
FeatureUnpackedD16VMem]>;
def FeatureISAVersion8_0_3 : FeatureSet<
[FeatureVolcanicIslands,
FeatureLDSBankCount32,
FeatureUnpackedD16VMem]>;
def FeatureISAVersion8_0_5 : FeatureSet<
[FeatureVolcanicIslands,
FeatureLDSBankCount32,
FeatureSGPRInitBug,
FeatureUnpackedD16VMem]>;
def FeatureISAVersion8_1_0 : FeatureSet<
[FeatureVolcanicIslands,
FeatureLDSBankCount16,
FeatureSupportsXNACK,
FeatureImageStoreD16Bug,
FeatureImageGather4D16Bug]>;
def FeatureISAVersion9_0_0 : FeatureSet<
[FeatureGFX9,
FeatureMadMixInsts,
FeatureLDSBankCount32,
FeatureDsSrc2Insts,
FeatureExtendedImageInsts,
FeatureMadMacF32Insts,
FeatureImageGather4D16Bug]>;
def FeatureISAVersion9_0_2 : FeatureSet<
[FeatureGFX9,
FeatureMadMixInsts,
FeatureLDSBankCount32,
FeatureDsSrc2Insts,
FeatureExtendedImageInsts,
FeatureMadMacF32Insts,
FeatureImageGather4D16Bug]>;
def FeatureISAVersion9_0_4 : FeatureSet<
[FeatureGFX9,
FeatureLDSBankCount32,
FeatureDsSrc2Insts,
FeatureExtendedImageInsts,
FeatureMadMacF32Insts,
FeatureFmaMixInsts,
FeatureImageGather4D16Bug]>;
def FeatureISAVersion9_0_6 : FeatureSet<
[FeatureGFX9,
HalfRate64Ops,
FeatureFmaMixInsts,
FeatureLDSBankCount32,
FeatureDsSrc2Insts,
FeatureExtendedImageInsts,
FeatureMadMacF32Insts,
FeatureDLInsts,
FeatureDot1Insts,
FeatureDot2Insts,
FeatureDot7Insts,
FeatureSupportsSRAMECC,
FeatureImageGather4D16Bug]>;
def FeatureISAVersion9_0_8 : FeatureSet<
[FeatureGFX9,
HalfRate64Ops,
FeatureFmaMixInsts,
FeatureLDSBankCount32,
FeatureDsSrc2Insts,
FeatureExtendedImageInsts,
FeatureMadMacF32Insts,
FeatureDLInsts,
FeatureDot1Insts,
FeatureDot2Insts,
FeatureDot3Insts,
FeatureDot4Insts,
FeatureDot5Insts,
FeatureDot6Insts,
FeatureDot7Insts,
FeatureMAIInsts,
FeaturePkFmacF16Inst,
FeatureAtomicFaddInsts,
FeatureSupportsSRAMECC,
FeatureMFMAInlineLiteralBug,
FeatureImageGather4D16Bug]>;
def FeatureISAVersion9_0_9 : FeatureSet<
[FeatureGFX9,
FeatureMadMixInsts,
FeatureLDSBankCount32,
FeatureDsSrc2Insts,
FeatureExtendedImageInsts,
FeatureMadMacF32Insts,
FeatureImageGather4D16Bug]>;
def FeatureISAVersion9_0_A : FeatureSet<
[FeatureGFX9,
FeatureGFX90AInsts,
FeatureFmaMixInsts,
FeatureLDSBankCount32,
FeatureDLInsts,
FeatureDot1Insts,
FeatureDot2Insts,
FeatureDot3Insts,
FeatureDot4Insts,
FeatureDot5Insts,
FeatureDot6Insts,
FeatureDot7Insts,
Feature64BitDPP,
FeaturePackedFP32Ops,
FeatureMAIInsts,
FeaturePkFmacF16Inst,
FeatureAtomicFaddInsts,
FeatureMadMacF32Insts,
FeatureSupportsSRAMECC,
FeaturePackedTID,
FullRate64Ops]>;