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[GlobalISel][TableGen] Support Intrinsics in MIR Patterns (#79278)
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10 changes: 10 additions & 0 deletions
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llvm/test/TableGen/GlobalISelCombinerEmitter/Inputs/test-intrinsics.td
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// Dummy intrinsic definitions for TableGen. | ||
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def int_1in_1out : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], []>; | ||
def int_0in_1out : DefaultAttrsIntrinsic<[llvm_i32_ty], [], []>; | ||
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def int_sideeffects_1in_1out : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrHasSideEffects]>; | ||
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def int_convergent_1in_1out : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrConvergent]>; | ||
def int_convergent_sideeffects_1in_1out : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrConvergent, IntrHasSideEffects]>; |
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86 changes: 86 additions & 0 deletions
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llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
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// RUN: llvm-tblgen -I %S/Inputs -I %p/../../../include -gen-global-isel-combiner \ | ||
// RUN: -combiners=MyCombiner %s | \ | ||
// RUN: FileCheck %s | ||
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include "llvm/Target/Target.td" | ||
include "llvm/Target/GlobalISel/Combine.td" | ||
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include "test-intrinsics.td" | ||
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def MyTargetISA : InstrInfo; | ||
def MyTarget : Target { let InstructionSet = MyTargetISA; } | ||
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def IntrinTest0 : GICombineRule< | ||
(defs root:$a), | ||
(match (int_1in_1out $a, 0)), | ||
(apply (int_1in_1out $a, $x), | ||
(int_0in_1out i32:$x))>; | ||
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def SpecialIntrins : GICombineRule< | ||
(defs root:$a), | ||
(match (int_sideeffects_1in_1out $a, $b)), | ||
(apply (int_convergent_1in_1out i32:$x, $b), | ||
(int_convergent_sideeffects_1in_1out $a, $x))>; | ||
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def MyCombiner: GICombiner<"GenMyCombiner", [ | ||
IntrinTest0, | ||
SpecialIntrins | ||
]>; | ||
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// CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { | ||
// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { | ||
// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(114), GIMT_Encode2(116), /*)*//*default:*//*Label 2*/ GIMT_Encode4(132), | ||
// CHECK-NEXT: /*TargetOpcode::G_INTRINSIC*//*Label 0*/ GIMT_Encode4(18), | ||
// CHECK-NEXT: /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 1*/ GIMT_Encode4(73), | ||
// CHECK-NEXT: // Label 0: @18 | ||
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(72), // Rule ID 0 // | ||
// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), | ||
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, | ||
// CHECK-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::1in_1out), | ||
// CHECK-NEXT: // MIs[0] a | ||
// CHECK-NEXT: // No operand predicates | ||
// CHECK-NEXT: // MIs[0] Operand 2 | ||
// CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, | ||
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, | ||
// CHECK-NEXT: // Combiner Rule #0: IntrinTest0 | ||
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC), | ||
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), | ||
// CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/0, GIMT_Encode2(Intrinsic::0in_1out), | ||
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC), | ||
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a | ||
// CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/1, GIMT_Encode2(Intrinsic::1in_1out), | ||
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, | ||
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, | ||
// CHECK-NEXT: GIR_Done, | ||
// CHECK-NEXT: // Label 3: @72 | ||
// CHECK-NEXT: GIM_Reject, | ||
// CHECK-NEXT: // Label 1: @73 | ||
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(131), // Rule ID 1 // | ||
// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule1Enabled), | ||
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, | ||
// CHECK-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::sideeffects_1in_1out), | ||
// CHECK-NEXT: // MIs[0] a | ||
// CHECK-NEXT: // No operand predicates | ||
// CHECK-NEXT: // MIs[0] b | ||
// CHECK-NEXT: // No operand predicates | ||
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, | ||
// CHECK-NEXT: // Combiner Rule #1: SpecialIntrins | ||
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC_CONVERGENT), | ||
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), | ||
// CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/0, GIMT_Encode2(Intrinsic::convergent_1in_1out), | ||
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b | ||
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS), | ||
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a | ||
// CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/1, GIMT_Encode2(Intrinsic::convergent_sideeffects_1in_1out), | ||
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, | ||
// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, | ||
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, | ||
// CHECK-NEXT: GIR_Done, | ||
// CHECK-NEXT: // Label 4: @131 | ||
// CHECK-NEXT: GIM_Reject, | ||
// CHECK-NEXT: // Label 2: @132 | ||
// CHECK-NEXT: GIM_Reject, | ||
// CHECK-NEXT: }; // Size: 133 bytes | ||
// CHECK-NEXT: return MatchTable0; | ||
// CHECK-NEXT: } |
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config.suffixes = [".td"] | ||
config.excludes = ["Common"] | ||
config.excludes = ["Common", "Inputs"] |
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