Subregister support

[llvmbot]

Bugzilla Link	769
Resolution	DUPLICATE
Resolved on	Sep 26, 2007 01:14
Version	1.0
OS	All
Reporter	LLVM Bugzilla Contributor

Extended Description

This bug is to cover the work necessary in tablegen and the common code generator to support
subregisters. This will intially be used by PowerPC for condition registers, but will be extended to be
used by x86 for 8 and 16 bit (and 32 bit?) subregs.

An pseudocode example of this will basically look like:

virtual reg 1024, 1025 = CRField register class
virtual reg 1026 = CRBits register class

1024 = seteq X, Y
1025 = seteq W, Z
1026 = crand 1024.subreg(EQ), 1025.subreg(EQ)
br_cc 1026, mbb5

where EQ will be the subreg number of the "EQ" field in the CRField register class.

[lattner]

This will also be extremely valuable for SPARC, which will let us get rid of the ugly FPMover.cpp hack.

Basically in the case of SPARC V8, there is no "copy double precision FP value", you have to do it as 2
copies of floats.

I would like to be able to codegen copy as:

Dest.subreg(LO) = COPYFLOAT SRC.subreg(LO)
Dest.subreg(HI) = COPYFLOAT SRC.subreg(HI)

In the instruction selector, then have everything happen.

Actually, this brings up an interesting point: we will probably have to do something special to handle
SSA and subreg definitions. In the example above, "Dest" is defined twice! :(

-Chris

[lattner]

*** This bug has been marked as a duplicate of bug llvm/llvm-bugzilla-archive#1350 ***