aarch64: __builtin_shufflevector with a zero vector CST as the second argument and doing a "ext" like should produce ushr/shl

[pinskia]

Take:

#define vect64 __attribute__((vector_size(8)))

void f(vect64  unsigned short *a)
{
  *a = __builtin_shufflevector(*a,(vect64 unsigned short){0}, 2,3, 4,5);
}

This should just produce (for little-endian; big-endian should be shl instead):

        ldr     d31, [x0]
        ushr d31, d31, 32
        str     d31, [x0]

Right now, LLVM produces mov/ext to do this shuffle.

[pinskia]

Note LLVM is able to handle this for x86_64. GCC is just the opposite; handling it for aarch64 and not for x86_64. Filed https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113871 for the GCC not handling it on x86_64.

[llvmbot]

@llvm/issue-subscribers-backend-aarch64

Author: Andrew Pinski (pinskia)

Take: ``` #define vect64 __attribute__((vector_size(8)))

void f(vect64 unsigned short *a)
{
*a = __builtin_shufflevector(*a,(vect64 unsigned short){0}, 2,3, 4,5);
}

This should just produce (for little-endian; big-endian should be shl instead):

    ldr     d31, [x0]
    ushr d31, d31, 32
    str     d31, [x0]

Right now, LLVM produces mov/ext to do this shuffle.

</details>

[pinskia]

Note the first operand as 0 can use shl/ushr too.
Like:

#define vect64 __attribute__((vector_size(8)))

void f(vect64  unsigned short *a)
{
  *a = __builtin_shufflevector((vect64 unsigned short){0},*a, 3,4,5,6);
}

GCC does not catch this one though, I filed https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113872 for that.