Cannot Pass Ring Oscillator Through OpenFPGA yosys_flow?

[tornupnegatives]

Our team is interested in synthesizing a ring oscillator design to assist in radiation-testing of our FPGA architecture. I have been trying at this for a little while with minimal success, so I am hoping the community can shed some light on it.

I have created a custom yosys script (attached) which is for the most part identical to the default one used by the OpenFPGA yosys_flow. However, I have limited the scope of the synth command so that it does not go through the "check" pass, which would throw an error due to the logical loop intrinsic to the ring oscillator design. That is, yosys seems natively configured to detect oscillations and reject such designs. Disabling this check allows for the generation of a BLIF file regardless.

However, if I disable this check, the <bench>_output_verilog.v file is never emitted, and even if I force emit it, the OpenFPGA flow does not continue. The OpenFPGA flow simply throws the following error:

Traceback (most recent call last):
  File "/opt/openfpga/openfpga_flow/scripts/run_fpga_flow.py", line 805, in run_ace2
    process = subprocess.run(
  File "/usr/lib/python3.8/subprocess.py", line 516, in run
    raise CalledProcessError(retcode, process.args,
subprocess.CalledProcessError: Command '['/opt/openfpga/build/vtr-verilog-to-routing/ace2/ace', '-b', 'ring_oscillator_yosys_out.blif', '-o', 'ring_oscillator_ace_out.act', '-n', 'ring_oscillator_ace_out.blif', '-c', 'clk', '', '']' died with <Signals.SIGABRT: 6>.

Could you please shed some light on this issue? If you need more information, let me know.

ring_oscillator.ys.txt