L-E needs a bidirectional input/output pin component

[prlaba]

As far as I know, L-E's only "bidirectional" component is the RAM component, which can be configured to have bidirectional data pins.

However, to create a circuit using the bidirectional RAM component, you're forced to create a separate DATA_IN input pin and DATA_OUT output pin, and connect them both to the RAM's data pins. (Additionally you would create WE and OE input pins, connected, respectively, to the RAM's WE and OE pins, and a CLK input pin if you're using a clock to drive the RAM's read/write operations.)

You can connect the DATA_IN and DATA_OUT pins directly to the RAM's data pins, so long as they're configured as tri-state (Three-state property set to Yes). Of course you have to ensure that: 1) the DATA_IN pin is floating (U) when reading from RAM (OE=1), 2) the DATA_OUT pin is floating when writing to RAM (WE=1), and 3) the OE and WE pins are not both 1 at the same time; otherwise you'll see signal/bus conflicts (red lines between the RAM's data pins and the DATA_IN and DATA_OUT pins).

This arrangement works fine when the RAM component is used in a stand-alone main circuit, but causes problems when used as a subcircuit.

Because the RAM subcircuit uses separate DATA_IN and DATA_OUT input and output pins, the master circuit is forced to also deal with separate data input and data output signals. Depending on the master circuit's requirements, it can create its own DATA_IN and DATA_OUT input and output pins, but if it attempts to tie the two pins together (as was done in the RAM subcircuit) an immediate Oscillation Apparent error occurs.

One solution is to use controlled buffers in the RAM subcircuit, one controlled by its WE input pin, the other controlled by its OE input pin. The outputs of both buffers are then connected directly to the RAM's data pins. This eliminates the oscillation error in the master circuit. Through experiments, I discovered that only a WE controlled buffer is needed; the DATA_OUT output pin can be connected directly to the RAM's data pins without any oscillation errors in the master circuit.

But all of this could be avoided if L-E provided a bidirectional input/output pin (see the Digital simulator for an example of such a component). Such a pin would eliminate the need for separate DATA_IN and DATA_OUT input and output pins tied, directly or through buffers, to the RAM's bidirectional data pins; instead a single bidirectional DATA (or BUS) pin, tied directly to the RAM's data pins, would suffice. This would more naturally reflect how an actual RAM component would be connected in a circuit.

Comments?

[BFH-ktt1]

I find this a very interesting discussion that I have seen more often. Bi-directional buses are basically used to reduce pin-count, but also have their inherent "problems". When I did my studies in the 1980's this was a big issue, as the limitation was on the PCB, and we were working at "high" frequencies starting from 100MHz. Nowadays we have to ask at which level are we going to do digital design, PCB-level or ASIC/FPGA level. On PCB, bi-directional buses make sense, as the different IC's require less "pads", but on ASIC/FPGA level it only introduces unnecessary delays due to the capacitance that needs to be charged/discharged (three-state; analog aspects of digital circuits), that reduces drastically the speed of the overall system compared to s simple "Push-Pull" input-output system. The basic Idea in LE for the moment is a digital design in an FPGA/ASIC, where the bi-directional behavior is only on top-level for IO-PAD reduction. Just my 5c's.

[primechaser]

thanks @BFH-ktt1 for pointing me to this component.
I had a brief look and realized, generated HDL seems to be incomplete (please refer to attached RTL).
In addition you might want to consider also accepting "number of pins" set to "1".

Thanks for looking into this.

portIO_test.zip

[BFH-ktt1]

@primechaser : You're completely right, there was a bug in the HDL-generator of the PortIO component. My latest PR fixes this, and also allows to set the number of pins to 1.

[prlaba]

Re the I/O Port component...

I've never used the I/O Port component before, but I don't see how it's relevant to this discussion, since that component has separate input and output pins. Yes, the device internally ties the two pins together but it separates the input and output sides externally.

The RAM component, on the other hand, has a single bidirectional data pin (if you configure it that way); and therein lies the problem if you're trying to use it in a circuit without a bidirectional Pin component: you're forced to split the RAM's data pins into an input side (using an input Pin) and output side (using and output Pin).

If you're trying to use L-E to create circuits that contain a bidirectional bus (like I am), you generally don't want to separate that bus into an input side and output side; you simply connect devices to it. Devices that gate data onto the bus (input devices) need a controlled buffer between their data and the bus, so that there is only one bus master at a time. Devices that accept data from the bus (output devices) don't need a controlled buffer-they can all be connected directly to the bus. Because the RAM component provides its own internally controlled buffers (controlled by the WE and OE inputs), no external buffers should be required to connect that device to the bus.

A bidirectional Pin would not seem difficult to implement, but that may not be true in the case of L-E. If you're interested, check out the Digital simulator and play around with its bidirectional pin.

[prlaba]

I should clarify my comment re the Digital simulator.

Digital doesn't have a Bidirectional Pin component per se. Instead, it converts its standard Input and Output pins to be bidirectional when they're used in a subcircuit.

Check out the custom Memory circuit, which contains a 32K x 16 ROM and 32K x 16 RAM, as a good example. The Memory circuit's 16-bit data bus is an Output pin, so you can't load data into memory when using the circuit standalone. But when the circuit is used as a subcircuit, that same pin becomes bidirectional in the master curcuit, meaning you can connect an Input pin to the same bus to write to the subcircuit's RAM, or attach other input devices (with their own controlled buffers) to gate data onto the data bus, or attach other output devices onto the bus.

The key here is that the data bus - the output from the Memory subcircuit - never has to be split into two separate "data-in" and "data-out" busses.

[maehne]

There have been many issues raised about supporting inout ports / bidirectional ports and several attempts to support them in Logisim-evolution, as summarised by @kevinawalsh's comment in issue #253. Unfortunately, Logisim's simulation engine would need a complete rewrite to make this possible, for which we lack ressources. PRs in this direction are welcome, but be aware it is a major undertaking and would require a lot of testing to ensure compatibility with existing Logisim-evolution designs.