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gcc 编译器问题 internal compiler error: in output_constructor_regular_field, at varasm.c:5512 #77
Comments
struct Mul02Table
{
constexpr Mul02Table() : values()
{
for (int s = 0; s < 4; s++) {
values[s] = 1;
}
}
unsigned char values[4];
};
static constexpr Mul02Table mul02; native stage1 works:
native stage2 broken:
由于交叉编译没问题,stage1 也没问题(这个其实比较可疑,没想明白原因),问题肯定在 附上 stacktrace(拿我系统编译器产生的):
|
loongson/build-tools#12 (comment) |
确认了这个 fix 解决不了这边的问题,stage2 仍然 ICE |
之前还找到的另外一个可能是 |
这个昨天确认了,也解决不了问题 |
cross post from loongson/build-tools#12:
|
确认这个问题被 upstream v6.2 分支修复了(我使用的集成分支 https://github.com/xen0n/gcc/commits/for-gentoo-gcc-12-v20220210 ) For the record: (likely fixed by the added bstrpick/alsl constraints) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index fa7e24c31df..2cd3ff76dfb 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -1286,7 +1286,7 @@
(match_operand:SHORT 1 "nonimmediate_operand" "r,m")))]
""
"@
- bstrpick.<d>\t%0,%1,<SHORT:qi_hi>,0
+ bstrpick.w\t%0,%1,<SHORT:qi_hi>,0
ld.<SHORT:size>u\t%0,%1"
[(set_attr "move_type" "pick_ins,load")
(set_attr "compression" "*,*")
@@ -1309,7 +1309,7 @@
(zero_extend:GPR
(truncate:SHORT (match_operand:DI 1 "register_operand" "r"))))]
"TARGET_64BIT"
- "bstrpick.<d>\t%0,%1,<SHORT:qi_hi>,0"
+ "bstrpick.w\t%0,%1,<SHORT:qi_hi>,0"
[(set_attr "move_type" "pick_ins")
(set_attr "mode" "<GPR:MODE>")])
@@ -1404,7 +1404,7 @@
(sign_extend:HI
(truncate:QI (match_operand:DI 1 "register_operand" "r"))))]
"TARGET_64BIT"
- "ext.w.<size>\t%0,%1"
+ "ext.w.b\t%0,%1"
[(set_attr "move_type" "signext")
(set_attr "mode" "SI")])
@@ -2500,12 +2500,24 @@
[(set_attr "type" "shift,shift")
(set_attr "mode" "<MODE>")])
+;; The following templates were added to generate "bstrpick.d + alsl.d"
+;; instruction pairs.
+;; It is required that the values of const_immlsa_operand and
+;; shift_mask_operand must have the following correspondence:
+;;
+;; const_immlsa_operand shift_mask_operand
+;; 1 <=> 0x1fffffffe
+;; 2 <=> 0x3fffffffc
+;; 3 <=> 0x7fffffff8
+;; 4 <=> 0xffffffff0
+
(define_insn "zero_extend_ashift1"
[(set (match_operand:DI 0 "register_operand" "=r")
(and:DI (ashift:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0)
(match_operand 2 "const_immlsa_operand" ""))
(match_operand 3 "shift_mask_operand" "")))]
- "TARGET_64BIT"
+ "TARGET_64BIT
+ && (((((1 << INTVAL (operands[2])) - 1) + (INTVAL (operands[3]))) & 0xf) == 0xf)"
"bstrpick.d\t%0,%1,31,0\n\talsl.d\t%0,%0,$r0,%2"
[(set_attr "type" "arith")
(set_attr "mode" "DI")
@@ -2516,7 +2528,8 @@
(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
(match_operand 2 "const_immlsa_operand" ""))
(match_operand 3 "shift_mask_operand" "")))]
- "TARGET_64BIT"
+ "TARGET_64BIT
+ && (((((1 << INTVAL (operands[2])) - 1) + (INTVAL (operands[3]))) & 0xf) == 0xf)"
"bstrpick.d\t%0,%1,31,0\n\talsl.d\t%0,%0,$r0,%2"
[(set_attr "type" "arith")
(set_attr "mode" "DI")
@@ -2525,10 +2538,11 @@
(define_insn "alsl_paired1"
[(set (match_operand:DI 0 "register_operand" "=&r")
(plus:DI (and:DI (ashift:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0)
- (match_operand 2 "const_immlsa_operand" ""))
- (match_operand 3 "shift_mask_operand" ""))
- (match_operand:DI 4 "register_operand" "r")))]
- "TARGET_64BIT"
+ (match_operand 2 "const_immlsa_operand" ""))
+ (match_operand 3 "shift_mask_operand" ""))
+ (match_operand:DI 4 "register_operand" "r")))]
+ "TARGET_64BIT
+ && (((((1 << INTVAL (operands[2])) - 1) + (INTVAL (operands[3]))) & 0xf) == 0xf)"
"bstrpick.d\t%0,%1,31,0\n\talsl.d\t%0,%0,%4,%2"
[(set_attr "type" "arith")
(set_attr "mode" "DI")
@@ -2537,10 +2551,11 @@
(define_insn "alsl_paired2"
[(set (match_operand:DI 0 "register_operand" "=&r")
(plus:DI (match_operand:DI 1 "register_operand" "r")
- (and:DI (ashift:DI (match_operand:DI 2 "register_operand" "r")
- (match_operand 3 "const_immlsa_operand" ""))
- (match_operand 4 "shift_mask_operand" ""))))]
- "TARGET_64BIT"
+ (and:DI (ashift:DI (match_operand:DI 2 "register_operand" "r")
+ (match_operand 3 "const_immlsa_operand" ""))
+ (match_operand 4 "shift_mask_operand" ""))))]
+ "TARGET_64BIT
+ && (((((1 << INTVAL (operands[3])) - 1) + (INTVAL (operands[4]))) & 0xf) == 0xf)"
"bstrpick.d\t%0,%2,31,0\n\talsl.d\t%0,%0,%1,%3"
[(set_attr "type" "arith")
(set_attr "mode" "DI")
@@ -2549,8 +2564,8 @@
(define_insn "alsl<mode>3"
[(set (match_operand:GPR 0 "register_operand" "=r")
(plus:GPR (ashift:GPR (match_operand:GPR 1 "register_operand" "r")
- (match_operand 2 "const_immlsa_operand" ""))
- (match_operand:GPR 3 "register_operand" "r")))]
+ (match_operand 2 "const_immlsa_operand" ""))
+ (match_operand:GPR 3 "register_operand" "r")))]
""
"alsl.<d>\t%0,%1,%3,%2"
[(set_attr "type" "arith")
diff --git a/gcc/config/loongarch/predicates.md b/gcc/config/loongarch/predicates.md
index 1a8ab26d21e..be07887915d 100644
--- a/gcc/config/loongarch/predicates.md
+++ b/gcc/config/loongarch/predicates.md
@@ -252,25 +252,10 @@
(and (match_code "const_int")
(match_test "UINTVAL (op) == 0xffffffff")))
-(define_predicate "and_load_operand"
- (ior (match_operand 0 "qi_mask_operand")
- (match_operand 0 "hi_mask_operand")
- (match_operand 0 "si_mask_operand")))
-
(define_predicate "low_bitmask_operand"
(and (match_code "const_int")
(match_test "low_bitmask_len (mode, INTVAL (op)) > 12")))
-(define_predicate "and_reg_operand"
- (ior (match_operand 0 "register_operand")
- (match_operand 0 "const_uns_arith_operand")
- (match_operand 0 "low_bitmask_operand")
- (match_operand 0 "si_mask_operand")))
-
-(define_predicate "and_operand"
- (ior (match_operand 0 "and_load_operand")
- (match_operand 0 "and_reg_operand")))
-
(define_predicate "d_operand"
(and (match_code "reg")
(match_test "GP_REG_P (REGNO (op))"))) |
大家辛苦了! |
loongson/build-tools#12
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