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uart.rs
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/
uart.rs
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/* automatically generated by rust-bindgen 0.58.1 */
use
super::*;
#[repr(C)]
#[derive(Copy, Clone, Debug, Default, Eq, Hash, Ord, PartialEq, PartialOrd)]
pub struct __BindgenBitfieldUnit<Storage> {
storage: Storage,
}
impl<Storage> __BindgenBitfieldUnit<Storage> {
#[inline]
pub const fn new(storage: Storage) -> Self {
Self { storage }
}
}
impl<Storage> __BindgenBitfieldUnit<Storage>
where
Storage: AsRef<[u8]> + AsMut<[u8]>,
{
#[inline]
pub fn get_bit(&self, index: usize) -> bool {
debug_assert!(index / 8 < self.storage.as_ref().len());
let byte_index = index / 8;
let byte = self.storage.as_ref()[byte_index];
let bit_index = if cfg!(target_endian = "big") {
7 - (index % 8)
} else {
index % 8
};
let mask = 1 << bit_index;
byte & mask == mask
}
#[inline]
pub fn set_bit(&mut self, index: usize, val: bool) {
debug_assert!(index / 8 < self.storage.as_ref().len());
let byte_index = index / 8;
let byte = &mut self.storage.as_mut()[byte_index];
let bit_index = if cfg!(target_endian = "big") {
7 - (index % 8)
} else {
index % 8
};
let mask = 1 << bit_index;
if val {
*byte |= mask;
} else {
*byte &= !mask;
}
}
#[inline]
pub fn get(&self, bit_offset: usize, bit_width: u8) -> u64 {
debug_assert!(bit_width <= 64);
debug_assert!(bit_offset / 8 < self.storage.as_ref().len());
debug_assert!((bit_offset + (bit_width as usize)) / 8 <= self.storage.as_ref().len());
let mut val = 0;
for i in 0..(bit_width as usize) {
if self.get_bit(i + bit_offset) {
let index = if cfg!(target_endian = "big") {
bit_width as usize - 1 - i
} else {
i
};
val |= 1 << index;
}
}
val
}
#[inline]
pub fn set(&mut self, bit_offset: usize, bit_width: u8, val: u64) {
debug_assert!(bit_width <= 64);
debug_assert!(bit_offset / 8 < self.storage.as_ref().len());
debug_assert!((bit_offset + (bit_width as usize)) / 8 <= self.storage.as_ref().len());
for i in 0..(bit_width as usize) {
let mask = 1 << i;
let val_bit_is_set = val & mask == mask;
let index = if cfg!(target_endian = "big") {
bit_width as usize - 1 - i
} else {
i
};
self.set_bit(index + bit_offset, val_bit_is_set);
}
}
}
pub const UART_UTX_CONFIG_OFFSET: u32 = 0;
pub const UART_CR_UTX_EN_POS: u32 = 0;
pub const UART_CR_UTX_EN_LEN: u32 = 1;
pub const UART_CR_UTX_EN_MSK: u32 = 1;
pub const UART_CR_UTX_EN_UMSK: i32 = -2;
pub const UART_CR_UTX_CTS_EN_POS: u32 = 1;
pub const UART_CR_UTX_CTS_EN_LEN: u32 = 1;
pub const UART_CR_UTX_CTS_EN_MSK: u32 = 2;
pub const UART_CR_UTX_CTS_EN_UMSK: i32 = -3;
pub const UART_CR_UTX_FRM_EN_POS: u32 = 2;
pub const UART_CR_UTX_FRM_EN_LEN: u32 = 1;
pub const UART_CR_UTX_FRM_EN_MSK: u32 = 4;
pub const UART_CR_UTX_FRM_EN_UMSK: i32 = -5;
pub const UART_CR_UTX_PRT_EN_POS: u32 = 4;
pub const UART_CR_UTX_PRT_EN_LEN: u32 = 1;
pub const UART_CR_UTX_PRT_EN_MSK: u32 = 16;
pub const UART_CR_UTX_PRT_EN_UMSK: i32 = -17;
pub const UART_CR_UTX_PRT_SEL_POS: u32 = 5;
pub const UART_CR_UTX_PRT_SEL_LEN: u32 = 1;
pub const UART_CR_UTX_PRT_SEL_MSK: u32 = 32;
pub const UART_CR_UTX_PRT_SEL_UMSK: i32 = -33;
pub const UART_CR_UTX_IR_EN_POS: u32 = 6;
pub const UART_CR_UTX_IR_EN_LEN: u32 = 1;
pub const UART_CR_UTX_IR_EN_MSK: u32 = 64;
pub const UART_CR_UTX_IR_EN_UMSK: i32 = -65;
pub const UART_CR_UTX_IR_INV_POS: u32 = 7;
pub const UART_CR_UTX_IR_INV_LEN: u32 = 1;
pub const UART_CR_UTX_IR_INV_MSK: u32 = 128;
pub const UART_CR_UTX_IR_INV_UMSK: i32 = -129;
pub const UART_CR_UTX_BIT_CNT_D_POS: u32 = 8;
pub const UART_CR_UTX_BIT_CNT_D_LEN: u32 = 3;
pub const UART_CR_UTX_BIT_CNT_D_MSK: u32 = 1792;
pub const UART_CR_UTX_BIT_CNT_D_UMSK: i32 = -1793;
pub const UART_CR_UTX_BIT_CNT_P_POS: u32 = 12;
pub const UART_CR_UTX_BIT_CNT_P_LEN: u32 = 2;
pub const UART_CR_UTX_BIT_CNT_P_MSK: u32 = 12288;
pub const UART_CR_UTX_BIT_CNT_P_UMSK: i32 = -12289;
pub const UART_CR_UTX_LEN_POS: u32 = 16;
pub const UART_CR_UTX_LEN_LEN: u32 = 16;
pub const UART_CR_UTX_LEN_MSK: u32 = 4294901760;
pub const UART_CR_UTX_LEN_UMSK: i64 = -4294901761;
pub const UART_URX_CONFIG_OFFSET: u32 = 4;
pub const UART_CR_URX_EN_POS: u32 = 0;
pub const UART_CR_URX_EN_LEN: u32 = 1;
pub const UART_CR_URX_EN_MSK: u32 = 1;
pub const UART_CR_URX_EN_UMSK: i32 = -2;
pub const UART_CR_URX_RTS_SW_MODE_POS: u32 = 1;
pub const UART_CR_URX_RTS_SW_MODE_LEN: u32 = 1;
pub const UART_CR_URX_RTS_SW_MODE_MSK: u32 = 2;
pub const UART_CR_URX_RTS_SW_MODE_UMSK: i32 = -3;
pub const UART_CR_URX_RTS_SW_VAL_POS: u32 = 2;
pub const UART_CR_URX_RTS_SW_VAL_LEN: u32 = 1;
pub const UART_CR_URX_RTS_SW_VAL_MSK: u32 = 4;
pub const UART_CR_URX_RTS_SW_VAL_UMSK: i32 = -5;
pub const UART_CR_URX_ABR_EN_POS: u32 = 3;
pub const UART_CR_URX_ABR_EN_LEN: u32 = 1;
pub const UART_CR_URX_ABR_EN_MSK: u32 = 8;
pub const UART_CR_URX_ABR_EN_UMSK: i32 = -9;
pub const UART_CR_URX_PRT_EN_POS: u32 = 4;
pub const UART_CR_URX_PRT_EN_LEN: u32 = 1;
pub const UART_CR_URX_PRT_EN_MSK: u32 = 16;
pub const UART_CR_URX_PRT_EN_UMSK: i32 = -17;
pub const UART_CR_URX_PRT_SEL_POS: u32 = 5;
pub const UART_CR_URX_PRT_SEL_LEN: u32 = 1;
pub const UART_CR_URX_PRT_SEL_MSK: u32 = 32;
pub const UART_CR_URX_PRT_SEL_UMSK: i32 = -33;
pub const UART_CR_URX_IR_EN_POS: u32 = 6;
pub const UART_CR_URX_IR_EN_LEN: u32 = 1;
pub const UART_CR_URX_IR_EN_MSK: u32 = 64;
pub const UART_CR_URX_IR_EN_UMSK: i32 = -65;
pub const UART_CR_URX_IR_INV_POS: u32 = 7;
pub const UART_CR_URX_IR_INV_LEN: u32 = 1;
pub const UART_CR_URX_IR_INV_MSK: u32 = 128;
pub const UART_CR_URX_IR_INV_UMSK: i32 = -129;
pub const UART_CR_URX_BIT_CNT_D_POS: u32 = 8;
pub const UART_CR_URX_BIT_CNT_D_LEN: u32 = 3;
pub const UART_CR_URX_BIT_CNT_D_MSK: u32 = 1792;
pub const UART_CR_URX_BIT_CNT_D_UMSK: i32 = -1793;
pub const UART_CR_URX_DEG_EN_POS: u32 = 11;
pub const UART_CR_URX_DEG_EN_LEN: u32 = 1;
pub const UART_CR_URX_DEG_EN_MSK: u32 = 2048;
pub const UART_CR_URX_DEG_EN_UMSK: i32 = -2049;
pub const UART_CR_URX_DEG_CNT_POS: u32 = 12;
pub const UART_CR_URX_DEG_CNT_LEN: u32 = 4;
pub const UART_CR_URX_DEG_CNT_MSK: u32 = 61440;
pub const UART_CR_URX_DEG_CNT_UMSK: i32 = -61441;
pub const UART_CR_URX_LEN_POS: u32 = 16;
pub const UART_CR_URX_LEN_LEN: u32 = 16;
pub const UART_CR_URX_LEN_MSK: u32 = 4294901760;
pub const UART_CR_URX_LEN_UMSK: i64 = -4294901761;
pub const UART_BIT_PRD_OFFSET: u32 = 8;
pub const UART_CR_UTX_BIT_PRD_POS: u32 = 0;
pub const UART_CR_UTX_BIT_PRD_LEN: u32 = 16;
pub const UART_CR_UTX_BIT_PRD_MSK: u32 = 65535;
pub const UART_CR_UTX_BIT_PRD_UMSK: i32 = -65536;
pub const UART_CR_URX_BIT_PRD_POS: u32 = 16;
pub const UART_CR_URX_BIT_PRD_LEN: u32 = 16;
pub const UART_CR_URX_BIT_PRD_MSK: u32 = 4294901760;
pub const UART_CR_URX_BIT_PRD_UMSK: i64 = -4294901761;
pub const UART_DATA_CONFIG_OFFSET: u32 = 12;
pub const UART_CR_UART_BIT_INV_POS: u32 = 0;
pub const UART_CR_UART_BIT_INV_LEN: u32 = 1;
pub const UART_CR_UART_BIT_INV_MSK: u32 = 1;
pub const UART_CR_UART_BIT_INV_UMSK: i32 = -2;
pub const UART_UTX_IR_POSITION_OFFSET: u32 = 16;
pub const UART_CR_UTX_IR_POS_S_POS: u32 = 0;
pub const UART_CR_UTX_IR_POS_S_LEN: u32 = 16;
pub const UART_CR_UTX_IR_POS_S_MSK: u32 = 65535;
pub const UART_CR_UTX_IR_POS_S_UMSK: i32 = -65536;
pub const UART_CR_UTX_IR_POS_P_POS: u32 = 16;
pub const UART_CR_UTX_IR_POS_P_LEN: u32 = 16;
pub const UART_CR_UTX_IR_POS_P_MSK: u32 = 4294901760;
pub const UART_CR_UTX_IR_POS_P_UMSK: i64 = -4294901761;
pub const UART_URX_IR_POSITION_OFFSET: u32 = 20;
pub const UART_CR_URX_IR_POS_S_POS: u32 = 0;
pub const UART_CR_URX_IR_POS_S_LEN: u32 = 16;
pub const UART_CR_URX_IR_POS_S_MSK: u32 = 65535;
pub const UART_CR_URX_IR_POS_S_UMSK: i32 = -65536;
pub const UART_URX_RTO_TIMER_OFFSET: u32 = 24;
pub const UART_CR_URX_RTO_VALUE_POS: u32 = 0;
pub const UART_CR_URX_RTO_VALUE_LEN: u32 = 8;
pub const UART_CR_URX_RTO_VALUE_MSK: u32 = 255;
pub const UART_CR_URX_RTO_VALUE_UMSK: i32 = -256;
pub const UART_INT_STS_OFFSET: u32 = 32;
pub const UART_UTX_END_INT_POS: u32 = 0;
pub const UART_UTX_END_INT_LEN: u32 = 1;
pub const UART_UTX_END_INT_MSK: u32 = 1;
pub const UART_UTX_END_INT_UMSK: i32 = -2;
pub const UART_URX_END_INT_POS: u32 = 1;
pub const UART_URX_END_INT_LEN: u32 = 1;
pub const UART_URX_END_INT_MSK: u32 = 2;
pub const UART_URX_END_INT_UMSK: i32 = -3;
pub const UART_UTX_FIFO_INT_POS: u32 = 2;
pub const UART_UTX_FIFO_INT_LEN: u32 = 1;
pub const UART_UTX_FIFO_INT_MSK: u32 = 4;
pub const UART_UTX_FIFO_INT_UMSK: i32 = -5;
pub const UART_URX_FIFO_INT_POS: u32 = 3;
pub const UART_URX_FIFO_INT_LEN: u32 = 1;
pub const UART_URX_FIFO_INT_MSK: u32 = 8;
pub const UART_URX_FIFO_INT_UMSK: i32 = -9;
pub const UART_URX_RTO_INT_POS: u32 = 4;
pub const UART_URX_RTO_INT_LEN: u32 = 1;
pub const UART_URX_RTO_INT_MSK: u32 = 16;
pub const UART_URX_RTO_INT_UMSK: i32 = -17;
pub const UART_URX_PCE_INT_POS: u32 = 5;
pub const UART_URX_PCE_INT_LEN: u32 = 1;
pub const UART_URX_PCE_INT_MSK: u32 = 32;
pub const UART_URX_PCE_INT_UMSK: i32 = -33;
pub const UART_UTX_FER_INT_POS: u32 = 6;
pub const UART_UTX_FER_INT_LEN: u32 = 1;
pub const UART_UTX_FER_INT_MSK: u32 = 64;
pub const UART_UTX_FER_INT_UMSK: i32 = -65;
pub const UART_URX_FER_INT_POS: u32 = 7;
pub const UART_URX_FER_INT_LEN: u32 = 1;
pub const UART_URX_FER_INT_MSK: u32 = 128;
pub const UART_URX_FER_INT_UMSK: i32 = -129;
pub const UART_INT_MASK_OFFSET: u32 = 36;
pub const UART_CR_UTX_END_MASK_POS: u32 = 0;
pub const UART_CR_UTX_END_MASK_LEN: u32 = 1;
pub const UART_CR_UTX_END_MASK_MSK: u32 = 1;
pub const UART_CR_UTX_END_MASK_UMSK: i32 = -2;
pub const UART_CR_URX_END_MASK_POS: u32 = 1;
pub const UART_CR_URX_END_MASK_LEN: u32 = 1;
pub const UART_CR_URX_END_MASK_MSK: u32 = 2;
pub const UART_CR_URX_END_MASK_UMSK: i32 = -3;
pub const UART_CR_UTX_FIFO_MASK_POS: u32 = 2;
pub const UART_CR_UTX_FIFO_MASK_LEN: u32 = 1;
pub const UART_CR_UTX_FIFO_MASK_MSK: u32 = 4;
pub const UART_CR_UTX_FIFO_MASK_UMSK: i32 = -5;
pub const UART_CR_URX_FIFO_MASK_POS: u32 = 3;
pub const UART_CR_URX_FIFO_MASK_LEN: u32 = 1;
pub const UART_CR_URX_FIFO_MASK_MSK: u32 = 8;
pub const UART_CR_URX_FIFO_MASK_UMSK: i32 = -9;
pub const UART_CR_URX_RTO_MASK_POS: u32 = 4;
pub const UART_CR_URX_RTO_MASK_LEN: u32 = 1;
pub const UART_CR_URX_RTO_MASK_MSK: u32 = 16;
pub const UART_CR_URX_RTO_MASK_UMSK: i32 = -17;
pub const UART_CR_URX_PCE_MASK_POS: u32 = 5;
pub const UART_CR_URX_PCE_MASK_LEN: u32 = 1;
pub const UART_CR_URX_PCE_MASK_MSK: u32 = 32;
pub const UART_CR_URX_PCE_MASK_UMSK: i32 = -33;
pub const UART_CR_UTX_FER_MASK_POS: u32 = 6;
pub const UART_CR_UTX_FER_MASK_LEN: u32 = 1;
pub const UART_CR_UTX_FER_MASK_MSK: u32 = 64;
pub const UART_CR_UTX_FER_MASK_UMSK: i32 = -65;
pub const UART_CR_URX_FER_MASK_POS: u32 = 7;
pub const UART_CR_URX_FER_MASK_LEN: u32 = 1;
pub const UART_CR_URX_FER_MASK_MSK: u32 = 128;
pub const UART_CR_URX_FER_MASK_UMSK: i32 = -129;
pub const UART_INT_CLEAR_OFFSET: u32 = 40;
pub const UART_CR_UTX_END_CLR_POS: u32 = 0;
pub const UART_CR_UTX_END_CLR_LEN: u32 = 1;
pub const UART_CR_UTX_END_CLR_MSK: u32 = 1;
pub const UART_CR_UTX_END_CLR_UMSK: i32 = -2;
pub const UART_CR_URX_END_CLR_POS: u32 = 1;
pub const UART_CR_URX_END_CLR_LEN: u32 = 1;
pub const UART_CR_URX_END_CLR_MSK: u32 = 2;
pub const UART_CR_URX_END_CLR_UMSK: i32 = -3;
pub const UART_CR_URX_RTO_CLR_POS: u32 = 4;
pub const UART_CR_URX_RTO_CLR_LEN: u32 = 1;
pub const UART_CR_URX_RTO_CLR_MSK: u32 = 16;
pub const UART_CR_URX_RTO_CLR_UMSK: i32 = -17;
pub const UART_CR_URX_PCE_CLR_POS: u32 = 5;
pub const UART_CR_URX_PCE_CLR_LEN: u32 = 1;
pub const UART_CR_URX_PCE_CLR_MSK: u32 = 32;
pub const UART_CR_URX_PCE_CLR_UMSK: i32 = -33;
pub const UART_INT_EN_OFFSET: u32 = 44;
pub const UART_CR_UTX_END_EN_POS: u32 = 0;
pub const UART_CR_UTX_END_EN_LEN: u32 = 1;
pub const UART_CR_UTX_END_EN_MSK: u32 = 1;
pub const UART_CR_UTX_END_EN_UMSK: i32 = -2;
pub const UART_CR_URX_END_EN_POS: u32 = 1;
pub const UART_CR_URX_END_EN_LEN: u32 = 1;
pub const UART_CR_URX_END_EN_MSK: u32 = 2;
pub const UART_CR_URX_END_EN_UMSK: i32 = -3;
pub const UART_CR_UTX_FIFO_EN_POS: u32 = 2;
pub const UART_CR_UTX_FIFO_EN_LEN: u32 = 1;
pub const UART_CR_UTX_FIFO_EN_MSK: u32 = 4;
pub const UART_CR_UTX_FIFO_EN_UMSK: i32 = -5;
pub const UART_CR_URX_FIFO_EN_POS: u32 = 3;
pub const UART_CR_URX_FIFO_EN_LEN: u32 = 1;
pub const UART_CR_URX_FIFO_EN_MSK: u32 = 8;
pub const UART_CR_URX_FIFO_EN_UMSK: i32 = -9;
pub const UART_CR_URX_RTO_EN_POS: u32 = 4;
pub const UART_CR_URX_RTO_EN_LEN: u32 = 1;
pub const UART_CR_URX_RTO_EN_MSK: u32 = 16;
pub const UART_CR_URX_RTO_EN_UMSK: i32 = -17;
pub const UART_CR_URX_PCE_EN_POS: u32 = 5;
pub const UART_CR_URX_PCE_EN_LEN: u32 = 1;
pub const UART_CR_URX_PCE_EN_MSK: u32 = 32;
pub const UART_CR_URX_PCE_EN_UMSK: i32 = -33;
pub const UART_CR_UTX_FER_EN_POS: u32 = 6;
pub const UART_CR_UTX_FER_EN_LEN: u32 = 1;
pub const UART_CR_UTX_FER_EN_MSK: u32 = 64;
pub const UART_CR_UTX_FER_EN_UMSK: i32 = -65;
pub const UART_CR_URX_FER_EN_POS: u32 = 7;
pub const UART_CR_URX_FER_EN_LEN: u32 = 1;
pub const UART_CR_URX_FER_EN_MSK: u32 = 128;
pub const UART_CR_URX_FER_EN_UMSK: i32 = -129;
pub const UART_STATUS_OFFSET: u32 = 48;
pub const UART_STS_UTX_BUS_BUSY_POS: u32 = 0;
pub const UART_STS_UTX_BUS_BUSY_LEN: u32 = 1;
pub const UART_STS_UTX_BUS_BUSY_MSK: u32 = 1;
pub const UART_STS_UTX_BUS_BUSY_UMSK: i32 = -2;
pub const UART_STS_URX_BUS_BUSY_POS: u32 = 1;
pub const UART_STS_URX_BUS_BUSY_LEN: u32 = 1;
pub const UART_STS_URX_BUS_BUSY_MSK: u32 = 2;
pub const UART_STS_URX_BUS_BUSY_UMSK: i32 = -3;
pub const UART_STS_URX_ABR_PRD_OFFSET: u32 = 52;
pub const UART_STS_URX_ABR_PRD_START_POS: u32 = 0;
pub const UART_STS_URX_ABR_PRD_START_LEN: u32 = 16;
pub const UART_STS_URX_ABR_PRD_START_MSK: u32 = 65535;
pub const UART_STS_URX_ABR_PRD_START_UMSK: i32 = -65536;
pub const UART_STS_URX_ABR_PRD_0X55_POS: u32 = 16;
pub const UART_STS_URX_ABR_PRD_0X55_LEN: u32 = 16;
pub const UART_STS_URX_ABR_PRD_0X55_MSK: u32 = 4294901760;
pub const UART_STS_URX_ABR_PRD_0X55_UMSK: i64 = -4294901761;
pub const UART_FIFO_CONFIG_0_OFFSET: u32 = 128;
pub const UART_DMA_TX_EN_POS: u32 = 0;
pub const UART_DMA_TX_EN_LEN: u32 = 1;
pub const UART_DMA_TX_EN_MSK: u32 = 1;
pub const UART_DMA_TX_EN_UMSK: i32 = -2;
pub const UART_DMA_RX_EN_POS: u32 = 1;
pub const UART_DMA_RX_EN_LEN: u32 = 1;
pub const UART_DMA_RX_EN_MSK: u32 = 2;
pub const UART_DMA_RX_EN_UMSK: i32 = -3;
pub const UART_TX_FIFO_CLR_POS: u32 = 2;
pub const UART_TX_FIFO_CLR_LEN: u32 = 1;
pub const UART_TX_FIFO_CLR_MSK: u32 = 4;
pub const UART_TX_FIFO_CLR_UMSK: i32 = -5;
pub const UART_RX_FIFO_CLR_POS: u32 = 3;
pub const UART_RX_FIFO_CLR_LEN: u32 = 1;
pub const UART_RX_FIFO_CLR_MSK: u32 = 8;
pub const UART_RX_FIFO_CLR_UMSK: i32 = -9;
pub const UART_TX_FIFO_OVERFLOW_POS: u32 = 4;
pub const UART_TX_FIFO_OVERFLOW_LEN: u32 = 1;
pub const UART_TX_FIFO_OVERFLOW_MSK: u32 = 16;
pub const UART_TX_FIFO_OVERFLOW_UMSK: i32 = -17;
pub const UART_TX_FIFO_UNDERFLOW_POS: u32 = 5;
pub const UART_TX_FIFO_UNDERFLOW_LEN: u32 = 1;
pub const UART_TX_FIFO_UNDERFLOW_MSK: u32 = 32;
pub const UART_TX_FIFO_UNDERFLOW_UMSK: i32 = -33;
pub const UART_RX_FIFO_OVERFLOW_POS: u32 = 6;
pub const UART_RX_FIFO_OVERFLOW_LEN: u32 = 1;
pub const UART_RX_FIFO_OVERFLOW_MSK: u32 = 64;
pub const UART_RX_FIFO_OVERFLOW_UMSK: i32 = -65;
pub const UART_RX_FIFO_UNDERFLOW_POS: u32 = 7;
pub const UART_RX_FIFO_UNDERFLOW_LEN: u32 = 1;
pub const UART_RX_FIFO_UNDERFLOW_MSK: u32 = 128;
pub const UART_RX_FIFO_UNDERFLOW_UMSK: i32 = -129;
pub const UART_FIFO_CONFIG_1_OFFSET: u32 = 132;
pub const UART_TX_FIFO_CNT_POS: u32 = 0;
pub const UART_TX_FIFO_CNT_LEN: u32 = 6;
pub const UART_TX_FIFO_CNT_MSK: u32 = 63;
pub const UART_TX_FIFO_CNT_UMSK: i32 = -64;
pub const UART_RX_FIFO_CNT_POS: u32 = 8;
pub const UART_RX_FIFO_CNT_LEN: u32 = 6;
pub const UART_RX_FIFO_CNT_MSK: u32 = 16128;
pub const UART_RX_FIFO_CNT_UMSK: i32 = -16129;
pub const UART_TX_FIFO_TH_POS: u32 = 16;
pub const UART_TX_FIFO_TH_LEN: u32 = 5;
pub const UART_TX_FIFO_TH_MSK: u32 = 2031616;
pub const UART_TX_FIFO_TH_UMSK: i32 = -2031617;
pub const UART_RX_FIFO_TH_POS: u32 = 24;
pub const UART_RX_FIFO_TH_LEN: u32 = 5;
pub const UART_RX_FIFO_TH_MSK: u32 = 520093696;
pub const UART_RX_FIFO_TH_UMSK: i32 = -520093697;
pub const UART_FIFO_WDATA_OFFSET: u32 = 136;
pub const UART_FIFO_WDATA_POS: u32 = 0;
pub const UART_FIFO_WDATA_LEN: u32 = 8;
pub const UART_FIFO_WDATA_MSK: u32 = 255;
pub const UART_FIFO_WDATA_UMSK: i32 = -256;
pub const UART_FIFO_RDATA_OFFSET: u32 = 140;
pub const UART_FIFO_RDATA_POS: u32 = 0;
pub const UART_FIFO_RDATA_LEN: u32 = 8;
pub const UART_FIFO_RDATA_MSK: u32 = 255;
pub const UART_FIFO_RDATA_UMSK: i32 = -256;
pub const UART_RX_FIFO_SIZE: u32 = 32;
pub const UART_TX_FIFO_SIZE: u32 = 32;
pub const UART_DEFAULT_RECV_TIMEOUT: u32 = 80;
pub const BL_UART_BUFFER_SIZE_MIN: u32 = 128;
pub const BL_UART_BUFFER_SIZE_MASK: u32 = 127;
pub type __uint8_t = ::cty::c_uchar;
pub type __uint16_t = ::cty::c_ushort;
pub type __uint32_t = ::cty::c_uint;
#[repr(C)]
#[derive(Copy, Clone)]
pub struct uart_reg {
pub utx_config: uart_reg__bindgen_ty_1,
pub urx_config: uart_reg__bindgen_ty_2,
pub uart_bit_prd: uart_reg__bindgen_ty_3,
pub data_config: uart_reg__bindgen_ty_4,
pub utx_ir_position: uart_reg__bindgen_ty_5,
pub urx_ir_position: uart_reg__bindgen_ty_6,
pub urx_rto_timer: uart_reg__bindgen_ty_7,
pub RESERVED0x1c: [u8; 4usize],
pub uart_int_sts: uart_reg__bindgen_ty_8,
pub uart_int_mask: uart_reg__bindgen_ty_9,
pub uart_int_clear: uart_reg__bindgen_ty_10,
pub uart_int_en: uart_reg__bindgen_ty_11,
pub uart_status: uart_reg__bindgen_ty_12,
pub sts_urx_abr_prd: uart_reg__bindgen_ty_13,
pub RESERVED0x38: [u8; 72usize],
pub uart_fifo_config_0: uart_reg__bindgen_ty_14,
pub uart_fifo_config_1: uart_reg__bindgen_ty_15,
pub uart_fifo_wdata: uart_reg__bindgen_ty_16,
pub uart_fifo_rdata: uart_reg__bindgen_ty_17,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union uart_reg__bindgen_ty_1 {
pub BF: uart_reg__bindgen_ty_1__bindgen_ty_1,
pub WORD: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Default, Copy, Clone)]
pub struct uart_reg__bindgen_ty_1__bindgen_ty_1 {
pub _bitfield_align_1: [u16; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl uart_reg__bindgen_ty_1__bindgen_ty_1 {
#[inline]
pub fn cr_utx_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_cr_utx_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn cr_utx_cts_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_cr_utx_cts_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn cr_utx_frm_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_cr_utx_frm_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved_3(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_reserved_3(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn cr_utx_prt_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_cr_utx_prt_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn cr_utx_prt_sel(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_cr_utx_prt_sel(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn cr_utx_ir_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_cr_utx_ir_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn cr_utx_ir_inv(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_cr_utx_ir_inv(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn cr_utx_bit_cnt_d(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 3u8) as u32) }
}
#[inline]
pub fn set_cr_utx_bit_cnt_d(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 3u8, val as u64)
}
}
#[inline]
pub fn reserved_11(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_reserved_11(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn cr_utx_bit_cnt_p(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 2u8) as u32) }
}
#[inline]
pub fn set_cr_utx_bit_cnt_p(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 2u8, val as u64)
}
}
#[inline]
pub fn reserved_14_15(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 2u8) as u32) }
}
#[inline]
pub fn set_reserved_14_15(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 2u8, val as u64)
}
}
#[inline]
pub fn cr_utx_len(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 16u8) as u32) }
}
#[inline]
pub fn set_cr_utx_len(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 16u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
cr_utx_en: u32,
cr_utx_cts_en: u32,
cr_utx_frm_en: u32,
reserved_3: u32,
cr_utx_prt_en: u32,
cr_utx_prt_sel: u32,
cr_utx_ir_en: u32,
cr_utx_ir_inv: u32,
cr_utx_bit_cnt_d: u32,
reserved_11: u32,
cr_utx_bit_cnt_p: u32,
reserved_14_15: u32,
cr_utx_len: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let cr_utx_en: u32 = unsafe { ::core::mem::transmute(cr_utx_en) };
cr_utx_en as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let cr_utx_cts_en: u32 = unsafe { ::core::mem::transmute(cr_utx_cts_en) };
cr_utx_cts_en as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let cr_utx_frm_en: u32 = unsafe { ::core::mem::transmute(cr_utx_frm_en) };
cr_utx_frm_en as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let reserved_3: u32 = unsafe { ::core::mem::transmute(reserved_3) };
reserved_3 as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let cr_utx_prt_en: u32 = unsafe { ::core::mem::transmute(cr_utx_prt_en) };
cr_utx_prt_en as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let cr_utx_prt_sel: u32 = unsafe { ::core::mem::transmute(cr_utx_prt_sel) };
cr_utx_prt_sel as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let cr_utx_ir_en: u32 = unsafe { ::core::mem::transmute(cr_utx_ir_en) };
cr_utx_ir_en as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let cr_utx_ir_inv: u32 = unsafe { ::core::mem::transmute(cr_utx_ir_inv) };
cr_utx_ir_inv as u64
});
__bindgen_bitfield_unit.set(8usize, 3u8, {
let cr_utx_bit_cnt_d: u32 = unsafe { ::core::mem::transmute(cr_utx_bit_cnt_d) };
cr_utx_bit_cnt_d as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let reserved_11: u32 = unsafe { ::core::mem::transmute(reserved_11) };
reserved_11 as u64
});
__bindgen_bitfield_unit.set(12usize, 2u8, {
let cr_utx_bit_cnt_p: u32 = unsafe { ::core::mem::transmute(cr_utx_bit_cnt_p) };
cr_utx_bit_cnt_p as u64
});
__bindgen_bitfield_unit.set(14usize, 2u8, {
let reserved_14_15: u32 = unsafe { ::core::mem::transmute(reserved_14_15) };
reserved_14_15 as u64
});
__bindgen_bitfield_unit.set(16usize, 16u8, {
let cr_utx_len: u32 = unsafe { ::core::mem::transmute(cr_utx_len) };
cr_utx_len as u64
});
__bindgen_bitfield_unit
}
}
impl Default for uart_reg__bindgen_ty_1 {
fn default() -> Self {
unsafe { ::core::mem::zeroed() }
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union uart_reg__bindgen_ty_2 {
pub BF: uart_reg__bindgen_ty_2__bindgen_ty_1,
pub WORD: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Default, Copy, Clone)]
pub struct uart_reg__bindgen_ty_2__bindgen_ty_1 {
pub _bitfield_align_1: [u16; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl uart_reg__bindgen_ty_2__bindgen_ty_1 {
#[inline]
pub fn cr_urx_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_cr_urx_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn cr_urx_rts_sw_mode(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_cr_urx_rts_sw_mode(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn cr_urx_rts_sw_val(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_cr_urx_rts_sw_val(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn cr_urx_abr_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_cr_urx_abr_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn cr_urx_prt_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_cr_urx_prt_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn cr_urx_prt_sel(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_cr_urx_prt_sel(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn cr_urx_ir_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_cr_urx_ir_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn cr_urx_ir_inv(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_cr_urx_ir_inv(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn cr_urx_bit_cnt_d(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 3u8) as u32) }
}
#[inline]
pub fn set_cr_urx_bit_cnt_d(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 3u8, val as u64)
}
}
#[inline]
pub fn cr_urx_deg_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_cr_urx_deg_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn cr_urx_deg_cnt(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 4u8) as u32) }
}
#[inline]
pub fn set_cr_urx_deg_cnt(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 4u8, val as u64)
}
}
#[inline]
pub fn cr_urx_len(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 16u8) as u32) }
}
#[inline]
pub fn set_cr_urx_len(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 16u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
cr_urx_en: u32,
cr_urx_rts_sw_mode: u32,
cr_urx_rts_sw_val: u32,
cr_urx_abr_en: u32,
cr_urx_prt_en: u32,
cr_urx_prt_sel: u32,
cr_urx_ir_en: u32,
cr_urx_ir_inv: u32,
cr_urx_bit_cnt_d: u32,
cr_urx_deg_en: u32,
cr_urx_deg_cnt: u32,
cr_urx_len: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let cr_urx_en: u32 = unsafe { ::core::mem::transmute(cr_urx_en) };
cr_urx_en as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let cr_urx_rts_sw_mode: u32 = unsafe { ::core::mem::transmute(cr_urx_rts_sw_mode) };
cr_urx_rts_sw_mode as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let cr_urx_rts_sw_val: u32 = unsafe { ::core::mem::transmute(cr_urx_rts_sw_val) };
cr_urx_rts_sw_val as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let cr_urx_abr_en: u32 = unsafe { ::core::mem::transmute(cr_urx_abr_en) };
cr_urx_abr_en as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let cr_urx_prt_en: u32 = unsafe { ::core::mem::transmute(cr_urx_prt_en) };
cr_urx_prt_en as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let cr_urx_prt_sel: u32 = unsafe { ::core::mem::transmute(cr_urx_prt_sel) };
cr_urx_prt_sel as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let cr_urx_ir_en: u32 = unsafe { ::core::mem::transmute(cr_urx_ir_en) };
cr_urx_ir_en as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let cr_urx_ir_inv: u32 = unsafe { ::core::mem::transmute(cr_urx_ir_inv) };
cr_urx_ir_inv as u64
});
__bindgen_bitfield_unit.set(8usize, 3u8, {
let cr_urx_bit_cnt_d: u32 = unsafe { ::core::mem::transmute(cr_urx_bit_cnt_d) };
cr_urx_bit_cnt_d as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let cr_urx_deg_en: u32 = unsafe { ::core::mem::transmute(cr_urx_deg_en) };
cr_urx_deg_en as u64
});
__bindgen_bitfield_unit.set(12usize, 4u8, {
let cr_urx_deg_cnt: u32 = unsafe { ::core::mem::transmute(cr_urx_deg_cnt) };
cr_urx_deg_cnt as u64
});
__bindgen_bitfield_unit.set(16usize, 16u8, {
let cr_urx_len: u32 = unsafe { ::core::mem::transmute(cr_urx_len) };
cr_urx_len as u64
});
__bindgen_bitfield_unit
}
}
impl Default for uart_reg__bindgen_ty_2 {
fn default() -> Self {
unsafe { ::core::mem::zeroed() }
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union uart_reg__bindgen_ty_3 {
pub BF: uart_reg__bindgen_ty_3__bindgen_ty_1,
pub WORD: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Default, Copy, Clone)]
pub struct uart_reg__bindgen_ty_3__bindgen_ty_1 {
pub _bitfield_align_1: [u16; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl uart_reg__bindgen_ty_3__bindgen_ty_1 {
#[inline]
pub fn cr_utx_bit_prd(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 16u8) as u32) }
}
#[inline]
pub fn set_cr_utx_bit_prd(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 16u8, val as u64)
}
}
#[inline]
pub fn cr_urx_bit_prd(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 16u8) as u32) }
}
#[inline]
pub fn set_cr_urx_bit_prd(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 16u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
cr_utx_bit_prd: u32,
cr_urx_bit_prd: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 16u8, {
let cr_utx_bit_prd: u32 = unsafe { ::core::mem::transmute(cr_utx_bit_prd) };
cr_utx_bit_prd as u64
});
__bindgen_bitfield_unit.set(16usize, 16u8, {
let cr_urx_bit_prd: u32 = unsafe { ::core::mem::transmute(cr_urx_bit_prd) };
cr_urx_bit_prd as u64
});
__bindgen_bitfield_unit
}
}
impl Default for uart_reg__bindgen_ty_3 {
fn default() -> Self {
unsafe { ::core::mem::zeroed() }
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union uart_reg__bindgen_ty_4 {
pub BF: uart_reg__bindgen_ty_4__bindgen_ty_1,
pub WORD: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Default, Copy, Clone)]
pub struct uart_reg__bindgen_ty_4__bindgen_ty_1 {
pub _bitfield_align_1: [u32; 0],
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
}
impl uart_reg__bindgen_ty_4__bindgen_ty_1 {
#[inline]
pub fn cr_uart_bit_inv(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_cr_uart_bit_inv(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved_1_31(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 31u8) as u32) }
}
#[inline]
pub fn set_reserved_1_31(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 31u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
cr_uart_bit_inv: u32,
reserved_1_31: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize]> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let cr_uart_bit_inv: u32 = unsafe { ::core::mem::transmute(cr_uart_bit_inv) };
cr_uart_bit_inv as u64
});
__bindgen_bitfield_unit.set(1usize, 31u8, {
let reserved_1_31: u32 = unsafe { ::core::mem::transmute(reserved_1_31) };
reserved_1_31 as u64
});
__bindgen_bitfield_unit
}
}
impl Default for uart_reg__bindgen_ty_4 {
fn default() -> Self {
unsafe { ::core::mem::zeroed() }
}