/
boot_stub.elf.lst
2183 lines (2028 loc) · 85.1 KB
/
boot_stub.elf.lst
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/Users/Luppy/mynewt/stm32bluepill-mynewt-sensor/bin/targets/gd32vf103c-start_boot/app/apps/boot_stub/boot_stub.elf: file format elf32-littleriscv
/Users/Luppy/mynewt/stm32bluepill-mynewt-sensor/bin/targets/gd32vf103c-start_boot/app/apps/boot_stub/boot_stub.elf
architecture: riscv:rv32, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x0800015c
Program Header:
LOAD off 0x00001000 vaddr 0x08000000 paddr 0x08000000 align 2**12
filesz 0x00000c2c memsz 0x00000c2c flags r-x
LOAD off 0x00002000 vaddr 0x20000000 paddr 0x08000c2c align 2**12
filesz 0x00000040 memsz 0x00000040 flags rw-
LOAD off 0x00002800 vaddr 0x20004800 paddr 0x20004800 align 2**12
filesz 0x00000000 memsz 0x00000800 flags rw-
Sections:
Idx Name Size VMA LMA File off Algn Flags
0 .init 0000021c 08000000 08000000 00001000 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .text 000009ba 0800021c 0800021c 0000121c 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000054 08000bd8 08000bd8 00001bd8 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .lalign 00000000 08000c2c 08000c2c 00002040 2**0 CONTENTS
4 .dalign 00000000 20000000 20000000 00002040 2**0 CONTENTS
5 .data 0000003c 20000000 08000c2c 00002000 2**2 CONTENTS, ALLOC, LOAD, DATA
6 .sdata 00000004 2000003c 08000c68 0000203c 2**2 CONTENTS, ALLOC, LOAD, DATA
7 .bss 00000000 20000040 08000c6c 00000000 2**0 ALLOC
8 .stack 00000800 20004800 20004800 00002800 2**0 ALLOC
9 .debug_line 00009f97 00000000 00000000 00002040 2**0 CONTENTS, READONLY, DEBUGGING
10 .debug_info 0000940a 00000000 00000000 0000bfd7 2**0 CONTENTS, READONLY, DEBUGGING
11 .debug_abbrev 00001b5a 00000000 00000000 000153e1 2**0 CONTENTS, READONLY, DEBUGGING
12 .debug_aranges 00000910 00000000 00000000 00016f40 2**3 CONTENTS, READONLY, DEBUGGING
13 .debug_str 0000344e 00000000 00000000 00017850 2**0 CONTENTS, READONLY, DEBUGGING
14 .debug_loc 000033e5 00000000 00000000 0001ac9e 2**0 CONTENTS, READONLY, DEBUGGING
15 .debug_ranges 000007a8 00000000 00000000 0001e083 2**0 CONTENTS, READONLY, DEBUGGING
16 .comment 00000033 00000000 00000000 0001e82b 2**0 CONTENTS, READONLY
17 .debug_frame 000013f4 00000000 00000000 0001e860 2**2 CONTENTS, READONLY, DEBUGGING
SYMBOL TABLE:
08000000 l d .init 00000000 .init
0800021c l d .text 00000000 .text
08000bd8 l d .rodata 00000000 .rodata
08000c2c l d .lalign 00000000 .lalign
20000000 l d .dalign 00000000 .dalign
20000000 l d .data 00000000 .data
2000003c l d .sdata 00000000 .sdata
20000040 l d .bss 00000000 .bss
20004800 l d .stack 00000000 .stack
00000000 l d .debug_line 00000000 .debug_line
00000000 l d .debug_info 00000000 .debug_info
00000000 l d .debug_abbrev 00000000 .debug_abbrev
00000000 l d .debug_aranges 00000000 .debug_aranges
00000000 l d .debug_str 00000000 .debug_str
00000000 l d .debug_loc 00000000 .debug_loc
00000000 l d .debug_ranges 00000000 .debug_ranges
00000000 l d .comment 00000000 .comment
00000000 l d .debug_frame 00000000 .debug_frame
00000000 l df *ABS* 00000000 start.o
08000000 l .init 00000000 vector_base
08000182 l .init 00000000 _reset_handler_0800
00000000 l df *ABS* 00000000 system_gd32vf103.c
0800021c l F .text 000000e2 system_clock_108m_hxtal
080002fe l F .text 0000000c system_clock_config
00000000 l df *ABS* 00000000 fini.c
00000000 l df *ABS* 00000000 entry.o
0800039c l .text 00000000 service_loop
00000000 l df *ABS* 00000000 inline.c
00000000 l df *ABS* 00000000 start.c
00000000 l df *ABS* 00000000 boot.c
00000000 l df *ABS* 00000000 hal_bsp.c
00000000 l df *ABS* 00000000 hal_common.c
00000000 l df *ABS* 00000000 gd32vf103_periph.c
0800041a l F .text 00000036 gd32vf103_periph_create_timers
00000000 l df *ABS* 00000000 hal_system.c
00000000 l df *ABS* 00000000 hal_system_start.c
00000000 l df *ABS* 00000000 hal_timer.c
08000bd8 l O .rodata 0000000c gd32vf103_tmr_devs
00000000 l df *ABS* 00000000 gd32vf103_eclic.c
00000000 l df *ABS* 00000000 gd32vf103_rcu.c
00000000 l df *ABS* 00000000 gd32vf103_timer.c
00000000 l df *ABS* 00000000 n200_func.c
00000000 l df *ABS* 00000000 os_fault.c
00000000 l df *ABS* 00000000 os_cputime.c
00000000 l df *ABS* 00000000 gd32vf103c-start_boot-sysflash.c
2000083c g .sdata 00000000 __global_pointer$
08000472 g F .text 00000024 hal_timer_init
0800046c g F .text 00000006 hal_system_start
08000ae4 g F .text 0000000a eclic_get_cliccfg
08000460 g F .text 0000000c hal_system_reset
08000b0e g F .text 00000010 eclic_get_nlbits
08000aca g F .text 00000010 eclic_get_intctrl
00000800 g *ABS* 00000000 __stack_size
08000796 g F .text 00000216 timer_channel_output_config
2000083c g .sdata 00000000 _gp
08000a3c g F .text 00000064 timer_channel_output_shadow_config
20000014 g O .data 00000014 gd32vf103_tmr1
08000bc4 g F .text 00000012 os_cputime_init
00000000 g *ABS* 00000000 _imghdr_size
08000772 g F .text 0000000a timer_enable
2000003c g O .sdata 00000004 SystemCoreClock
080005be g F .text 0000001c rcu_periph_reset_disable
08000bba g F .text 0000000a __assert_func
0800036c w .text 00000000 irq_entry
0800045c g F .text 00000004 hal_debugger_connected
08000aba g F .text 00000010 eclic_set_intctrl
20000000 g O .data 00000014 gd32vf103_tmr0
08000ada g F .text 0000000a eclic_set_cliccfg
080003f0 g F .text 00000002 _init
0800069e g F .text 0000001c timer_struct_para_init
080006ba g F .text 000000b8 timer_init
080009ac g F .text 00000064 timer_channel_output_mode_config
08000b1e g F .text 0000004c eclic_set_irq_lvl_abs
08000aa8 g F .text 00000012 eclic_enable_interrupt
20000000 g .stack 00000000 _ram_start
0800015c g F .init 00000000 _reset_handler
20005000 g .stack 00000000 _sp
080003e4 g F .text 0000000c _start
0800058e g F .text 00000018 rcu_periph_clock_enable
08000214 g .init 00000000 enable_mcycle_minstret
080005da g F .text 000000c4 timer_deinit
08000aa0 g F .text 00000008 timer_interrupt_enable
08000496 g F .text 000000c8 hal_timer_config
08000450 g F .text 0000000c gd32vf103_periph_create
08000b6a g F .text 00000050 eclic_set_irq_priority
20000040 g .sdata 00000000 __bss_start
080003f2 g F .text 00000016 main
0800020e g .init 00000000 disable_mcycle_minstret
00000000 g .init 00000000 __text
08000aee g F .text 00000020 eclic_set_nlbits
0800030a g F .text 0000005e SystemInit
08000368 g F .text 00000002 _fini
080005a6 g F .text 00000018 rcu_periph_reset_enable
20000000 g .dalign 00000000 _data
08000be4 g O .rodata 00000048 sysflash_map_dflt
08000564 g F .text 0000002a eclic_irq_enable
20000040 g .sdata 00000000 _edata
20000040 g .sdata 00000000 _end
20000028 g O .data 00000014 gd32vf103_tmr2
0800055e g F .text 00000006 eclic_global_interrupt_enable
08000c2c g .lalign 00000000 _data_lma
080003de g F .text 00000006 exit
0800077c g F .text 0000001a timer_channel_output_struct_para_init
08000a10 g F .text 0000002c timer_channel_output_pulse_value_config
08000414 g F .text 00000006 _exit
08000408 g F .text 0000000c hal_bsp_init
Disassembly of section .init:
08000000 <vector_base>:
.weak CAN1_EWMC_IRQHandler
.weak USBFS_IRQHandler
vector_base:
/* Insert vector table at the start of ROM address 0x800 0000, similar to Arm */
j _reset_handler
8000000: aab1 j 800015c <_reset_handler>
8000002: 0001 nop
...
0800015c <_reset_handler>:
_reset_handler:
/* Called upon startup */
/* Disable Local/Timer/External interrupts */
csrc CSR_MSTATUS, MSTATUS_MIE
800015c: 30047073 csrci mstatus,8
/* Upon restart, program starts running at address 0x0, which is aliased to ROM address 0x800 0000.
We jump to the right ROM address 0x800 0000 so that RAM addressing works correctly. */
la a0, _reset_handler
8000160: 00000517 auipc a0,0x0
8000164: ffc50513 addi a0,a0,-4 # 800015c <_reset_handler>
li a1, 1
8000168: 4585 li a1,1
slli a1, a1, 29
800016a: 05f6 slli a1,a1,0x1d
bleu a1, a0, _reset_handler_0800
800016c: 00b57b63 bgeu a0,a1,8000182 <_reset_handler_0800>
srli a1, a1, 2
8000170: 8189 srli a1,a1,0x2
bleu a1, a0, _reset_handler_0800
8000172: 00b57863 bgeu a0,a1,8000182 <_reset_handler_0800>
la a0, _reset_handler_0800
8000176: 00000517 auipc a0,0x0
800017a: 00c50513 addi a0,a0,12 # 8000182 <_reset_handler_0800>
add a0, a0, a1
800017e: 952e add a0,a0,a1
jr a0
8000180: 8502 jr a0
08000182 <_reset_handler_0800>:
_reset_handler_0800:
/* We are now running at the right ROM address 0x800 0000 */
/* Set the the NMI base to share with mtvec by setting CSR_MMISC_CTL */
li t0, 0x200
8000182: 20000293 li t0,512
csrs CSR_MMISC_CTL, t0
8000186: 7d02a073 csrs 0x7d0,t0
/* Intialise the mtvt */
la t0, vector_base
800018a: 00000297 auipc t0,0x0
800018e: e7628293 addi t0,t0,-394 # 8000000 <vector_base>
csrw CSR_MTVT, t0
8000192: 30729073 csrw mtvt,t0
/* Intialise the mtvt2 and enable it */
la t0, irq_entry
8000196: 00000297 auipc t0,0x0
800019a: 1d628293 addi t0,t0,470 # 800036c <irq_entry>
csrw CSR_MTVT2, t0
800019e: 7ec29073 csrw 0x7ec,t0
csrs CSR_MTVT2, 0x1
80001a2: 7ec0e073 csrsi 0x7ec,1
csrw fcsr, x0
#endif
.option push
.option norelax
la gp, __global_pointer$
80001a6: 18000197 auipc gp,0x18000
80001aa: 69618193 addi gp,gp,1686 # 2000083c <__global_pointer$>
.option pop
la sp, _sp
80001ae: 18005117 auipc sp,0x18005
80001b2: e5210113 addi sp,sp,-430 # 20005000 <_sp>
/* Load data section */
la a0, _data_lma
80001b6: 00001517 auipc a0,0x1
80001ba: a7650513 addi a0,a0,-1418 # 8000c2c <_data_lma>
la a1, _data
80001be: 18000597 auipc a1,0x18000
80001c2: e4258593 addi a1,a1,-446 # 20000000 <_data>
la a2, _edata
80001c6: 18000617 auipc a2,0x18000
80001ca: e7a60613 addi a2,a2,-390 # 20000040 <__bss_start>
bgeu a1, a2, 2f
80001ce: 00c5fa63 bgeu a1,a2,80001e2 <_reset_handler_0800+0x60>
1:
lw t0, (a0)
80001d2: 00052283 lw t0,0(a0)
sw t0, (a1)
80001d6: 0055a023 sw t0,0(a1)
addi a0, a0, 4
80001da: 0511 addi a0,a0,4
addi a1, a1, 4
80001dc: 0591 addi a1,a1,4
bltu a1, a2, 1b
80001de: fec5eae3 bltu a1,a2,80001d2 <_reset_handler_0800+0x50>
2:
/* Clear bss section */
la a0, __bss_start
80001e2: 18000517 auipc a0,0x18000
80001e6: e5e50513 addi a0,a0,-418 # 20000040 <__bss_start>
la a1, _end
80001ea: 18000597 auipc a1,0x18000
80001ee: e5658593 addi a1,a1,-426 # 20000040 <__bss_start>
bgeu a0, a1, 2f
80001f2: 00b57763 bgeu a0,a1,8000200 <_reset_handler_0800+0x7e>
1:
sw zero, (a0)
80001f6: 00052023 sw zero,0(a0)
addi a0, a0, 4
80001fa: 0511 addi a0,a0,4
bltu a0, a1, 1b
80001fc: feb56de3 bltu a0,a1,80001f6 <_reset_handler_0800+0x74>
2:
/*enable mcycle_minstret*/
csrci CSR_MCOUNTINHIBIT, 0x5
8000200: 3202f073 csrci mucounteren,5
/* NOTUSED: Call global constructors
la a0, __libc_fini_array
call atexit
call __libc_init_array */
call SystemInit
8000204: 2219 jal 800030a <SystemInit>
call _start
8000206: 2af9 jal 80003e4 <_start>
call _fini
8000208: 2285 jal 8000368 <_fini>
tail exit
800020a: aad1 j 80003de <exit>
1:
j 1b
800020c: a001 j 800020c <_reset_handler_0800+0x8a>
0800020e <disable_mcycle_minstret>:
.global disable_mcycle_minstret
disable_mcycle_minstret:
csrsi CSR_MCOUNTINHIBIT, 0x5
800020e: 3202e073 csrsi mucounteren,5
ret
8000212: 8082 ret
08000214 <enable_mcycle_minstret>:
.global enable_mcycle_minstret
enable_mcycle_minstret:
csrci CSR_MCOUNTINHIBIT, 0x5
8000214: 3202f073 csrci mucounteren,5
ret
8000218: 8082 ret
...
Disassembly of section .text:
0800021c <system_clock_108m_hxtal>:
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable HXTAL */
RCU_CTL |= RCU_CTL_HXTALEN;
800021c: 40021737 lui a4,0x40021
8000220: 431c lw a5,0(a4)
8000222: 66c1 lui a3,0x10
8000224: 8fd5 or a5,a5,a3
8000226: c31c sw a5,0(a4)
uint32_t timeout = 0U;
8000228: 4781 li a5,0
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
do{
timeout++;
800022a: 0785 addi a5,a5,1
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
800022c: 40021737 lui a4,0x40021
8000230: 4318 lw a4,0(a4)
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
8000232: 00e71693 slli a3,a4,0xe
8000236: 0006c663 bltz a3,8000242 <system_clock_108m_hxtal+0x26>
800023a: 6741 lui a4,0x10
800023c: 177d addi a4,a4,-1
800023e: fee796e3 bne a5,a4,800022a <system_clock_108m_hxtal+0xe>
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
8000242: 400217b7 lui a5,0x40021
8000246: 439c lw a5,0(a5)
8000248: 00e79713 slli a4,a5,0xe
800024c: 00074363 bltz a4,8000252 <system_clock_108m_hxtal+0x36>
while(1){
}
8000250: a001 j 8000250 <system_clock_108m_hxtal+0x34>
}
/* HXTAL is stable */
/* AHB = SYSCLK */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
8000252: 400217b7 lui a5,0x40021
8000256: 43d8 lw a4,4(a5)
8000258: c3d8 sw a4,4(a5)
/* APB2 = AHB/1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
800025a: 43d8 lw a4,4(a5)
800025c: c3d8 sw a4,4(a5)
/* APB1 = AHB/2 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
800025e: 43d8 lw a4,4(a5)
8000260: 40076713 ori a4,a4,1024
8000264: c3d8 sw a4,4(a5)
/* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
8000266: 43d8 lw a4,4(a5)
8000268: dfc406b7 lui a3,0xdfc40
800026c: 16fd addi a3,a3,-1
800026e: 8f75 and a4,a4,a3
8000270: c3d8 sw a4,4(a5)
RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27);
8000272: 43d8 lw a4,4(a5)
8000274: 202906b7 lui a3,0x20290
8000278: 8f55 or a4,a4,a3
800027a: c3d8 sw a4,4(a5)
RCU_CTL |= RCU_CTL_PLL2EN;
/* wait till PLL1 is ready */
while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){
}
}else if(HXTAL_VALUE==8000000){
RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
800027c: 57d8 lw a4,44(a5)
800027e: 76bd lui a3,0xfffef
8000280: 8f75 and a4,a4,a3
8000282: d7d8 sw a4,44(a5)
RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 | RCU_PREDV1_DIV2 | RCU_PLL1_MUL20 | RCU_PLL2_MUL20);
8000284: 57d8 lw a4,44(a5)
8000286: 66c1 lui a3,0x10
8000288: f1168693 addi a3,a3,-239 # ff11 <__stack_size+0xf711>
800028c: 8f55 or a4,a4,a3
800028e: d7d8 sw a4,44(a5)
/* enable PLL1 */
RCU_CTL |= RCU_CTL_PLL1EN;
8000290: 4398 lw a4,0(a5)
8000292: 040006b7 lui a3,0x4000
8000296: 8f55 or a4,a4,a3
8000298: c398 sw a4,0(a5)
/* wait till PLL1 is ready */
while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){
800029a: 400217b7 lui a5,0x40021
800029e: 439c lw a5,0(a5)
80002a0: 00479713 slli a4,a5,0x4
80002a4: fe075be3 bgez a4,800029a <system_clock_108m_hxtal+0x7e>
}
/* enable PLL2 */
RCU_CTL |= RCU_CTL_PLL2EN;
80002a8: 40021737 lui a4,0x40021
80002ac: 431c lw a5,0(a4)
80002ae: 100006b7 lui a3,0x10000
80002b2: 8fd5 or a5,a5,a3
80002b4: c31c sw a5,0(a4)
/* wait till PLL1 is ready */
while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){
80002b6: 400217b7 lui a5,0x40021
80002ba: 439c lw a5,0(a5)
80002bc: 00279713 slli a4,a5,0x2
80002c0: fe075be3 bgez a4,80002b6 <system_clock_108m_hxtal+0x9a>
}
}
/* enable PLL */
RCU_CTL |= RCU_CTL_PLLEN;
80002c4: 40021737 lui a4,0x40021
80002c8: 431c lw a5,0(a4)
80002ca: 010006b7 lui a3,0x1000
80002ce: 8fd5 or a5,a5,a3
80002d0: c31c sw a5,0(a4)
/* wait until PLL is stable */
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
80002d2: 400217b7 lui a5,0x40021
80002d6: 439c lw a5,0(a5)
80002d8: 00679713 slli a4,a5,0x6
80002dc: fe075be3 bgez a4,80002d2 <system_clock_108m_hxtal+0xb6>
}
/* select PLL as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
80002e0: 400217b7 lui a5,0x40021
80002e4: 43d8 lw a4,4(a5)
80002e6: 9b71 andi a4,a4,-4
80002e8: c3d8 sw a4,4(a5)
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
80002ea: 43d8 lw a4,4(a5)
80002ec: 00276713 ori a4,a4,2
80002f0: c3d8 sw a4,4(a5)
/* wait until PLL is selected as system clock */
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
80002f2: 400217b7 lui a5,0x40021
80002f6: 43dc lw a5,4(a5)
80002f8: 8ba1 andi a5,a5,8
80002fa: dfe5 beqz a5,80002f2 <system_clock_108m_hxtal+0xd6>
}
}
80002fc: 8082 ret
080002fe <system_clock_config>:
{
80002fe: 1141 addi sp,sp,-16
8000300: c606 sw ra,12(sp)
system_clock_108m_hxtal();
8000302: 3f29 jal 800021c <system_clock_108m_hxtal>
}
8000304: 40b2 lw ra,12(sp)
8000306: 0141 addi sp,sp,16
8000308: 8082 ret
0800030a <SystemInit>:
{
800030a: 1141 addi sp,sp,-16
800030c: c606 sw ra,12(sp)
RCU_CTL |= RCU_CTL_IRC8MEN;
800030e: 400217b7 lui a5,0x40021
8000312: 4398 lw a4,0(a5)
8000314: 00176713 ori a4,a4,1
8000318: c398 sw a4,0(a5)
RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
800031a: 43d8 lw a4,4(a5)
800031c: e0ff06b7 lui a3,0xe0ff0
8000320: 06b1 addi a3,a3,12
8000322: 8f75 and a4,a4,a3
8000324: c3d8 sw a4,4(a5)
RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN);
8000326: 4398 lw a4,0(a5)
8000328: fef706b7 lui a3,0xfef70
800032c: 16fd addi a3,a3,-1
800032e: 8f75 and a4,a4,a3
8000330: c398 sw a4,0(a5)
RCU_CTL &= ~(RCU_CTL_HXTALBPS);
8000332: 4398 lw a4,0(a5)
8000334: fffc06b7 lui a3,0xfffc0
8000338: 16fd addi a3,a3,-1
800033a: 8f75 and a4,a4,a3
800033c: c398 sw a4,0(a5)
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF |
800033e: 43d8 lw a4,4(a5)
8000340: df0106b7 lui a3,0xdf010
8000344: 16fd addi a3,a3,-1
8000346: 8f75 and a4,a4,a3
8000348: c3d8 sw a4,4(a5)
RCU_CFG1 = 0x00000000U;
800034a: 0207a623 sw zero,44(a5) # 4002102c <_sp+0x2001c02c>
RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
800034e: 4398 lw a4,0(a5)
8000350: eaf706b7 lui a3,0xeaf70
8000354: 16fd addi a3,a3,-1
8000356: 8f75 and a4,a4,a3
8000358: c398 sw a4,0(a5)
RCU_INT = 0x00FF0000U;
800035a: 00ff0737 lui a4,0xff0
800035e: c798 sw a4,8(a5)
system_clock_config();
8000360: 3f79 jal 80002fe <system_clock_config>
}
8000362: 40b2 lw ra,12(sp)
8000364: 0141 addi sp,sp,16
8000366: 8082 ret
08000368 <_fini>:
// Function called after main() finishes */
void _fini() {
// Do nothing
8000368: 8082 ret
...
0800036c <irq_entry>:
.weak irq_entry
irq_entry: // -------------> This label will be set to MTVT2 register
// Allocate the stack space
SAVE_CONTEXT// Save 16 regs
800036c: 715d addi sp,sp,-80
800036e: c006 sw ra,0(sp)
8000370: c212 sw tp,4(sp)
8000372: c416 sw t0,8(sp)
8000374: c61a sw t1,12(sp)
8000376: c81e sw t2,16(sp)
8000378: ca2a sw a0,20(sp)
800037a: cc2e sw a1,24(sp)
800037c: ce32 sw a2,28(sp)
800037e: d036 sw a3,32(sp)
8000380: d23a sw a4,36(sp)
8000382: d43e sw a5,40(sp)
8000384: d642 sw a6,44(sp)
8000386: d846 sw a7,48(sp)
8000388: da72 sw t3,52(sp)
800038a: dc76 sw t4,56(sp)
800038c: de7a sw t5,60(sp)
800038e: c0fe sw t6,64(sp)
//------This special CSR read operation, which is actually use mcause as operand to directly store it to memory
csrrwi x0, CSR_PUSHMCAUSE, 17
8000390: 7ee8d073 csrwi 0x7ee,17
//------This special CSR read operation, which is actually use mepc as operand to directly store it to memory
csrrwi x0, CSR_PUSHMEPC, 18
8000394: 7ef95073 csrwi 0x7ef,18
//------This special CSR read operation, which is actually use Msubm as operand to directly store it to memory
csrrwi x0, CSR_PUSHMSUBM, 19
8000398: 7eb9d073 csrwi 0x7eb,19
0800039c <service_loop>:
service_loop:
//------This special CSR read/write operation, which is actually Claim the CLIC to find its pending highest
// ID, if the ID is not 0, then automatically enable the mstatus.MIE, and jump to its vector-entry-label, and
// update the link register
csrrw ra, CSR_JALMNXTI, ra
800039c: 7ed090f3 csrrw ra,0x7ed,ra
//RESTORE_CONTEXT_EXCPT_X5
#---- Critical section with interrupts disabled -----------------------
DISABLE_MIE # Disable interrupts
80003a0: 30047073 csrci mstatus,8
LOAD x5, 19*REGBYTES(sp)
80003a4: 42b6 lw t0,76(sp)
csrw CSR_MSUBM, x5
80003a6: 7c429073 csrw 0x7c4,t0
LOAD x5, 18*REGBYTES(sp)
80003aa: 42a6 lw t0,72(sp)
csrw CSR_MEPC, x5
80003ac: 34129073 csrw mepc,t0
LOAD x5, 17*REGBYTES(sp)
80003b0: 4296 lw t0,68(sp)
csrw CSR_MCAUSE, x5
80003b2: 34229073 csrw mcause,t0
RESTORE_CONTEXT
80003b6: 4082 lw ra,0(sp)
80003b8: 4212 lw tp,4(sp)
80003ba: 42a2 lw t0,8(sp)
80003bc: 4332 lw t1,12(sp)
80003be: 43c2 lw t2,16(sp)
80003c0: 4552 lw a0,20(sp)
80003c2: 45e2 lw a1,24(sp)
80003c4: 4672 lw a2,28(sp)
80003c6: 5682 lw a3,32(sp)
80003c8: 5712 lw a4,36(sp)
80003ca: 57a2 lw a5,40(sp)
80003cc: 5832 lw a6,44(sp)
80003ce: 58c2 lw a7,48(sp)
80003d0: 5e52 lw t3,52(sp)
80003d2: 5ee2 lw t4,56(sp)
80003d4: 5f72 lw t5,60(sp)
80003d6: 4f86 lw t6,64(sp)
80003d8: 6161 addi sp,sp,80
// Return to regular code
mret
80003da: 30200073 mret
080003de <exit>:
#define EXIT_SUCCESS 0
#define EXIT_FAILURE 1
__extern void _exit(int s);
__extern_inline void exit(int err)
{
80003de: 1141 addi sp,sp,-16
80003e0: c606 sw ra,12(sp)
_exit(err);
80003e2: 280d jal 8000414 <_exit>
080003e4 <_start>:
/*
* Rudimentary startup function.
*/
void _start(void)
{
80003e4: 1141 addi sp,sp,-16
80003e6: c606 sw ra,12(sp)
#if !MYNEWT_VAL(OS_SCHEDULING)
int rc;
rc = main(0, NULL);
80003e8: 4581 li a1,0
80003ea: 4501 li a0,0
80003ec: 2019 jal 80003f2 <main>
80003ee: 201d jal 8000414 <_exit>
080003f0 <_init>:
}
void
_init(void)
{
}
80003f0: 8082 ret
080003f2 <main>:
void *_estack; // End of stack, defined in Linker Script.
extern const struct flash_area sysflash_map_dflt[]; // Contains addresses of flash sections. Defined in bin/targets/bluepill_boot/generated/src/bluepill_boot-sysflash.c
int
main(void)
{
80003f2: 1141 addi sp,sp,-16
80003f4: c606 sw ra,12(sp)
// This is a stub bootloader for Blue Pill. We jump straight into the application.
// This simple bootloader allows the application to take up more ROM space.
hal_bsp_init();
80003f6: 2809 jal 8000408 <hal_bsp_init>
// img_start points to the STM32 Vector Table for the app...
// First word contains initial MSP value (estack = end of RAM)
// Second word contains address of entry point (Reset_Handler = 0x0800112d)
void *img_start = (void *) (
sysflash_map_dflt[1].fa_off // Offset of FLASH_AREA_IMAGE_0 (application image): 0x08001000
80003f8: 080017b7 lui a5,0x8001
80003fc: be478793 addi a5,a5,-1052 # 8000be4 <sysflash_map_dflt>
8000400: 4b88 lw a0,16(a5)
+ 0x20 // Size of Mynewt image header
); // Equals 0x08001020 (__isr_vector)
// Jump to Reset_Handler of the application. Uses first word and second word of img_start.
hal_system_start(img_start);
8000402: 02050513 addi a0,a0,32
8000406: 209d jal 800046c <hal_system_start>
08000408 <hal_bsp_init>:
return dump_cfg;
}
void
hal_bsp_init(void)
{
8000408: 1141 addi sp,sp,-16
800040a: c606 sw ra,12(sp)
int rc;
(void)rc;
gd32vf103_periph_create();
800040c: 2091 jal 8000450 <gd32vf103_periph_create>
MYNEWT_VAL(BSP_FLASH_SPI_NAME), &flash_spi_cfg);
assert(rc == 0);
#endif
#endif
}
800040e: 40b2 lw ra,12(sp)
8000410: 0141 addi sp,sp,16
8000412: 8082 ret
08000414 <_exit>:
void _exit(int status);
void
_exit(int status)
{
8000414: 1141 addi sp,sp,-16
8000416: c606 sw ra,12(sp)
hal_system_reset();
8000418: 20a1 jal 8000460 <hal_system_reset>
0800041a <gd32vf103_periph_create_timers>:
#endif
#endif
static void
gd32vf103_periph_create_timers(void)
{
800041a: 1141 addi sp,sp,-16
800041c: c606 sw ra,12(sp)
int rc;
(void)rc;
#if MYNEWT_VAL(TIMER_0)
hal_timer_init(0, NULL);
800041e: 4581 li a1,0
8000420: 4501 li a0,0
8000422: 2881 jal 8000472 <hal_timer_init>
#endif
#if MYNEWT_VAL(TIMER_1)
hal_timer_init(1, NULL);
8000424: 4581 li a1,0
8000426: 4505 li a0,1
8000428: 20a9 jal 8000472 <hal_timer_init>
#endif
#if MYNEWT_VAL(TIMER_2)
hal_timer_init(2, NULL);
800042a: 4581 li a1,0
800042c: 4509 li a0,2
800042e: 2091 jal 8000472 <hal_timer_init>
#endif
#if MYNEWT_VAL(OS_CPUTIME_TIMER_NUM) >= 0
rc = os_cputime_init(MYNEWT_VAL(OS_CPUTIME_FREQ));
8000430: 000f4537 lui a0,0xf4
8000434: 24050513 addi a0,a0,576 # f4240 <__stack_size+0xf3a40>
8000438: 78c000ef jal ra,8000bc4 <os_cputime_init>
assert(rc == 0);
800043c: e501 bnez a0,8000444 <gd32vf103_periph_create_timers+0x2a>
#endif
}
800043e: 40b2 lw ra,12(sp)
8000440: 0141 addi sp,sp,16
8000442: 8082 ret
assert(rc == 0);
8000444: 4681 li a3,0
8000446: 4601 li a2,0
8000448: 4581 li a1,0
800044a: 4501 li a0,0
800044c: 76e000ef jal ra,8000bba <__assert_func>
08000450 <gd32vf103_periph_create>:
#endif
}
void
gd32vf103_periph_create(void)
{
8000450: 1141 addi sp,sp,-16
8000452: c606 sw ra,12(sp)
gd32vf103_periph_create_timers();
8000454: 37d9 jal 800041a <gd32vf103_periph_create_timers>
gd32vf103_periph_create_uart();
gd32vf103_periph_create_spi();
}
8000456: 40b2 lw ra,12(sp)
8000458: 0141 addi sp,sp,16
800045a: 8082 ret
0800045c <hal_debugger_connected>:
int
hal_debugger_connected(void)
{
return 0;
}
800045c: 4501 li a0,0
800045e: 8082 ret
08000460 <hal_system_reset>:
{
8000460: 1141 addi sp,sp,-16
8000462: c606 sw ra,12(sp)
if (hal_debugger_connected()) {
8000464: 3fe5 jal 800045c <hal_debugger_connected>
8000466: dd7d beqz a0,8000464 <hal_system_reset+0x4>
asm ("ebreak");
8000468: 9002 ebreak
800046a: bfed j 8000464 <hal_system_reset+0x4>
0800046c <hal_system_start>:
*
* @param hdr The header for the image to boot.
*/
void
hal_system_start(void *img_start)
{
800046c: 1141 addi sp,sp,-16
800046e: c606 sw ra,12(sp)
__attribute__((noreturn)) void (*fn)(void) = img_start;
/* Jump to image. */
fn();
8000470: 9502 jalr a0
08000472 <hal_timer_init>:
int
hal_timer_init(int timer_num, void *cfg)
{
struct gd32vf103_hal_tmr *tmr;
if (timer_num >= GD32VF103_HAL_TIMER_MAX
8000472: 4789 li a5,2
8000474: 00a7cd63 blt a5,a0,800048e <hal_timer_init+0x1c>
|| !(tmr = gd32vf103_tmr_devs[timer_num])) {
8000478: 00251793 slli a5,a0,0x2
800047c: 08001537 lui a0,0x8001
8000480: bd850513 addi a0,a0,-1064 # 8000bd8 <gd32vf103_tmr_devs>
8000484: 953e add a0,a0,a5
8000486: 411c lw a5,0(a0)
8000488: c789 beqz a5,8000492 <hal_timer_init+0x20>
return -1;
}
return 0;
800048a: 4501 li a0,0
800048c: 8082 ret
return -1;
800048e: 557d li a0,-1
8000490: 8082 ret
8000492: 557d li a0,-1
}
8000494: 8082 ret
08000496 <hal_timer_config>:
*/
int
hal_timer_config(int timer_num, uint32_t freq_hz)
{
struct gd32vf103_hal_tmr *tmr;
if (timer_num >= GD32VF103_HAL_TIMER_MAX || !(tmr = gd32vf103_tmr_devs[timer_num])) {
8000496: 4789 li a5,2
8000498: 0aa7cf63 blt a5,a0,8000556 <hal_timer_config+0xc0>
{
800049c: 7179 addi sp,sp,-48
800049e: d606 sw ra,44(sp)
80004a0: d422 sw s0,40(sp)
80004a2: d226 sw s1,36(sp)
80004a4: d04a sw s2,32(sp)
if (timer_num >= GD32VF103_HAL_TIMER_MAX || !(tmr = gd32vf103_tmr_devs[timer_num])) {
80004a6: 00251793 slli a5,a0,0x2
80004aa: 08001537 lui a0,0x8001
80004ae: bd850513 addi a0,a0,-1064 # 8000bd8 <gd32vf103_tmr_devs>
80004b2: 953e add a0,a0,a5
80004b4: 4100 lw s0,0(a0)
80004b6: c055 beqz s0,800055a <hal_timer_config+0xc4>
80004b8: 892e mv s2,a1
return -1;
}
// Based on Examples/TIMER/TIMER1_timebase/main.c
eclic_global_interrupt_enable();
80004ba: 2055 jal 800055e <eclic_global_interrupt_enable>
eclic_set_nlbits(ECLIC_GROUP_LEVEL3_PRIO1);
80004bc: 450d li a0,3
80004be: 2d05 jal 8000aee <eclic_set_nlbits>
eclic_irq_enable(tmr->irq, 1, 0);
80004c0: 4601 li a2,0
80004c2: 4585 li a1,1
80004c4: 4408 lw a0,8(s0)
80004c6: 2879 jal 8000564 <eclic_irq_enable>
TIMER1 Configuration:
TIMER1CLK = SystemCoreClock/5400 = 20KHz.
TIMER1 configuration is timing mode, and the timing is 0.2s(4000/20000 = 0.2s).
CH0 update rate = TIMER1 counter clock/CH0CV = 20000/4000 = 5Hz.
---------------------------------------------------------------------------- */
uint32_t prescaler = SystemCoreClock / freq_hz;
80004c8: 200007b7 lui a5,0x20000
80004cc: 03c7a483 lw s1,60(a5) # 2000003c <SystemCoreClock>
80004d0: 0324d4b3 divu s1,s1,s2
if (prescaler > 0xffff) {
80004d4: 67c1 lui a5,0x10
80004d6: 06f4fb63 bgeu s1,a5,800054c <hal_timer_config+0xb6>
assert(0);
return -1; // Only 16 bits supported for prescaler
}
timer_parameter_struct timer_initpara;
rcu_periph_clock_enable(tmr->rcu);
80004da: 4048 lw a0,4(s0)
80004dc: 284d jal 800058e <rcu_periph_clock_enable>
timer_deinit(tmr->periph);
80004de: 4008 lw a0,0(s0)
80004e0: 28ed jal 80005da <timer_deinit>
// Initialize TIMER init parameter struct
timer_struct_para_init(&timer_initpara);
80004e2: 0808 addi a0,sp,16
80004e4: 2a6d jal 800069e <timer_struct_para_init>
// TIMER configuration
timer_initpara.prescaler = prescaler; // Previously 5399
80004e6: 00911823 sh s1,16(sp)
timer_initpara.alignedmode = TIMER_COUNTER_EDGE;
80004ea: 00011923 sh zero,18(sp)
timer_initpara.counterdirection = TIMER_COUNTER_UP; // Count starts from 0
80004ee: 00011a23 sh zero,20(sp)
timer_initpara.period = 1; // Count ends at 1, previously 4000
80004f2: 4485 li s1,1
80004f4: cc26 sw s1,24(sp)
timer_initpara.clockdivision = TIMER_CKDIV_DIV1;
80004f6: 00011e23 sh zero,28(sp)
timer_init(tmr->periph, &timer_initpara);
80004fa: 080c addi a1,sp,16
80004fc: 4008 lw a0,0(s0)
80004fe: 2a75 jal 80006ba <timer_init>
timer_oc_parameter_struct timer_ocinitpara;
// Initialize TIMER channel output parameter struct
timer_channel_output_struct_para_init(&timer_ocinitpara);
8000500: 0048 addi a0,sp,4
8000502: 2cad jal 800077c <timer_channel_output_struct_para_init>
// CH0, CH1 and CH2 configuration in OC timing mode
timer_ocinitpara.outputstate = TIMER_CCX_ENABLE;
8000504: 00911223 sh s1,4(sp)
timer_ocinitpara.ocpolarity = TIMER_OC_POLARITY_HIGH;
8000508: 00011423 sh zero,8(sp)
timer_ocinitpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW;
800050c: 00011623 sh zero,12(sp)
timer_channel_output_config( tmr->periph, TIMER_CH_0, &timer_ocinitpara);
8000510: 0050 addi a2,sp,4
8000512: 4581 li a1,0
8000514: 4008 lw a0,0(s0)
8000516: 2441 jal 8000796 <timer_channel_output_config>
// CH0 configuration in OC timing mode
timer_channel_output_pulse_value_config(tmr->periph, TIMER_CH_0, 2000); // TODO: Why 2000
8000518: 7d000613 li a2,2000
800051c: 4581 li a1,0
800051e: 4008 lw a0,0(s0)
8000520: 29c5 jal 8000a10 <timer_channel_output_pulse_value_config>
timer_channel_output_mode_config( tmr->periph, TIMER_CH_0, TIMER_OC_MODE_TIMING);
8000522: 4601 li a2,0
8000524: 4581 li a1,0
8000526: 4008 lw a0,0(s0)
8000528: 2151 jal 80009ac <timer_channel_output_mode_config>
timer_channel_output_shadow_config( TIMER1, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE);
800052a: 4601 li a2,0
800052c: 4581 li a1,0
800052e: 40000537 lui a0,0x40000
8000532: 2329 jal 8000a3c <timer_channel_output_shadow_config>
timer_interrupt_enable( tmr->periph, TIMER_INT_CH0);
8000534: 4589 li a1,2
8000536: 4008 lw a0,0(s0)
8000538: 23a5 jal 8000aa0 <timer_interrupt_enable>
timer_enable( tmr->periph);
800053a: 4008 lw a0,0(s0)
800053c: 2c1d jal 8000772 <timer_enable>
_REG32(tmr->pwm_regs, PWM_CFG) = PWM_CFG_ZEROCMP |
PWM_CFG_ENALWAYS | scale;
plic_enable_interrupt(tmr->pwmxcmp0_int);
#endif // OLD
return 0;
800053e: 4501 li a0,0
}
8000540: 50b2 lw ra,44(sp)
8000542: 5422 lw s0,40(sp)
8000544: 5492 lw s1,36(sp)
8000546: 5902 lw s2,32(sp)
8000548: 6145 addi sp,sp,48
800054a: 8082 ret