The goal of these 3 consecutive projects is to simulate the execution of a five-stage pipelined processor, namely FETCH, DECODE, EXECUTE, MEMORY and WRITE BACK.
| Project No. | Description | Related Code |
|---|---|---|
| 0 | A sequential 5-stage pipelined simulator that can do operand forwarding or bypassing. | sim-pipe.c, sim-pipe.h |
| 1 | A sequential pipeline simulator with four-way set-associative cache simulation modules. | sim-pipe.c, sim-pipe.h, mycache.h |
| 2 | A parallel version of the 5-stage pipelined simulator with cache simulation. | sim-pipe_multiproc.c |
Estimated code amount: ~ 2,000 lines