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rt2800.h
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rt2800.h
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/*
Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
<http://rt2x00.serialmonkey.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the
Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
Module: rt2800
Abstract: Data structures and registers for the rt2800 modules.
Supported chipsets: RT2800E, RT2800ED & RT2800U.
*/
#ifndef RT2800_H
#define RT2800_H
/*
* RF chip defines.
*
* RF2820 2.4G 2T3R
* RF2850 2.4G/5G 2T3R
* RF2720 2.4G 1T2R
* RF2750 2.4G/5G 1T2R
* RF3020 2.4G 1T1R
* RF2020 2.4G B/G
* RF3021 2.4G 1T2R
* RF3022 2.4G 2T2R
* RF3052 2.4G/5G 2T2R
* RF2853 2.4G/5G 3T3R
* RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
* RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
* RF3053 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
* RF5360 2.4G 1T1R
* RF5370 2.4G 1T1R
* RF5390 2.4G 1T1R
*/
#define BIT0 (1 << 0)
#define BIT1 (1 << 1)
#define BIT2 (1 << 2)
#define BIT3 (1 << 3)
#define BIT4 (1 << 4)
#define BIT5 (1 << 5)
#define BIT6 (1 << 6)
#define BIT7 (1 << 7)
#define BIT8 (1 << 8)
#define BIT9 (1 << 9)
#define BIT10 (1 << 10)
#define BIT11 (1 << 11)
#define BIT12 (1 << 12)
#define BIT13 (1 << 13)
#define BIT14 (1 << 14)
#define BIT15 (1 << 15)
#define BIT16 (1 << 16)
#define BIT17 (1 << 17)
#define BIT18 (1 << 18)
#define BIT19 (1 << 19)
#define BIT20 (1 << 20)
#define BIT21 (1 << 21)
#define BIT22 (1 << 22)
#define BIT23 (1 << 23)
#define BIT24 (1 << 24)
#define BIT25 (1 << 25)
#define BIT26 (1 << 26)
#define BIT27 (1 << 27)
#define BIT28 (1 << 28)
#define BIT29 (1 << 29)
#define BIT30 (1 << 30)
#define BIT31 (1 << 31)
#define RF2820 0x0001
#define RF2850 0x0002
#define RF2720 0x0003
#define RF2750 0x0004
#define RF3020 0x0005
#define RF2020 0x0006
#define RF3021 0x0007
#define RF3022 0x0008
#define RF3052 0x0009
#define RF2853 0x000a
#define RF3320 0x000b
#define RF3322 0x000c
#define RF3053 0x000d
#define RF3290 0x3290
#define RF5360 0x5360
#define RF5370 0x5370
#define RF5372 0x5372
#define RF5390 0x5390
#define RF5392 0x5392
#define RF7630 0x7630
/*
* Chipset revisions.
*/
#define REV_RT2860C 0x0100
#define REV_RT2860D 0x0101
#define REV_RT2872E 0x0200
#define REV_RT3070E 0x0200
#define REV_RT3070F 0x0201
#define REV_RT3071E 0x0211
#define REV_RT3090E 0x0211
#define REV_RT3390E 0x0211
#define REV_RT5390F 0x0502
#define REV_RT5390R 0x1502
/*
* Signal information.
* Default offset is required for RSSI <-> dBm conversion.
*/
#define DEFAULT_RSSI_OFFSET 120
/*
* Register layout information.
*/
#define CSR_REG_BASE 0x1000
#define CSR_REG_SIZE 0x0800
#define EEPROM_BASE 0x0000
#define EEPROM_SIZE 0x0110
#define BBP_BASE 0x0000
#define BBP_SIZE 0x00ff
#define RF_BASE 0x0004
#define RF_SIZE 0x0010
#define RFCSR_BASE 0x0000
#define RFCSR_SIZE 0x0040
/*
* Number of TX queues.
*/
#define NUM_TX_QUEUES 4
/*
* Registers.
*/
/*
* MAC_CSR0_3290: MAC_CSR0 for RT3290 to identity MAC version number.
*/
#define MAC_CSR0_3290 0x0000
/*
* E2PROM_CSR: PCI EEPROM control register.
* RELOAD: Write 1 to reload eeprom content.
* TYPE: 0: 93c46, 1:93c66.
* LOAD_STATUS: 1:loading, 0:done.
*/
#define E2PROM_CSR 0x0004
#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
#define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
#define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
#define E2PROM_CSR_TYPE FIELD32(0x00000030)
#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
/*
* CMB_CTRL_CFG
*/
#define CMB_CTRL 0x0020
#define AUX_OPT_BIT0 FIELD32(0x00000001)
#define AUX_OPT_BIT1 FIELD32(0x00000002)
#define AUX_OPT_BIT2 FIELD32(0x00000004)
#define AUX_OPT_BIT3 FIELD32(0x00000008)
#define AUX_OPT_BIT4 FIELD32(0x00000010)
#define AUX_OPT_BIT5 FIELD32(0x00000020)
#define AUX_OPT_BIT6 FIELD32(0x00000040)
#define AUX_OPT_BIT7 FIELD32(0x00000080)
#define AUX_OPT_BIT8 FIELD32(0x00000100)
#define AUX_OPT_BIT9 FIELD32(0x00000200)
#define AUX_OPT_BIT10 FIELD32(0x00000400)
#define AUX_OPT_BIT11 FIELD32(0x00000800)
#define AUX_OPT_BIT12 FIELD32(0x00001000)
#define AUX_OPT_BIT13 FIELD32(0x00002000)
#define AUX_OPT_BIT14 FIELD32(0x00004000)
#define AUX_OPT_BIT15 FIELD32(0x00008000)
#define LDO25_LEVEL FIELD32(0x00030000)
#define LDO25_LARGEA FIELD32(0x00040000)
#define LDO25_FRC_ON FIELD32(0x00080000)
#define CMB_RSV FIELD32(0x00300000)
#define XTAL_RDY FIELD32(0x00400000)
#define PLL_LD FIELD32(0x00800000)
#define LDO_CORE_LEVEL FIELD32(0x0F000000)
#define LDO_BGSEL FIELD32(0x30000000)
#define LDO3_EN FIELD32(0x40000000)
#define LDO0_EN FIELD32(0x80000000)
/*
* EFUSE_CSR_3290: RT3290 EEPROM
*/
#define EFUSE_CTRL_3290 0x0024
/*
* EFUSE_DATA3 of 3290
*/
#define EFUSE_DATA3_3290 0x0028
/*
* EFUSE_DATA2 of 3290
*/
#define EFUSE_DATA2_3290 0x002c
/*
* EFUSE_DATA1 of 3290
*/
#define EFUSE_DATA1_3290 0x0030
/*
* EFUSE_DATA0 of 3290
*/
#define EFUSE_DATA0_3290 0x0034
/*
* OSC_CTRL_CFG
* Ring oscillator configuration
*/
#define OSC_CTRL 0x0038
#define OSC_REF_CYCLE FIELD32(0x00001fff)
#define OSC_RSV FIELD32(0x0000e000)
#define OSC_CAL_CNT FIELD32(0x0fff0000)
#define OSC_CAL_ACK FIELD32(0x10000000)
#define OSC_CLK_32K_VLD FIELD32(0x20000000)
#define OSC_CAL_REQ FIELD32(0x40000000)
#define OSC_ROSC_EN FIELD32(0x80000000)
/*
* COEX_CFG_0
*/
#define COEX_CFG0 0x0040
#define COEX_CFG_ANT FIELD32(0xff000000)
/*
* COEX_CFG_1
*/
#define COEX_CFG1 0x0044
/*
* COEX_CFG_2
*/
#define COEX_CFG2 0x0048
#define BT_COEX_CFG1 FIELD32(0xff000000)
#define BT_COEX_CFG0 FIELD32(0x00ff0000)
#define WL_COEX_CFG1 FIELD32(0x0000ff00)
#define WL_COEX_CFG0 FIELD32(0x000000ff)
/*
* COEX_CFG_3
*/
#define COEXCFG3 0x4C
/*
* PLL_CTRL_CFG
* PLL configuration register
*/
#define PLL_CTRL 0x0050
#define PLL_RESERVED_INPUT1 FIELD32(0x000000ff)
#define PLL_RESERVED_INPUT2 FIELD32(0x0000ff00)
#define PLL_CONTROL FIELD32(0x00070000)
#define PLL_LPF_R1 FIELD32(0x00080000)
#define PLL_LPF_C1_CTRL FIELD32(0x00300000)
#define PLL_LPF_C2_CTRL FIELD32(0x00c00000)
#define PLL_CP_CURRENT_CTRL FIELD32(0x03000000)
#define PLL_PFD_DELAY_CTRL FIELD32(0x0c000000)
#define PLL_LOCK_CTRL FIELD32(0x70000000)
#define PLL_VBGBK_EN FIELD32(0x80000000)
/*
* WLAN_CTRL_CFG
* RT3290 wlan configuration
*/
#define WLAN_FUN_CTRL 0x0080
#define WLAN_EN FIELD32(0x00000001)
#define WLAN_CLK_EN FIELD32(0x00000002)
#define WLAN_RSV1 FIELD32(0x00000004)
#define WLAN_RESET FIELD32(0x00000008)
#define PCIE_APP0_CLK_REQ FIELD32(0x00000010)
#define FRC_WL_ANT_SET FIELD32(0x00000020)
#define INV_TR_SW0 FIELD32(0x00000040)
#define WLAN_GPIO_IN_BIT0 FIELD32(0x00000100)
#define WLAN_GPIO_IN_BIT1 FIELD32(0x00000200)
#define WLAN_GPIO_IN_BIT2 FIELD32(0x00000400)
#define WLAN_GPIO_IN_BIT3 FIELD32(0x00000800)
#define WLAN_GPIO_IN_BIT4 FIELD32(0x00001000)
#define WLAN_GPIO_IN_BIT5 FIELD32(0x00002000)
#define WLAN_GPIO_IN_BIT6 FIELD32(0x00004000)
#define WLAN_GPIO_IN_BIT7 FIELD32(0x00008000)
#define WLAN_GPIO_IN_BIT_ALL FIELD32(0x0000ff00)
#define WLAN_GPIO_OUT_BIT0 FIELD32(0x00010000)
#define WLAN_GPIO_OUT_BIT1 FIELD32(0x00020000)
#define WLAN_GPIO_OUT_BIT2 FIELD32(0x00040000)
#define WLAN_GPIO_OUT_BIT3 FIELD32(0x00050000)
#define WLAN_GPIO_OUT_BIT4 FIELD32(0x00100000)
#define WLAN_GPIO_OUT_BIT5 FIELD32(0x00200000)
#define WLAN_GPIO_OUT_BIT6 FIELD32(0x00400000)
#define WLAN_GPIO_OUT_BIT7 FIELD32(0x00800000)
#define WLAN_GPIO_OUT_BIT_ALL FIELD32(0x00ff0000)
#define WLAN_GPIO_OUT_OE_BIT0 FIELD32(0x01000000)
#define WLAN_GPIO_OUT_OE_BIT1 FIELD32(0x02000000)
#define WLAN_GPIO_OUT_OE_BIT2 FIELD32(0x04000000)
#define WLAN_GPIO_OUT_OE_BIT3 FIELD32(0x08000000)
#define WLAN_GPIO_OUT_OE_BIT4 FIELD32(0x10000000)
#define WLAN_GPIO_OUT_OE_BIT5 FIELD32(0x20000000)
#define WLAN_GPIO_OUT_OE_BIT6 FIELD32(0x40000000)
#define WLAN_GPIO_OUT_OE_BIT7 FIELD32(0x80000000)
#define WLAN_GPIO_OUT_OE_BIT_ALL FIELD32(0xff000000)
/*
* AUX_CTRL: Aux/PCI-E related configuration
*/
#define AUX_CTRL 0x10c
#define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002)
#define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400)
/*
* OPT_14: Unknown register used by rt3xxx devices.
*/
#define OPT_14_CSR 0x0114
#define OPT_14_CSR_BIT0 FIELD32(0x00000001)
/*
* INT_SOURCE_CSR: Interrupt source register.
* Write one to clear corresponding bit.
* TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
*/
#define INT_R0_DONE (0x00000001)
#define INT_R1_DONE (0x00000002)
#define INT_T0_DONE (0x00000010)
#define INT_T1_DONE (0x00000020)
#define INT_T2_DONE (0x00000040)
#define INT_T3_DONE (0x00000080)
#define INT_T4_DONE (0x00000100)
#define INT_T5_DONE (0x00000200)
#define INT_T6_DONE (0x00000400)
#define INT_T7_DONE (0x00000800)
#define INT_T8_DONE (0x00001000)
#define INT_T9_DONE (0x00002000)
#define INT_RESVD (0x00004000 |0x00008000)
#define INT_RX_COHE (0x00010000)
#define INT_TX_COHE (0x00020000)
#define INT_ANY_COH (0x00040000)
#define INT_MCU_CMD (0x00080000)
#define INT_TBTT_ISR (0x00100000)
#define INT_PRE_TBTT (0x00200000)
#define INT_TX_STAT (0x00400000)
#define INT_AUTO_WAKE (0x00800000)
#define INT_GP_TIMER (0x01000000)
#define INT_RESVD_2 (0x02000000)
#define INT_RX_DLY (0x04000000)
#define INT_TX_DLY (0x08000000)
#define DELAYINTMASK 0x0DFF3FF3
#define INTMASK 0x0DFF3FF3
#define RxINT (INT_R0_DONE | INT_R1_DONE /* | INT_RX_DLY */)
#define TxDataInt (INT_T0_DONE | INT_T1_DONE | INT_T2_DONE | INT_T3_DONE /*| INT_TX_DLY*/)
#define TxMgmtInt (INT_T9_DONE /*| INT_TX_DLY*/)
#define INT_SOURCE_CSR 0x0200
#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
#define INT_SOURCE_CSR_7630_RXDELAYINT FIELD32(INT_RX_DLY)
#define INT_SOURCE_CSR_7630_TXDELAYINT FIELD32(INT_TX_DLY)
#define INT_SOURCE_CSR_7630_RX_DONE FIELD32((INT_R0_DONE || INT_R1_DONE ))
#define INT_SOURCE_CSR_7630_AC0_DMA_DONE FIELD32(INT_T0_DONE)
#define INT_SOURCE_CSR_7630_AC1_DMA_DONE FIELD32(INT_T1_DONE)
#define INT_SOURCE_CSR_7630_AC2_DMA_DONE FIELD32(INT_T2_DONE)
#define INT_SOURCE_CSR_7630_AC3_DMA_DONE FIELD32(INT_T3_DONE)
#define INT_SOURCE_CSR_7630_HCCA_DMA_DONE FIELD32(INT_T4_DONE)
#define INT_SOURCE_CSR_7630_MGMT_DMA_DONE FIELD32(INT_T5_DONE)
#define INT_SOURCE_CSR_7630_MCU_COMMAND FIELD32(INT_MCU_CMD)
#define INT_SOURCE_CSR_7630_RXTX_COHERENT FIELD32(INT_ANY_COH)
#define INT_SOURCE_CSR_7630_TBTT FIELD32(INT_TBTT_ISR)
#define INT_SOURCE_CSR_7630_PRE_TBTT FIELD32(INT_PRE_TBTT)
#define INT_SOURCE_CSR_7630_TX_FIFO_STATUS FIELD32(INT_TX_STAT)
#define INT_SOURCE_CSR_7630_AUTO_WAKEUP FIELD32(INT_AUTO_WAKE)
#define INT_SOURCE_CSR_7630_GPTIMER FIELD32(INT_GP_TIMER)
#define INT_SOURCE_CSR_7630_RX_COHERENT FIELD32(INT_RX_COHE)
#define INT_SOURCE_CSR_7630_TX_COHERENT FIELD32(INT_TX_COHE)
/*
* INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
*/
#if 0
#define INT_MASK_CSR 0x0204
#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
#endif
#define INT_MASK_CSR 0x0204
#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
#define INT_MASK_CSR_7630_RXDELAYINT FIELD32(INT_RX_DLY)
#define INT_MASK_CSR_7630_TXDELAYINT FIELD32(INT_TX_DLY)
#define INT_MASK_CSR_7630_RX_DONE FIELD32(INT_R0_DONE || INT_R1_DONE)
#define INT_MASK_CSR_7630_AC0_DMA_DONE FIELD32(INT_T0_DONE)
#define INT_MASK_CSR_7630_AC1_DMA_DONE FIELD32(INT_T1_DONE)
#define INT_MASK_CSR_7630_AC2_DMA_DONE FIELD32(INT_T2_DONE)
#define INT_MASK_CSR_7630_AC3_DMA_DONE FIELD32(INT_T3_DONE)
#define INT_MASK_CSR_7630_HCCA_DMA_DONE FIELD32(INT_T4_DONE)
#define INT_MASK_CSR_7630_MGMT_DMA_DONE FIELD32(INT_T5_DONE)
#define INT_MASK_CSR_7630_MCU_COMMAND FIELD32(INT_MCU_CMD)
#define INT_MASK_CSR_7630_RXTX_COHERENT FIELD32(INT_ANY_COH)
#define INT_MASK_CSR_7630_TBTT FIELD32(INT_TBTT_ISR)
#define INT_MASK_CSR_7630_PRE_TBTT FIELD32(INT_PRE_TBTT)
#define INT_MASK_CSR_7630_TX_FIFO_STATUS FIELD32(INT_TX_STAT)
#define INT_MASK_CSR_7630_AUTO_WAKEUP FIELD32(INT_AUTO_WAKE)
#define INT_MASK_CSR_7630_GPTIMER FIELD32(INT_GP_TIMER)
#define INT_MASK_CSR_7630_RX_COHERENT FIELD32(INT_RX_COHE)
#define INT_MASK_CSR_7630_TX_COHERENT FIELD32(INT_TX_COHE)
/*
* WPDMA_GLO_CFG
*/
#define WPDMA_GLO_CFG 0x0208
#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
/*
* WPDMA_RST_IDX
*/
#define WPDMA_RST_IDX 0x020c
#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
/*
* DELAY_INT_CFG
*/
#define DELAY_INT_CFG 0x0210
#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
/*
* WMM_AIFSN_CFG: Aifsn for each EDCA AC
* AIFSN0: AC_VO
* AIFSN1: AC_VI
* AIFSN2: AC_BE
* AIFSN3: AC_BK
*/
#define WMM_AIFSN_CFG 0x0214
#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
/*
* WMM_CWMIN_CSR: CWmin for each EDCA AC
* CWMIN0: AC_VO
* CWMIN1: AC_VI
* CWMIN2: AC_BE
* CWMIN3: AC_BK
*/
#define WMM_CWMIN_CFG 0x0218
#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
/*
* WMM_CWMAX_CSR: CWmax for each EDCA AC
* CWMAX0: AC_VO
* CWMAX1: AC_VI
* CWMAX2: AC_BE
* CWMAX3: AC_BK
*/
#define WMM_CWMAX_CFG 0x021c
#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
/*
* AC_TXOP0: AC_VO/AC_VI TXOP register
* AC0TXOP: AC_VO in unit of 32us
* AC1TXOP: AC_VI in unit of 32us
*/
#define WMM_TXOP0_CFG 0x0220
#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
/*
* AC_TXOP1: AC_BE/AC_BK TXOP register
* AC2TXOP: AC_BE in unit of 32us
* AC3TXOP: AC_BK in unit of 32us
*/
#define WMM_TXOP1_CFG 0x0224
#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
/*
* GPIO_CTRL_CFG:
* GPIOD: GPIO direction, 0: Output, 1: Input
*/
#define GPIO_CTRL_CFG 0x0228
#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
#define GPIO_CTRL_CFG_GPIOD_BIT0 FIELD32(0x00000100)
#define GPIO_CTRL_CFG_GPIOD_BIT1 FIELD32(0x00000200)
#define GPIO_CTRL_CFG_GPIOD_BIT2 FIELD32(0x00000400)
#define GPIO_CTRL_CFG_GPIOD_BIT3 FIELD32(0x00000800)
#define GPIO_CTRL_CFG_GPIOD_BIT4 FIELD32(0x00001000)
#define GPIO_CTRL_CFG_GPIOD_BIT5 FIELD32(0x00002000)
#define GPIO_CTRL_CFG_GPIOD_BIT6 FIELD32(0x00004000)
#define GPIO_CTRL_CFG_GPIOD_BIT7 FIELD32(0x00008000)
/*
* MCU_CMD_CFG
*/
#define MCU_CMD_CFG 0x022c
/*
* AC_VO register offsets
*/
#define TX_BASE_PTR0 0x0230
#define TX_MAX_CNT0 0x0234
#define TX_CTX_IDX0 0x0238
#define TX_DTX_IDX0 0x023c
/*
* AC_VI register offsets
*/
#define TX_BASE_PTR1 0x0240
#define TX_MAX_CNT1 0x0244
#define TX_CTX_IDX1 0x0248
#define TX_DTX_IDX1 0x024c
/*
* AC_BE register offsets
*/
#define TX_BASE_PTR2 0x0250
#define TX_MAX_CNT2 0x0254
#define TX_CTX_IDX2 0x0258
#define TX_DTX_IDX2 0x025c
/*
* AC_BK register offsets
*/
#define TX_BASE_PTR3 0x0260
#define TX_MAX_CNT3 0x0264
#define TX_CTX_IDX3 0x0268
#define TX_DTX_IDX3 0x026c
/*
* HCCA register offsets
*/
#define TX_BASE_PTR4 0x0270
#define TX_MAX_CNT4 0x0274
#define TX_CTX_IDX4 0x0278
#define TX_DTX_IDX4 0x027c
/*
* MGMT register offsets
*/
#define TX_BASE_PTR5 0x0280
#define TX_MAX_CNT5 0x0284
#define TX_CTX_IDX5 0x0288
#define TX_DTX_IDX5 0x028c
/*
* RX register offsets
*/
#define RX_BASE_PTR 0x0290
#define RX_MAX_CNT 0x0294
#define RX_CRX_IDX 0x0298
#define RX_DRX_IDX 0x029c
//woody
#define RINGREG_DIFF 0x10
#define TX_RING_BASE 0x0300
#define TX_RING_NUM 10
#define TX_RING_PTR 0x0300
#define TX_RING_CNT 0x0304
#define TX_RING_CIDX 0x0308
#define TX_RING_DIDX 0x030c
#define TX_MGMT_BASE (TX_RING_BASE + RINGREG_DIFF * 9)
#define TX_MGMT_CNT (TX_MGMT_BASE + 0x04)
#define TX_MGMT_CIDX (TX_MGMT_BASE + 0x08)
#define TX_MGMT_DIDX (TX_MGMT_BASE + 0x0c)
#define TX_CTRL_BASE (TX_RING_BASE + RINGREG_DIFF * 8)
#define TX_CTRL_CNT (TX_CTRL_BASE + 0x04)
#define TX_CTRL_CIDX (TX_CTRL_BASE + 0x08)
#define TX_CTRL_DIDX (TX_CTRL_BASE + 0x0c)
#define RX_RING_BASE 0x03c0
#define RX_RING_PTR RX_RING_BASE
#define RX_RING_CNT (RX_RING_BASE + 0x04)
#define RX_RING_CIDX (RX_RING_BASE + 0x08)
#define RX_RING_DIDX (RX_RING_BASE + 0x0c)
#define RX_RING1_BASE 0x03d0
#define RX_RING1_PTR RX_RING1_BASE
#define RX_RING1_CNT (RX_RING1_BASE + 0x04)
#define RX_RING1_CIDX (RX_RING1_BASE + 0x08)
#define RX_RING1_DIDX (RX_RING1_BASE + 0x0c)
#define TX_CHAN_BASE_1 (TX_RING_BASE + RINGREG_DIFF * 0)
#define TX_CHAN_BASE_2 (TX_RING_BASE + RINGREG_DIFF * 6)
/*
* USB_DMA_CFG
* RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
* RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
* PHY_CLEAR: phy watch dog enable.
* TX_CLEAR: Clear USB DMA TX path.
* TXOP_HALT: Halt TXOP count down when TX buffer is full.
* RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
* RX_BULK_EN: Enable USB DMA Rx.
* TX_BULK_EN: Enable USB DMA Tx.
* EP_OUT_VALID: OUT endpoint data valid.
* RX_BUSY: USB DMA RX FSM busy.
* TX_BUSY: USB DMA TX FSM busy.
*/
#define USB_DMA_CFG 0x02a0
#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
#define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
#define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
#define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
#define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
#define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
#define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
#define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
#define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
#define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
#define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
/*
* US_CYC_CNT
* BT_MODE_EN: Bluetooth mode enable
* CLOCK CYCLE: Clock cycle count in 1us.
* PCI:0x21, PCIE:0x7d, USB:0x1e
*/
#define US_CYC_CNT 0x02a4
#define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100)
#define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
/*
* PBF_SYS_CTRL
* HOST_RAM_WRITE: enable Host program ram write selection
*/
#define PBF_SYS_CTRL 0x0400
#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
/*
* HOST-MCU shared memory
*/
#define HOST_CMD_CSR 0x0404
#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
/*
* PBF registers
* Most are for debug. Driver doesn't touch PBF register.
*/
#define PBF_CFG 0x0408
#define PBF_MAX_PCNT 0x040c
#define PBF_CTRL 0x0410
#define PBF_INT_STA 0x0414
#define PBF_INT_ENA 0x0418
#define PBF_CFG_7630 0x0404
#define PBF_MAX_PCNT_7630 0x0408
#define TX_MAX_PCNT 0x0408
#define RX_MAX_PCNT 0x040c
#define RXQ_STA 0x0430
#define TXQ_STA 0x0434
#define BCN_OFFSET0_7630 0x041c
#define BCN_OFFSET1_7630 0x0420
#define BCN_OFFSET2_7630 0x0424
#define BCN_OFFSET3_7630 0x0428
#define FCE_PSE_CTRL 0x0800
#define FCE_PARAMETERS 0x0804
#define FCE_CSO 0x0808
#define FCE_L2_STUFF 0x080c
#define TX_CPU_PORT_FROM_FCE_BASE_PTR 0x09A0
#define TX_CPU_PORT_FROM_FCE_MAX_COUNT 0x09A4
#define FCE_PDMA_GLOBAL_CONF 0x09C4
#define TX_CPU_PORT_FROM_FCE_CPU_DESC_INDEX 0x09A8
#define FCE_SKIP_FS 0x0A6C
#define PER_PORT_PAUSE_ENABLE_CONTROL1 0x0A38
#define AMPDU_MAX_LEN_20M1S 0x1030
#define AMPDU_MAX_LEN_20M2S 0x1034
#define AMPDU_MAX_LEN_40M1S 0x1038
#define AMPDU_MAX_LEN_40M2S 0x103c
#define AMPDU_MAX_LEN 0x1040
#define HEADER_TRANS_CTRL_REG 0x0260
#define TSO_CTRL 0x0250
#define AUX_CLK_CFG 0x120C
#define BB_PA_MODE_CFG0 0x1214
#define BB_PA_MODE_CFG1 0x1218
#define RF_PA_MODE_CFG0 0x121C
#define RF_PA_MODE_CFG1 0x1220
#define TX_ALC_CFG_0 0x13B0
#define TX_ALC_CFG_1 0x13B4
#define TX0_RF_GAIN_CORR 0x13A0
#define TX0_RF_GAIN_ATTEN 0x13A8
#define TX0_BB_GAIN_ATTEN 0x13C0
#define TX_ALC_VGA3 0x13C8
#define TX_PWR_CFG_5 0x1384
#define TX_PWR_CFG_6 0x1388
#define TX_PWR_CFG_7 0x13D4
#define TX_PWR_CFG_8 0x13D8
#define TX_PWR_CFG_9 0x13DC
#define EXT_CCA_CFG 0x141c
#define WMM_CTRL 0x0230
#define RF_G_BAND 0x0100
#define RF_A_BAND 0x0200
#define RF_A_BAND_LB 0x0400
#define RF_A_BAND_MB 0x0800
#define RF_A_BAND_HB 0x1000
#define RF_A_BAND_11J 0x2000
#define RF_BW_20 1
#define RF_BW_40 2
#define RF_BW_10 4
#define RF_BW_80 8
#define RF_MISC 0x0518
/* b'00: 2.4G+5G external PA, b'01: 5G external PA, b'10: 2.4G external PA, b'11: Internal PA */
#define EXT_PA_2G_5G 0x0
#define EXT_PA_5G_ONLY 0x1
#define EXT_PA_2G_ONLY 0x2
#define INT_PA_2G_5G 0x3
/*
RF bank
*/
#define RF_BANK0 0
#define RF_BANK1 1
#define RF_BANK2 2
#define RF_BANK3 3
#define RF_BANK4 4
#define RF_BANK5 5
#define RF_BANK6 6
#define RF_BANK7 7
#define RF_BANK8 8
#define RF_BANK9 9
#define RF_BANK10 10
#define RF_BANK11 11
#define RF_BANK12 12
#define RF_BANK13 13
#define RF_BANK14 14
#define RF_BANK15 15
/*
RF sections
*/
#define RF_R00 0
#define RF_R01 1
#define RF_R02 2
#define RF_R03 3
#define RF_R04 4
#define RF_R05 5
#define RF_R06 6
#define RF_R07 7
#define RF_R08 8
#define RF_R09 9
#define RF_R10 10
#define RF_R11 11
#define RF_R12 12
#define RF_R13 13
#define RF_R14 14
#define RF_R15 15
#define RF_R16 16
#define RF_R17 17
#define RF_R18 18
#define RF_R19 19
#define RF_R20 20
#define RF_R21 21
#define RF_R22 22
#define RF_R23 23
#define RF_R24 24
#define RF_R25 25
#define RF_R26 26
#define RF_R27 27
#define RF_R28 28
#define RF_R29 29
#define RF_R30 30
#define RF_R31 31
#define RF_R32 32
#define RF_R33 33
#define RF_R34 34
#define RF_R35 35
#define RF_R36 36
#define RF_R37 37
#define RF_R38 38
#define RF_R39 39
#define RF_R40 40
#define RF_R41 41
#define RF_R42 42
#define RF_R43 43
#define RF_R44 44
#define RF_R45 45
#define RF_R46 46
#define RF_R47 47
#define RF_R48 48
#define RF_R49 49
#define RF_R50 50
#define RF_R51 51
#define RF_R52 52
#define RF_R53 53
#define RF_R54 54
#define RF_R55 55
#define RF_R56 56
#define RF_R57 57
#define RF_R58 58
#define RF_R59 59
#define RF_R60 60
#define RF_R61 61
#define RF_R62 62
#define RF_R63 63
#define RF_R64 64
#define RF_R65 65
#define RF_R66 66
#define RF_R67 67
#define RF_R68 68
#define RF_R69 69
#define RF_R70 70
#define RF_R71 71
#define RF_R72 72
#define RF_R73 73
#define RF_R74 74
#define RF_R75 75
#define RF_R76 76
#define RF_R77 77
#define RF_R78 78
#define RF_R79 79
#define RF_R126 126
#define RF_R127 127
/* BW */
#define BW_20 0
#define BW_40 1
#define BW_80 2
#define BW_10 4 /* 802.11j has 10MHz. This definition is for internal usage. doesn't fill in the IE or other field. */
/*
* BCN_OFFSET0:
*/
#define BCN_OFFSET0 0x042c
#define BCN_OFFSET0_7630 0x041c
#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
/*
* BCN_OFFSET1:
*/
#define BCN_OFFSET1 0x0430
#define BCN_OFFSET1_7630 0x0420
#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
/*
* TXRXQ_PCNT: PBF register
* PCNT_TX0Q: Page count for TX hardware queue 0
* PCNT_TX1Q: Page count for TX hardware queue 1
* PCNT_TX2Q: Page count for TX hardware queue 2
* PCNT_RX0Q: Page count for RX hardware queue
*/
#define TXRXQ_PCNT 0x0438
#define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff)
#define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00)
#define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000)
#define TXRXQ_PCNT_RX0Q FIELD32(0xff000000)
/*
* PBF register
* Debug. Driver doesn't touch PBF register.
*/
#define PBF_DBG 0x043c
/*
* RF registers
*/
#define RF_CSR_CFG 0x0500
#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
#define RF_CSR_CFG_REGNUM FIELD32(0x00003f00)
#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
#define RF_CSR_CFG_BUSY_MT7630 FIELD32(0x80000000)
#define RF_CSR_CFG_WRITE_MT7630 FIELD32(0x40000000)
#define RF_CSR_CFG_BANK_MT7630 FIELD32(0x00038000)