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rtw8852a.c
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rtw8852a.c
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/* Copyright(c) 2019-2020 Realtek Corporation
*/
#include "coex.h"
#include "fw.h"
#include "mac.h"
#include "phy.h"
#include "reg.h"
#include "rtw8852a.h"
#include "rtw8852a_rfk.h"
#include "rtw8852a_table.h"
#include "txrx.h"
#define RTW8852A_FW_FORMAT_MAX 0
#define RTW8852A_FW_BASENAME "rtw89/rtw8852a_fw"
#define RTW8852A_MODULE_FIRMWARE \
RTW8852A_FW_BASENAME ".bin"
static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = {
{128, 1896, grp_0}, /* ACH 0 */
{128, 1896, grp_0}, /* ACH 1 */
{128, 1896, grp_0}, /* ACH 2 */
{128, 1896, grp_0}, /* ACH 3 */
{128, 1896, grp_1}, /* ACH 4 */
{128, 1896, grp_1}, /* ACH 5 */
{128, 1896, grp_1}, /* ACH 6 */
{128, 1896, grp_1}, /* ACH 7 */
{32, 1896, grp_0}, /* B0MGQ */
{128, 1896, grp_0}, /* B0HIQ */
{32, 1896, grp_1}, /* B1MGQ */
{128, 1896, grp_1}, /* B1HIQ */
{40, 0, 0} /* FWCMDQ */
};
static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = {
1896, /* Group 0 */
1896, /* Group 1 */
3792, /* Public Max */
0 /* WP threshold */
};
static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = {
[RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie,
&rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
[RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
RTW89_HCIFC_POH},
[RTW89_QTA_INVALID] = {NULL},
};
static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = {
[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0,
&rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
&rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
&rtw89_mac_size.ple_qt5},
[RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size0,
&rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
&rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
&rtw89_mac_size.ple_qt_52a_wow},
[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4,
&rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4,
&rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
&rtw89_mac_size.ple_qt13},
[RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
NULL},
};
static const struct rtw89_reg2_def rtw8852a_pmac_ht20_mcs7_tbl[] = {
{0x44AC, 0x00000000},
{0x44B0, 0x00000000},
{0x44B4, 0x00000000},
{0x44B8, 0x00000000},
{0x44BC, 0x00000000},
{0x44C0, 0x00000000},
{0x44C4, 0x00000000},
{0x44C8, 0x00000000},
{0x44CC, 0x00000000},
{0x44D0, 0x00000000},
{0x44D4, 0x00000000},
{0x44D8, 0x00000000},
{0x44DC, 0x00000000},
{0x44E0, 0x00000000},
{0x44E4, 0x00000000},
{0x44E8, 0x00000000},
{0x44EC, 0x00000000},
{0x44F0, 0x00000000},
{0x44F4, 0x00000000},
{0x44F8, 0x00000000},
{0x44FC, 0x00000000},
{0x4500, 0x00000000},
{0x4504, 0x00000000},
{0x4508, 0x00000000},
{0x450C, 0x00000000},
{0x4510, 0x00000000},
{0x4514, 0x00000000},
{0x4518, 0x00000000},
{0x451C, 0x00000000},
{0x4520, 0x00000000},
{0x4524, 0x00000000},
{0x4528, 0x00000000},
{0x452C, 0x00000000},
{0x4530, 0x4E1F3E81},
{0x4534, 0x00000000},
{0x4538, 0x0000005A},
{0x453C, 0x00000000},
{0x4540, 0x00000000},
{0x4544, 0x00000000},
{0x4548, 0x00000000},
{0x454C, 0x00000000},
{0x4550, 0x00000000},
{0x4554, 0x00000000},
{0x4558, 0x00000000},
{0x455C, 0x00000000},
{0x4560, 0x4060001A},
{0x4564, 0x40000000},
{0x4568, 0x00000000},
{0x456C, 0x00000000},
{0x4570, 0x04000007},
{0x4574, 0x0000DC87},
{0x4578, 0x00000BAB},
{0x457C, 0x03E00000},
{0x4580, 0x00000048},
{0x4584, 0x00000000},
{0x4588, 0x000003E8},
{0x458C, 0x30000000},
{0x4590, 0x00000000},
{0x4594, 0x10000000},
{0x4598, 0x00000001},
{0x459C, 0x00030000},
{0x45A0, 0x01000000},
{0x45A4, 0x03000200},
{0x45A8, 0xC00001C0},
{0x45AC, 0x78018000},
{0x45B0, 0x80000000},
{0x45B4, 0x01C80600},
{0x45B8, 0x00000002},
{0x4594, 0x10000000}
};
static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = {
{0x4624, GENMASK(20, 14), 0x40},
{0x46f8, GENMASK(20, 14), 0x40},
{0x4674, GENMASK(20, 19), 0x2},
{0x4748, GENMASK(20, 19), 0x2},
{0x4650, GENMASK(14, 10), 0x18},
{0x4724, GENMASK(14, 10), 0x18},
{0x4688, GENMASK(1, 0), 0x3},
{0x475c, GENMASK(1, 0), 0x3},
};
static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs);
static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = {
{0x4624, GENMASK(20, 14), 0x1a},
{0x46f8, GENMASK(20, 14), 0x1a},
{0x4674, GENMASK(20, 19), 0x1},
{0x4748, GENMASK(20, 19), 0x1},
{0x4650, GENMASK(14, 10), 0x12},
{0x4724, GENMASK(14, 10), 0x12},
{0x4688, GENMASK(1, 0), 0x0},
{0x475c, GENMASK(1, 0), 0x0},
};
static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs);
static const struct rtw89_pwr_cfg rtw8852a_pwron[] = {
{0x00C6,
PWR_CV_MSK_B,
PWR_INTF_MSK_PCIE,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(6), BIT(6)},
{0x1086,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_SDIO,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), 0},
{0x1086,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_SDIO,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(1), BIT(1)},
{0x0005,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(4) | BIT(3), 0},
{0x0005,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(7), 0},
{0x0005,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(2), 0},
{0x0006,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(1), BIT(1)},
{0x0006,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x0005,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x0005,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(0), 0},
{0x106D,
PWR_CV_MSK_B | PWR_CV_MSK_C,
PWR_INTF_MSK_USB,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(6), 0},
{0x0088,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x0088,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), 0},
{0x0088,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x0088,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), 0},
{0x0088,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x0083,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(6), 0},
{0x0080,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(5), BIT(5)},
{0x0024,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0},
{0x02A0,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(1), BIT(1)},
{0x02A2,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0},
{0x0071,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_PCIE,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(4), 0},
{0x0010,
PWR_CV_MSK_A,
PWR_INTF_MSK_PCIE,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(2), BIT(2)},
{0x02A0,
PWR_CV_MSK_A,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
{0xFFFF,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
0,
PWR_CMD_END, 0, 0},
};
static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = {
{0x02F0,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0},
{0x02F1,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, 0xFF, 0},
{0x0006,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x0002,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(1) | BIT(0), 0},
{0x0082,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(1) | BIT(0), 0},
{0x106D,
PWR_CV_MSK_B | PWR_CV_MSK_C,
PWR_INTF_MSK_USB,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(6), BIT(6)},
{0x0005,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(1), BIT(1)},
{0x0005,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(1), 0},
{0x0091,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_PCIE,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), 0},
{0x0005,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_PCIE,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(2), BIT(2)},
{0x0007,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_USB,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(4), 0},
{0x0007,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_SDIO,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(6) | BIT(4), 0},
{0x0005,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_SDIO,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)},
{0x0005,
PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F |
PWR_CV_MSK_G,
PWR_INTF_MSK_USB,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)},
{0x1086,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_SDIO,
PWR_BASE_MAC,
PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x1086,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_SDIO,
PWR_BASE_MAC,
PWR_CMD_POLL, BIT(1), 0},
{0xFFFF,
PWR_CV_MSK_ALL,
PWR_INTF_MSK_ALL,
0,
PWR_CMD_END, 0, 0},
};
static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = {
rtw8852a_pwron, NULL
};
static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = {
rtw8852a_pwroff, NULL
};
static const u32 rtw8852a_h2c_regs[RTW89_H2CREG_MAX] = {
R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2,
R_AX_H2CREG_DATA3
};
static const u32 rtw8852a_c2h_regs[RTW89_C2HREG_MAX] = {
R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2,
R_AX_C2HREG_DATA3
};
static const struct rtw89_page_regs rtw8852a_page_regs = {
.hci_fc_ctrl = R_AX_HCI_FC_CTRL,
.ch_page_ctrl = R_AX_CH_PAGE_CTRL,
.ach_page_ctrl = R_AX_ACH0_PAGE_CTRL,
.ach_page_info = R_AX_ACH0_PAGE_INFO,
.pub_page_info3 = R_AX_PUB_PAGE_INFO3,
.pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1,
.pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2,
.pub_page_info1 = R_AX_PUB_PAGE_INFO1,
.pub_page_info2 = R_AX_PUB_PAGE_INFO2,
.wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1,
.wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2,
.wp_page_info1 = R_AX_WP_PAGE_INFO1,
};
static const struct rtw89_reg_def rtw8852a_dcfo_comp = {
R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK
};
static const struct rtw89_imr_info rtw8852a_imr_info = {
.wdrls_imr_set = B_AX_WDRLS_IMR_SET,
.wsec_imr_reg = R_AX_SEC_DEBUG,
.wsec_imr_set = B_AX_IMR_ERROR,
.mpdu_tx_imr_set = 0,
.mpdu_rx_imr_set = 0,
.sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
.txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR,
.txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR,
.txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET,
.txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
.txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR,
.txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET,
.wde_imr_clr = B_AX_WDE_IMR_CLR,
.wde_imr_set = B_AX_WDE_IMR_SET,
.ple_imr_clr = B_AX_PLE_IMR_CLR,
.ple_imr_set = B_AX_PLE_IMR_SET,
.host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR,
.host_disp_imr_set = B_AX_HOST_DISP_IMR_SET,
.cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR,
.cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET,
.other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR,
.other_disp_imr_set = 0,
.bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR,
.bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
.bbrpt_err_imr_set = 0,
.bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR,
.ptcl_imr_clr = B_AX_PTCL_IMR_CLR,
.ptcl_imr_set = B_AX_PTCL_IMR_SET,
.cdma_imr_0_reg = R_AX_DLE_CTRL,
.cdma_imr_0_clr = B_AX_DLE_IMR_CLR,
.cdma_imr_0_set = B_AX_DLE_IMR_SET,
.cdma_imr_1_reg = 0,
.cdma_imr_1_clr = 0,
.cdma_imr_1_set = 0,
.phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR,
.phy_intf_imr_clr = 0,
.phy_intf_imr_set = 0,
.rmac_imr_reg = R_AX_RMAC_ERR_ISR,
.rmac_imr_clr = B_AX_RMAC_IMR_CLR,
.rmac_imr_set = B_AX_RMAC_IMR_SET,
.tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR,
.tmac_imr_clr = B_AX_TMAC_IMR_CLR,
.tmac_imr_set = B_AX_TMAC_IMR_SET,
};
static const struct rtw89_xtal_info rtw8852a_xtal_info = {
.xcap_reg = R_AX_XTAL_ON_CTRL0,
.sc_xo_mask = B_AX_XTAL_SC_XO_MASK,
.sc_xi_mask = B_AX_XTAL_SC_XI_MASK,
};
static const struct rtw89_rrsr_cfgs rtw8852a_rrsr_cfgs = {
.ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
.rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
};
static const struct rtw89_dig_regs rtw8852a_dig_regs = {
.seg0_pd_reg = R_SEG0R_PD,
.pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
.pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK,
.bmode_pd_reg = R_BMODE_PDTH_EN_V1,
.bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
.bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1,
.bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
.p0_lna_init = {R_PATH0_LNA_INIT, B_PATH0_LNA_INIT_IDX_MSK},
.p1_lna_init = {R_PATH1_LNA_INIT, B_PATH1_LNA_INIT_IDX_MSK},
.p0_tia_init = {R_PATH0_TIA_INIT, B_PATH0_TIA_INIT_IDX_MSK},
.p1_tia_init = {R_PATH1_TIA_INIT, B_PATH1_TIA_INIT_IDX_MSK},
.p0_rxb_init = {R_PATH0_RXB_INIT, B_PATH0_RXB_INIT_IDX_MSK},
.p1_rxb_init = {R_PATH1_RXB_INIT, B_PATH1_RXB_INIT_IDX_MSK},
.p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC,
B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
.p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC,
B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
.p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC,
B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
.p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC,
B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
};
static const struct rtw89_edcca_regs rtw8852a_edcca_regs = {
.edcca_level = R_SEG0R_EDCCA_LVL,
.edcca_mask = B_EDCCA_LVL_MSK0,
.edcca_p_mask = B_EDCCA_LVL_MSK1,
.ppdu_level = R_SEG0R_EDCCA_LVL,
.ppdu_mask = B_EDCCA_LVL_MSK3,
.rpt_a = R_EDCCA_RPT_A,
.rpt_b = R_EDCCA_RPT_B,
.rpt_sel = R_EDCCA_RPT_SEL,
.rpt_sel_mask = B_EDCCA_RPT_SEL_MSK,
.tx_collision_t2r_st = R_TX_COLLISION_T2R_ST,
.tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
};
static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse,
struct rtw8852a_efuse *map)
{
ether_addr_copy(efuse->addr, map->e.mac_addr);
efuse->rfe_type = map->rfe_type;
efuse->xtal_cap = map->xtal_k;
}
static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
struct rtw8852a_efuse *map)
{
struct rtw89_tssi_info *tssi = &rtwdev->tssi;
struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
u8 i, j;
tssi->thermal[RF_PATH_A] = map->path_a_therm;
tssi->thermal[RF_PATH_B] = map->path_b_therm;
for (i = 0; i < RF_PATH_NUM_8852A; i++) {
memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
sizeof(ofst[i]->cck_tssi));
for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
rtw89_debug(rtwdev, RTW89_DBG_TSSI,
"[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
i, j, tssi->tssi_cck[i][j]);
memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
sizeof(ofst[i]->bw40_tssi));
memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
rtw89_debug(rtwdev, RTW89_DBG_TSSI,
"[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
i, j, tssi->tssi_mcs[i][j]);
}
}
static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
enum rtw89_efuse_block block)
{
struct rtw89_efuse *efuse = &rtwdev->efuse;
struct rtw8852a_efuse *map;
map = (struct rtw8852a_efuse *)log_map;
efuse->country_code[0] = map->country_code[0];
efuse->country_code[1] = map->country_code[1];
rtw8852a_efuse_parsing_tssi(rtwdev, map);
switch (rtwdev->hci.type) {
case RTW89_HCI_TYPE_PCIE:
rtw8852ae_efuse_parsing(efuse, map);
break;
default:
return -ENOTSUPP;
}
rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
return 0;
}
static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
{
struct rtw89_tssi_info *tssi = &rtwdev->tssi;
static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB};
u32 addr = rtwdev->chip->phycap_addr;
bool pg = false;
u32 ofst;
u8 i, j;
for (i = 0; i < RF_PATH_NUM_8852A; i++) {
for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
/* addrs are in decreasing order */
ofst = tssi_trim_addr[i] - addr - j;
tssi->tssi_trim[i][j] = phycap_map[ofst];
if (phycap_map[ofst] != 0xff)
pg = true;
}
}
if (!pg) {
memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
rtw89_debug(rtwdev, RTW89_DBG_TSSI,
"[TSSI][TRIM] no PG, set all trim info to 0\n");
}
for (i = 0; i < RF_PATH_NUM_8852A; i++)
for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
rtw89_debug(rtwdev, RTW89_DBG_TSSI,
"[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
i, j, tssi->tssi_trim[i][j],
tssi_trim_addr[i] - j);
}
static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
u8 *phycap_map)
{
struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC};
u32 addr = rtwdev->chip->phycap_addr;
u8 i;
for (i = 0; i < RF_PATH_NUM_8852A; i++) {
info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
i, info->thermal_trim[i]);
if (info->thermal_trim[i] != 0xff)
info->pg_thermal_trim = true;
}
}
static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev)
{
#define __thm_setting(raw) \
({ \
u8 __v = (raw); \
((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
})
struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
u8 i, val;
if (!info->pg_thermal_trim) {
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[THERMAL][TRIM] no PG, do nothing\n");
return;
}
for (i = 0; i < RF_PATH_NUM_8852A; i++) {
val = __thm_setting(info->thermal_trim[i]);
rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
i, val);
}
#undef __thm_setting
}
static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
u8 *phycap_map)
{
struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB};
u32 addr = rtwdev->chip->phycap_addr;
u8 i;
for (i = 0; i < RF_PATH_NUM_8852A; i++) {
info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
i, info->pa_bias_trim[i]);
if (info->pa_bias_trim[i] != 0xff)
info->pg_pa_bias_trim = true;
}
}
static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev)
{
struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
u8 pabias_2g, pabias_5g;
u8 i;
if (!info->pg_pa_bias_trim) {
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[PA_BIAS][TRIM] no PG, do nothing\n");
return;
}
for (i = 0; i < RF_PATH_NUM_8852A; i++) {
pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
rtw89_debug(rtwdev, RTW89_DBG_RFK,
"[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
i, pabias_2g, pabias_5g);
rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
}
}
static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
{
rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map);
rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map);
rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
return 0;
}
static void rtw8852a_power_trim(struct rtw89_dev *rtwdev)
{
rtw8852a_thermal_trim(rtwdev);
rtw8852a_pa_bias_trim(rtwdev);
}
static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
u8 mac_idx)
{
u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx);
u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx);
u8 txsc20 = 0, txsc40 = 0;
switch (chan->band_width) {
case RTW89_CHANNEL_WIDTH_80:
txsc40 = rtw89_phy_get_txsc(rtwdev, chan,
RTW89_CHANNEL_WIDTH_40);
fallthrough;
case RTW89_CHANNEL_WIDTH_40:
txsc20 = rtw89_phy_get_txsc(rtwdev, chan,
RTW89_CHANNEL_WIDTH_20);
break;
default:
break;
}
switch (chan->band_width) {
case RTW89_CHANNEL_WIDTH_80:
rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
break;
case RTW89_CHANNEL_WIDTH_40:
rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
rtw89_write32(rtwdev, sub_carr, txsc20);
break;
case RTW89_CHANNEL_WIDTH_20:
rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
rtw89_write32(rtwdev, sub_carr, 0);
break;
default:
break;
}
if (chan->channel > 14)
rtw89_write8_set(rtwdev, chk_rate,
B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
else
rtw89_write8_clr(rtwdev, chk_rate,
B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
}
static const u32 rtw8852a_sco_barker_threshold[14] = {
0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4
};
static const u32 rtw8852a_sco_cck_threshold[14] = {
0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724,
0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed
};
static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch,
u8 primary_ch, enum rtw89_bandwidth bw)
{
u8 ch_element;
if (bw == RTW89_CHANNEL_WIDTH_20) {
ch_element = central_ch - 1;
} else if (bw == RTW89_CHANNEL_WIDTH_40) {
if (primary_ch == 1)
ch_element = central_ch - 1 + 2;
else
ch_element = central_ch - 1 - 2;
} else {
rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw);
return -EINVAL;
}
rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
rtw8852a_sco_barker_threshold[ch_element]);
rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
rtw8852a_sco_cck_threshold[ch_element]);
return 0;
}
static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch,
u8 path)
{
u32 val;
val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
if (val == INV_RF_DATA) {
rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path);
return;
}
val &= ~0x303ff;
val |= central_ch;
if (central_ch > 14)
val |= (BIT(16) | BIT(8));
rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val);
}
static u8 rtw8852a_sco_mapping(u8 central_ch)
{
if (central_ch == 1)
return 109;
else if (central_ch >= 2 && central_ch <= 6)
return 108;
else if (central_ch >= 7 && central_ch <= 10)
return 107;
else if (central_ch >= 11 && central_ch <= 14)
return 106;
else if (central_ch == 36 || central_ch == 38)
return 51;
else if (central_ch >= 40 && central_ch <= 58)
return 50;
else if (central_ch >= 60 && central_ch <= 64)
return 49;
else if (central_ch == 100 || central_ch == 102)
return 48;
else if (central_ch >= 104 && central_ch <= 126)
return 47;
else if (central_ch >= 128 && central_ch <= 151)
return 46;
else if (central_ch >= 153 && central_ch <= 177)
return 45;
else
return 0;
}
static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch,
enum rtw89_phy_idx phy_idx)
{
u8 sco_comp;
bool is_2g = central_ch <= 14;
if (phy_idx == RTW89_PHY_0) {
/* Path A */
rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A);
if (is_2g)
rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1,
B_PATH0_TIA_ERR_G1_SEL, 1,
phy_idx);
else
rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1,
B_PATH0_TIA_ERR_G1_SEL, 0,
phy_idx);
/* Path B */
if (!rtwdev->dbcc_en) {
rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B);
if (is_2g)
rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
B_P1_MODE_SEL,
1, phy_idx);
else
rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
B_P1_MODE_SEL,
0, phy_idx);
} else {
if (is_2g)
rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND,
B_2P4G_BAND_SEL);
else
rtw89_phy_write32_set(rtwdev, R_2P4G_BAND,
B_2P4G_BAND_SEL);
}
/* SCO compensate FC setting */
sco_comp = rtw8852a_sco_mapping(central_ch);
rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV,
sco_comp, phy_idx);
} else {
/* Path B */
rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B);
if (is_2g)
rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
B_P1_MODE_SEL,
1, phy_idx);
else
rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
B_P1_MODE_SEL,
0, phy_idx);
/* SCO compensate FC setting */
sco_comp = rtw8852a_sco_mapping(central_ch);
rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV,
sco_comp, phy_idx);
}
/* Band edge */
if (is_2g)
rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1,
phy_idx);
else
rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0,
phy_idx);
/* CCK parameters */
if (central_ch == 14) {
rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
0x3b13ff);
rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23,
0x1c42de);
rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45,
0xfdb0ad);
rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67,
0xf60f6e);
rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89,
0xfd8f92);
rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF,
0xfff00a);
} else {
rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
0x3d23ff);
rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23,
0x29b354);
rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67,
0xfdb053);
rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89,
0xf86f9a);
rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB,
0xfaef92);
rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD,
0xfe5fcc);
rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF,
0xffdff5);
}
}
static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
{
u32 val = 0;
u32 adc_sel[2] = {0x12d0, 0x32d0};
u32 wbadc_sel[2] = {0x12ec, 0x32ec};
val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
if (val == INV_RF_DATA) {
rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path);
return;
}
val &= ~(BIT(11) | BIT(10));
switch (bw) {
case RTW89_CHANNEL_WIDTH_5:
rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
val |= (BIT(11) | BIT(10));
break;
case RTW89_CHANNEL_WIDTH_10:
rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
val |= (BIT(11) | BIT(10));
break;
case RTW89_CHANNEL_WIDTH_20:
rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
val |= (BIT(11) | BIT(10));
break;
case RTW89_CHANNEL_WIDTH_40:
rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
val |= BIT(11);
break;
case RTW89_CHANNEL_WIDTH_80:
rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
val |= BIT(10);
break;
default:
rtw89_warn(rtwdev, "Fail to set ADC\n");
}
rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val);
}
static void
rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
enum rtw89_phy_idx phy_idx)
{
/* Switch bandwidth */
switch (bw) {
case RTW89_CHANNEL_WIDTH_5: