pipistrello sometimes fails timing

[jordens]

Timing failures are intermittent. Potentially triggered by congestion and large filling factor. Failure is usually in the sys_clk domain, in the CPU (IIRC).

It looks like par starts with a particular unlucky guess and then can't find its way out. Overriding the libc rng seed with LD_PRELOAD does not help. Same code, same options can lead to success and failure. Sometimes ten builds in a row succeed followed by five builds failing.

Do we require this being fixed for the release?

[sbourdeauducq]

Turns out there are still some places in the Python part of the gateware that are still affected by this annoying Python iteration randomization, and the generated Verilog changes from one run to the next, which may in turn affect PAR. Does setting PYTHONHASHSEED help, as a workaround?

[jordens]

With -R it seems to fail timing consistently now.

[mithro]

We have found similar problems when using ISE - See timvideos/HDMI2USB-litex-firmware#209 and timvideos/HDMI2USB-litex-firmware#72