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Use meaningful class names
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Sebastien Bourdeauducq committed Jan 20, 2012
1 parent d3d5b48 commit 076c171
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Showing 7 changed files with 9 additions and 9 deletions.
4 changes: 2 additions & 2 deletions examples/corelogic_conv.py
@@ -1,8 +1,8 @@
from migen.fhdl import verilog from migen.fhdl import verilog
from migen.corelogic import divider from migen.corelogic import divider


d1 = divider.Inst(16) d1 = divider.Divider(16)
d2 = divider.Inst(16) d2 = divider.Divider(16)
frag = d1.get_fragment() + d2.get_fragment() frag = d1.get_fragment() + d2.get_fragment()
o = verilog.convert(frag, { o = verilog.convert(frag, {
d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i, d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i,
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2 changes: 1 addition & 1 deletion migen/bus/wishbone.py
Expand Up @@ -29,7 +29,7 @@ class Arbiter:
def __init__(self, masters, target): def __init__(self, masters, target):
self.masters = masters self.masters = masters
self.target = target self.target = target
self.rr = roundrobin.Inst(len(self.masters)) self.rr = roundrobin.RoundRobin(len(self.masters))


def get_fragment(self): def get_fragment(self):
comb = [] comb = []
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4 changes: 2 additions & 2 deletions migen/bus/wishbone2csr.py
Expand Up @@ -3,11 +3,11 @@
from migen.fhdl.structure import * from migen.fhdl.structure import *
from migen.corelogic import timeline from migen.corelogic import timeline


class Inst(): class WB2CSR():
def __init__(self): def __init__(self):
self.wishbone = wishbone.Slave("to_csr") self.wishbone = wishbone.Slave("to_csr")
self.csr = csr.Master("from_wishbone") self.csr = csr.Master("from_wishbone")
self.timeline = timeline.Inst(self.wishbone.cyc_i & self.wishbone.stb_i, self.timeline = timeline.Timeline(self.wishbone.cyc_i & self.wishbone.stb_i,
[(1, [self.csr.we_o.eq(self.wishbone.we_i)]), [(1, [self.csr.we_o.eq(self.wishbone.we_i)]),
(2, [self.wishbone.ack_o.eq(1)]), (2, [self.wishbone.ack_o.eq(1)]),
(3, [self.wishbone.ack_o.eq(0)])]) (3, [self.wishbone.ack_o.eq(0)])])
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2 changes: 1 addition & 1 deletion migen/corelogic/divider.py
@@ -1,6 +1,6 @@
from migen.fhdl.structure import * from migen.fhdl.structure import *


class Inst: class Divider:
def __init__(self, w): def __init__(self, w):
self.w = w self.w = w


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2 changes: 1 addition & 1 deletion migen/corelogic/roundrobin.py
@@ -1,6 +1,6 @@
from migen.fhdl.structure import * from migen.fhdl.structure import *


class Inst: class RoundRobin:
def __init__(self, n): def __init__(self, n):
self.n = n self.n = n
self.bn = bits_for(self.n-1) self.bn = bits_for(self.n-1)
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2 changes: 1 addition & 1 deletion migen/corelogic/timeline.py
@@ -1,6 +1,6 @@
from migen.fhdl.structure import * from migen.fhdl.structure import *


class Inst: class Timeline:
def __init__(self, trigger, events): def __init__(self, trigger, events):
self.trigger = trigger self.trigger = trigger
self.events = events self.events = events
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2 changes: 1 addition & 1 deletion migen/flow/ala.py
Expand Up @@ -60,7 +60,7 @@ def __init__(self, bv):


class DivMod(Actor): class DivMod(Actor):
def __init__(self, width): def __init__(self, width):
self.div = divider.Inst(width) self.div = divider.Divider(width)
Actor.__init__(self, Actor.__init__(self,
SchedulingModel(SchedulingModel.SEQUENTIAL, width), SchedulingModel(SchedulingModel.SEQUENTIAL, width),
("operands", Sink, [("dividend", self.div.dividend_i), ("divisor", self.div.divisor_i)]), ("operands", Sink, [("dividend", self.div.dividend_i), ("divisor", self.div.divisor_i)]),
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