iverilog vpi on windows: (i + nchunks == l) assertion fails

[enjoy-digital]

Simulating on a Windows machine (Windows XP) seems to randomly trigger the following assertion:
https://github.com/m-labs/migen/blob/master/vpi/ipc.c#L195

This can be reproduced with LiteSATA tests:
https://github.com/m-labs/misoc/tree/master/misoclib/mem/litesata/test

• make scrambler_tb triggers the issue from time to time.
• make link_tb seems to always trigger the issue.

(Note: to run these tests, the following verilog.py file should probably be used to avoid the verilog hanging issue: https://github.com/enjoy-digital/migen/blob/master/migen/fhdl/verilog.py)

[enjoy-digital]

fixed by 98cf103

on large simulations where we received more that one packet in a message, end of the message (and thus next packet(s) or part of) was ignored.

Tested on WinXP, Win8.1 with LiteSATA simulation.