TMU prefetch: generate datamem busy signal

m-labs · Jul 25, 2011 · 79679fb · 79679fb
1 parent df38f91
commit 79679fb
Showing 1 changed file with 3 additions and 0 deletions.
diff --git a/cores/tmu2/rtl/tmu2_datamem.v b/cores/tmu2/rtl/tmu2_datamem.v
@@ -173,6 +173,7 @@ always @(*) begin
 			req_ce = 1'b1;
 			missmask_init = 1'b1;
 			if(req_valid) begin
+				busy = 1'b1;
 				pipe_stb_o = 1'b1;
 				if(frag_miss_a_r | frag_miss_b_r | frag_miss_c_r | frag_miss_d_r) begin
 					frag_pipe_ack_o = 1'b0;
@@ -187,6 +188,7 @@ always @(*) begin
 			end
 		end
 		COMMIT: begin
+			busy = 1'b1;
 			retry = 1'b1;
 			if((frag_miss_a_r & missmask[0]) | (frag_miss_b_r & missmask[1]) | (frag_miss_c_r & missmask[2]) | (frag_miss_d_r & missmask[3])) begin
 				fetch_pipe_ack_o = 1'b1;
@@ -206,6 +208,7 @@ always @(*) begin
 				next_state = STROBE;
 		end
 		STROBE: begin
+			busy = 1'b1;
 			retry = 1'b1;
 			pipe_stb_o = 1'b1;
 			if(pipe_ack_i) begin