🤹♀️ Awesome - A curated list of amazing VLSI design automation papers, software and resources.
[TOC]
Papers of significance are marked in bold. My comments are marked in italic. Papers of other fields may also included, and we use the following tags to categorize different fields.
CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model(Jinwei Liu, CUHK) [code]
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement(Best Paper Award, Yibo Lin, PKU) [code]
UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine (1st-Place Award of ISPD 2017 Contest, Wuxi Li, UTA)
UTPlaceF 3.0: A Parallelization Framework for Modern FPGA Global Placement(Wuxi Li, UTA)
- Rather than empirically making partitions on physics level, the paper leverages matrix-blocking technique on mathematics level
UTPlaceF: A Routability-Driven FPGA Placer with Physical and Congestion Aware Packing(Wuxi Li, UTA)
- A routability-driven FPGA packing and placement engine
- Routing congestion level is indicated by cell area that may be inflated during FIP flow
To conduct a experiment, datasets, toolchains, hardware configuration, evaluation statistics, prior work and its results should be taken into consideration. This collection is hosted on Google Sheet for the convenience of editing. Also, some toolkits may help improve the quality of life! 🚀
- Limbo: Library for VLSI CAD Design Useful parsers and solvers' API.
- rsyn-x: This framework integrates parsers for common academic and industrial formats as Bookshelf, LEF/DEF, Verilog, Liberty, SDC and SPEF. It provides support for benchmarks from several EDA contests (e.g ISPD, ICCAD).
- Innovus®: Design rule checking and evaluation.
- EE 382V: VLSI Physical Design Automation (Prof. David Z. Pan, UT ECE) [slides]
- An series of VLSI physical design courses(NPTEL, India) [youtube]
- EE382V: Optimization Issues in VLSI CAD (Prof. David Z. Pan, UT ECE)