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platform.ucf
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platform.ucf
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#
# Copyright (C) 2009-2012 Chris McClelland
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU Lesser General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
NET "reset_in" LOC = "T15"; # BRST
# PortB
NET "fifoData_io<0>" LOC = "A2"; # PB0
NET "fifoData_io<1>" LOC = "D6"; # PB1
NET "fifoData_io<2>" LOC = "C6"; # PB2
NET "fifoData_io<3>" LOC = "B3"; # PB3
NET "fifoData_io<4>" LOC = "A3"; # PB4
NET "fifoData_io<5>" LOC = "B4"; # PB5
NET "fifoData_io<6>" LOC = "A4"; # PB6
NET "fifoData_io<7>" LOC = "C5"; # PB7
NET "ifclk_in" LOC = "C10";
NET "gotData_in" LOC = "C15"; # FLAGC
NET "gotRoom_in" LOC = "A9"; # FLAGB
# PortA
NET "sloe_out" LOC = "A15"; # PA2
NET "fifoAddr_out<0>" LOC = "A14"; # PA4
NET "fifoAddr_out<1>" LOC = "B14"; # PA5
NET "pktEnd_out" LOC = "C4"; # PA6
NET "slrd_out" LOC = "F13";
NET "slwr_out" LOC = "E13";
# On-board peripheral signals
NET "led_out<0>" LOC = "U18";
NET "led_out<1>" LOC = "M14";
NET "led_out<2>" LOC = "N14";
NET "led_out<3>" LOC = "L14";
NET "led_out<4>" LOC = "M13";
NET "led_out<5>" LOC = "D4";
NET "led_out<6>" LOC = "P16";
NET "led_out<7>" LOC = "N12";
NET "sseg_out<6>" LOC = "U16"; # segment g
NET "sseg_out<5>" LOC = "U15"; # segment f
NET "sseg_out<4>" LOC = "U13"; # segment e
NET "sseg_out<3>" LOC = "M11"; # segment d
NET "sseg_out<2>" LOC = "R11"; # segment c
NET "sseg_out<1>" LOC = "T12"; # segment b
NET "sseg_out<0>" LOC = "N10"; # segment a
NET "sseg_out<7>" LOC = "M10"; # decimal point
NET "anode_out<0>" LOC = "U11";
NET "anode_out<1>" LOC = "R10";
NET "anode_out<2>" LOC = "U10";
NET "anode_out<3>" LOC = "R8";
NET "sw_in<0>" LOC = "A10"; # SW0
NET "sw_in<1>" LOC = "D14"; # SW1
NET "sw_in<2>" LOC = "C14"; # SW2
NET "sw_in<3>" LOC = "P15"; # SW3
NET "sw_in<4>" LOC = "P12"; # SW4
NET "sw_in<5>" LOC = "R5"; # SW5
NET "sw_in<6>" LOC = "T5"; # SW6
NET "sw_in<7>" LOC = "E4"; # SW7
#========================================================
# Timing constraint of S3 50-MHz onboard oscillator
# name of the clock signal is clk
#========================================================
NET "ifclk_in" TNM_NET = "ifclk_in";
TIMESPEC "TS_clk" = PERIOD "ifclk_in" 20 ns HIGH 50 %;