/
mxc_epdc_fb.c
5322 lines (4547 loc) · 148 KB
/
mxc_epdc_fb.c
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/*
* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
/*
* Based on STMP378X LCDIF
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/uaccess.h>
#include <linux/cpufreq.h>
#include <linux/firmware.h>
#include <linux/kthread.h>
#include <linux/dmaengine.h>
#include <linux/pxp_dma.h>
#include <linux/mxcfb.h>
#include <linux/mxcfb_epdc_kernel.h>
#include <linux/gpio.h>
#ifdef USE_PMIC
#include <linux/regulator/driver.h>
#endif
#include <linux/fsl_devices.h>
// Frank.Lin 2011.05.09
#include <mach/hardware.h>
#include <mach/gpio.h>
#include <mach/iomux-mx50.h>
#include <linux/time.h>
#include <linux/bitops.h>
#include <linux/sort.h>
#include <linux/crc16.h>
#include "epdc_regs.h"
#include "lk_tps65185.h"
#define GDEBUG 0
#include <linux/gallen_dbg.h>
/*
* Enable this define to have a default panel
* loaded during driver initialization
*/
/*#define DEFAULT_PANEL_HW_INIT*/
#define NUM_SCREENS_MIN 2
#define EPDC_NUM_LUTS 16
//#define EPDC_MAX_NUM_UPDATES 20
#define EPDC_MAX_NUM_UPDATES giEPDC_MAX_NUM_UPDATES
#define INVALID_LUT -1
#define DEFAULT_TEMP_INDEX 0
#define DEFAULT_TEMP 20 /* room temp in deg Celsius */
#define INIT_UPDATE_MARKER 0x12345678
#define PAN_UPDATE_MARKER 0x12345679
#define POWER_STATE_OFF 0
#define POWER_STATE_ON 1
#define MERGE_OK 0
#define MERGE_FAIL 1
#define MERGE_BLOCK 2
// Frank.Lin 2011.05.09
#define GPIO_PWRALL (0*32 + 27) /* GPIO_1_27 */
#define EPDC_VCOM (3*32 + 21) /*GPIO_4_21 */
static unsigned long default_bpp = 16;
static int giEPDC_MAX_NUM_UPDATES=2;
static int *_line_ranges; // temporary buffer for calculating which line ranges needs to be updated
static u16 *_blocksCRC16; // CRC16 checksum of every 16x8 pixel block
struct update_marker_data {
struct list_head full_list;
struct list_head upd_list;
u32 update_marker;
struct completion update_completion;
int lut_num;
bool waiting;
};
struct update_desc_list {
struct list_head list;
struct mxcfb_update_data upd_data;/* Update parameters */
u32 epdc_offs; /* Added to buffer ptr to resolve alignment */
struct list_head upd_marker_list; /* List of markers for this update */
u32 update_order; /* Numeric ordering value for update */
};
/* This structure represents a list node containing both
* a memory region allocated as an output buffer for the PxP
* update processing task, and the update description (mode, region, etc.) */
struct update_data_list {
struct list_head list;
dma_addr_t phys_addr; /* Pointer to phys address of processed Y buf */
void *virt_addr;
u32 size;
dma_addr_t phys_addr_copybuf; /* Phys address of copied update data */
void *virt_addr_copybuf; /* Used for PxP SW workaround */
struct update_desc_list *update_desc;
int lut_num; /* Assigned before update is processed into working buffer */
int collision_mask; /* Set when update results in collision */
/* Represents other LUTs that we collide with */
};
struct mxc_epdc_fb_data {
struct fb_info info;
struct fb_var_screeninfo epdc_fb_var; /* Internal copy of screeninfo
so we can sync changes to it */
u32 pseudo_palette[16];
char fw_str[24];
struct list_head list;
struct mxc_epdc_fb_mode *cur_mode;
struct mxc_epdc_fb_platform_data *pdata;
int blank;
ssize_t map_size;
dma_addr_t phys_start;
u32 fb_offset;
int default_bpp;
int native_width;
int native_height;
int num_screens;
int epdc_irq;
struct device *dev;
int power_state;
int wait_for_powerdown;
struct completion powerdown_compl;
struct clk *epdc_clk_axi;
struct clk *epdc_clk_pix;
#ifdef USE_PMIC
struct regulator *display_regulator;
struct regulator *vcom_regulator;
#endif
bool fw_default_load;
/* FB elements related to EPDC updates */
bool in_init;
bool hw_ready;
bool waiting_for_idle;
u32 auto_mode;
u32 upd_scheme;
struct list_head upd_pending_list;
struct list_head upd_buf_queue;
struct list_head upd_buf_free_list;
struct list_head upd_buf_collision_list;
struct update_data_list *cur_update;
spinlock_t queue_lock;
int trt_entries;
int temp_index;
u8 *temp_range_bounds;
struct mxcfb_waveform_modes wv_modes;
u32 *waveform_buffer_virt;
u32 waveform_buffer_phys;
u32 waveform_buffer_size;
u32 *working_buffer_virt;
u32 working_buffer_phys;
u32 working_buffer_size;
u32 order_cnt;
struct list_head full_marker_list;
u32 lut_update_order[EPDC_NUM_LUTS];
u32 luts_complete_wb;
struct completion updates_done;
struct delayed_work epdc_done_work;
struct workqueue_struct *epdc_submit_workqueue;
struct work_struct epdc_submit_work;
//#ifdef FW_IN_RAM //[
struct work_struct epdc_firmware_work;
//#endif//]FW_IN_RAM
bool waiting_for_wb;
bool waiting_for_lut;
bool waiting_for_lut15;
struct completion update_res_free;
struct completion lut15_free;
struct completion eof_event;
int eof_sync_period;
struct mutex power_mutex;
bool powering_down;
bool updates_active;
int pwrdown_delay;
unsigned long tce_prevent;
int merge_on_waveform_mismatch;
/* FB elements related to PxP DMA */
struct completion pxp_tx_cmpl;
struct pxp_channel *pxp_chan;
struct pxp_config_data pxp_conf;
struct dma_async_tx_descriptor *txd;
dma_cookie_t cookie;
struct scatterlist sg[2];
struct mutex pxp_mutex; /* protects access to PxP */
};
struct waveform_data_header {
unsigned int wi0;
unsigned int wi1;
unsigned int wi2;
unsigned int wi3;
unsigned int wi4;
unsigned int wi5;
unsigned int wi6;
unsigned int xwia:24;
unsigned int cs1:8;
unsigned int wmta:24;
unsigned int fvsn:8;
unsigned int luts:8;
unsigned int mc:8;
unsigned int trc:8;
unsigned int reserved0_0:8;
unsigned int eb:8;
unsigned int sb:8;
unsigned int reserved0_1:8;
unsigned int reserved0_2:8;
unsigned int reserved0_3:8;
unsigned int reserved0_4:8;
unsigned int reserved0_5:8;
unsigned int cs2:8;
};
struct mxcfb_waveform_data_file {
struct waveform_data_header wdh;
u32 *data; /* Temperature Range Table + Waveform Data */
};
#include "ntx_hwconfig.h"
extern volatile NTX_HWCONFIG *gptHWCFG;
extern volatile int giRootDevNum;
extern volatile int giRootPartNum;
void __iomem *epdc_base;
struct mxc_epdc_fb_data *g_fb_data;
/* forward declaration */
static int mxc_epdc_fb_get_temp_index(struct mxc_epdc_fb_data *fb_data,
int temp);
static void mxc_epdc_fb_flush_updates(struct mxc_epdc_fb_data *fb_data);
static int mxc_epdc_fb_blank(int blank, struct fb_info *info);
static int mxc_epdc_fb_init_hw(struct fb_info *info);
static int pxp_process_update(struct mxc_epdc_fb_data *fb_data,
u32 src_width, u32 src_height,
struct mxcfb_rect *update_region);
static int pxp_complete_update(struct mxc_epdc_fb_data *fb_data, u32 *hist_stat);
static void draw_mode0(struct mxc_epdc_fb_data *fb_data);
static bool is_free_list_full(struct mxc_epdc_fb_data *fb_data);
static void mxc_epdc_fb_fw_handler(const struct firmware *fw,void *context);
//#ifdef DEBUG
#if 1
static void dump_pxp_config(struct mxc_epdc_fb_data *fb_data,
struct pxp_config_data *pxp_conf)
{
dev_info(fb_data->dev, "S0 fmt 0x%x",
pxp_conf->s0_param.pixel_fmt);
dev_info(fb_data->dev, "S0 width 0x%x",
pxp_conf->s0_param.width);
dev_info(fb_data->dev, "S0 height 0x%x",
pxp_conf->s0_param.height);
dev_info(fb_data->dev, "S0 ckey 0x%x",
pxp_conf->s0_param.color_key);
dev_info(fb_data->dev, "S0 ckey en 0x%x",
pxp_conf->s0_param.color_key_enable);
dev_info(fb_data->dev, "OL0 combine en 0x%x",
pxp_conf->ol_param[0].combine_enable);
dev_info(fb_data->dev, "OL0 fmt 0x%x",
pxp_conf->ol_param[0].pixel_fmt);
dev_info(fb_data->dev, "OL0 width 0x%x",
pxp_conf->ol_param[0].width);
dev_info(fb_data->dev, "OL0 height 0x%x",
pxp_conf->ol_param[0].height);
dev_info(fb_data->dev, "OL0 ckey 0x%x",
pxp_conf->ol_param[0].color_key);
dev_info(fb_data->dev, "OL0 ckey en 0x%x",
pxp_conf->ol_param[0].color_key_enable);
dev_info(fb_data->dev, "OL0 alpha 0x%x",
pxp_conf->ol_param[0].global_alpha);
dev_info(fb_data->dev, "OL0 alpha en 0x%x",
pxp_conf->ol_param[0].global_alpha_enable);
dev_info(fb_data->dev, "OL0 local alpha en 0x%x",
pxp_conf->ol_param[0].local_alpha_enable);
dev_info(fb_data->dev, "Out fmt 0x%x",
pxp_conf->out_param.pixel_fmt);
dev_info(fb_data->dev, "Out width 0x%x",
pxp_conf->out_param.width);
dev_info(fb_data->dev, "Out height 0x%x",
pxp_conf->out_param.height);
dev_info(fb_data->dev,
"drect left 0x%x right 0x%x width 0x%x height 0x%x",
pxp_conf->proc_data.drect.left, pxp_conf->proc_data.drect.top,
pxp_conf->proc_data.drect.width,
pxp_conf->proc_data.drect.height);
dev_info(fb_data->dev,
"srect left 0x%x right 0x%x width 0x%x height 0x%x",
pxp_conf->proc_data.srect.left, pxp_conf->proc_data.srect.top,
pxp_conf->proc_data.srect.width,
pxp_conf->proc_data.srect.height);
dev_info(fb_data->dev, "Scaling en 0x%x", pxp_conf->proc_data.scaling);
dev_info(fb_data->dev, "HFlip en 0x%x", pxp_conf->proc_data.hflip);
dev_info(fb_data->dev, "VFlip en 0x%x", pxp_conf->proc_data.vflip);
dev_info(fb_data->dev, "Rotation 0x%x", pxp_conf->proc_data.rotate);
dev_info(fb_data->dev, "BG Color 0x%x", pxp_conf->proc_data.bgcolor);
}
static void dump_epdc_reg(void)
{
#define KERN_DEBUG
printk(KERN_DEBUG "\n\n");
printk(KERN_DEBUG "EPDC_CTRL 0x%x\n", __raw_readl(EPDC_CTRL));
printk(KERN_DEBUG "EPDC_WVADDR 0x%x\n", __raw_readl(EPDC_WVADDR));
printk(KERN_DEBUG "EPDC_WB_ADDR 0x%x\n", __raw_readl(EPDC_WB_ADDR));
printk(KERN_DEBUG "EPDC_RES 0x%x\n", __raw_readl(EPDC_RES));
printk(KERN_DEBUG "EPDC_FORMAT 0x%x\n", __raw_readl(EPDC_FORMAT));
printk(KERN_DEBUG "EPDC_FIFOCTRL 0x%x\n", __raw_readl(EPDC_FIFOCTRL));
printk(KERN_DEBUG "EPDC_UPD_ADDR 0x%x\n", __raw_readl(EPDC_UPD_ADDR));
printk(KERN_DEBUG "EPDC_UPD_FIXED 0x%x\n", __raw_readl(EPDC_UPD_FIXED));
printk(KERN_DEBUG "EPDC_UPD_CORD 0x%x\n", __raw_readl(EPDC_UPD_CORD));
printk(KERN_DEBUG "EPDC_UPD_SIZE 0x%x\n", __raw_readl(EPDC_UPD_SIZE));
printk(KERN_DEBUG "EPDC_UPD_CTRL 0x%x\n", __raw_readl(EPDC_UPD_CTRL));
printk(KERN_DEBUG "EPDC_TEMP 0x%x\n", __raw_readl(EPDC_TEMP));
printk(KERN_DEBUG "EPDC_TCE_CTRL 0x%x\n", __raw_readl(EPDC_TCE_CTRL));
printk(KERN_DEBUG "EPDC_TCE_SDCFG 0x%x\n", __raw_readl(EPDC_TCE_SDCFG));
printk(KERN_DEBUG "EPDC_TCE_GDCFG 0x%x\n", __raw_readl(EPDC_TCE_GDCFG));
printk(KERN_DEBUG "EPDC_TCE_HSCAN1 0x%x\n", __raw_readl(EPDC_TCE_HSCAN1));
printk(KERN_DEBUG "EPDC_TCE_HSCAN2 0x%x\n", __raw_readl(EPDC_TCE_HSCAN2));
printk(KERN_DEBUG "EPDC_TCE_VSCAN 0x%x\n", __raw_readl(EPDC_TCE_VSCAN));
printk(KERN_DEBUG "EPDC_TCE_OE 0x%x\n", __raw_readl(EPDC_TCE_OE));
printk(KERN_DEBUG "EPDC_TCE_POLARITY 0x%x\n", __raw_readl(EPDC_TCE_POLARITY));
printk(KERN_DEBUG "EPDC_TCE_TIMING1 0x%x\n", __raw_readl(EPDC_TCE_TIMING1));
printk(KERN_DEBUG "EPDC_TCE_TIMING2 0x%x\n", __raw_readl(EPDC_TCE_TIMING2));
printk(KERN_DEBUG "EPDC_TCE_TIMING3 0x%x\n", __raw_readl(EPDC_TCE_TIMING3));
printk(KERN_DEBUG "EPDC_IRQ_MASK 0x%x\n", __raw_readl(EPDC_IRQ_MASK));
printk(KERN_DEBUG "EPDC_IRQ 0x%x\n", __raw_readl(EPDC_IRQ));
printk(KERN_DEBUG "EPDC_STATUS_LUTS 0x%x\n", __raw_readl(EPDC_STATUS_LUTS));
printk(KERN_DEBUG "EPDC_STATUS_NEXTLUT 0x%x\n", __raw_readl(EPDC_STATUS_NEXTLUT));
printk(KERN_DEBUG "EPDC_STATUS_COL 0x%x\n", __raw_readl(EPDC_STATUS_COL));
printk(KERN_DEBUG "EPDC_STATUS 0x%x\n", __raw_readl(EPDC_STATUS));
printk(KERN_DEBUG "EPDC_DEBUG 0x%x\n", __raw_readl(EPDC_DEBUG));
printk(KERN_DEBUG "EPDC_DEBUG_LUT0 0x%x\n", __raw_readl(EPDC_DEBUG_LUT0));
printk(KERN_DEBUG "EPDC_DEBUG_LUT1 0x%x\n", __raw_readl(EPDC_DEBUG_LUT1));
printk(KERN_DEBUG "EPDC_DEBUG_LUT2 0x%x\n", __raw_readl(EPDC_DEBUG_LUT2));
printk(KERN_DEBUG "EPDC_DEBUG_LUT3 0x%x\n", __raw_readl(EPDC_DEBUG_LUT3));
printk(KERN_DEBUG "EPDC_DEBUG_LUT4 0x%x\n", __raw_readl(EPDC_DEBUG_LUT4));
printk(KERN_DEBUG "EPDC_DEBUG_LUT5 0x%x\n", __raw_readl(EPDC_DEBUG_LUT5));
printk(KERN_DEBUG "EPDC_DEBUG_LUT6 0x%x\n", __raw_readl(EPDC_DEBUG_LUT6));
printk(KERN_DEBUG "EPDC_DEBUG_LUT7 0x%x\n", __raw_readl(EPDC_DEBUG_LUT7));
printk(KERN_DEBUG "EPDC_DEBUG_LUT8 0x%x\n", __raw_readl(EPDC_DEBUG_LUT8));
printk(KERN_DEBUG "EPDC_DEBUG_LUT9 0x%x\n", __raw_readl(EPDC_DEBUG_LUT9));
printk(KERN_DEBUG "EPDC_DEBUG_LUT10 0x%x\n", __raw_readl(EPDC_DEBUG_LUT10));
printk(KERN_DEBUG "EPDC_DEBUG_LUT11 0x%x\n", __raw_readl(EPDC_DEBUG_LUT11));
printk(KERN_DEBUG "EPDC_DEBUG_LUT12 0x%x\n", __raw_readl(EPDC_DEBUG_LUT12));
printk(KERN_DEBUG "EPDC_DEBUG_LUT13 0x%x\n", __raw_readl(EPDC_DEBUG_LUT13));
printk(KERN_DEBUG "EPDC_DEBUG_LUT14 0x%x\n", __raw_readl(EPDC_DEBUG_LUT14));
printk(KERN_DEBUG "EPDC_DEBUG_LUT15 0x%x\n", __raw_readl(EPDC_DEBUG_LUT15));
printk(KERN_DEBUG "EPDC_GPIO 0x%x\n", __raw_readl(EPDC_GPIO));
printk(KERN_DEBUG "EPDC_VERSION 0x%x\n", __raw_readl(EPDC_VERSION));
printk(KERN_DEBUG "\n\n");
}
static void dump_update_data(struct device *dev,
struct update_data_list *upd_data_list)
{
dev_info(dev,
"X = %d, Y = %d, Width = %d, Height = %d, WaveMode = %d, "
"LUT = %d, Coll Mask = 0x%x, order = %d\n",
upd_data_list->update_desc->upd_data.update_region.left,
upd_data_list->update_desc->upd_data.update_region.top,
upd_data_list->update_desc->upd_data.update_region.width,
upd_data_list->update_desc->upd_data.update_region.height,
upd_data_list->update_desc->upd_data.waveform_mode,
upd_data_list->lut_num,
upd_data_list->collision_mask,
upd_data_list->update_desc->update_order);
}
static void dump_collision_list(struct mxc_epdc_fb_data *fb_data)
{
struct update_data_list *plist;
dev_info(fb_data->dev, "Collision List:\n");
if (list_empty(&fb_data->upd_buf_collision_list))
dev_info(fb_data->dev, "Empty");
list_for_each_entry(plist, &fb_data->upd_buf_collision_list, list) {
dev_info(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
(u32)plist->virt_addr, plist->phys_addr);
dump_update_data(fb_data->dev, plist);
}
}
static void dump_free_list(struct mxc_epdc_fb_data *fb_data)
{
struct update_data_list *plist;
dev_info(fb_data->dev, "Free List:\n");
if (list_empty(&fb_data->upd_buf_free_list))
dev_info(fb_data->dev, "Empty");
list_for_each_entry(plist, &fb_data->upd_buf_free_list, list)
dev_info(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
(u32)plist->virt_addr, plist->phys_addr);
}
static void dump_queue(struct mxc_epdc_fb_data *fb_data)
{
struct update_data_list *plist;
dev_info(fb_data->dev, "Queue:\n");
if (list_empty(&fb_data->upd_buf_queue))
dev_info(fb_data->dev, "Empty");
list_for_each_entry(plist, &fb_data->upd_buf_queue, list) {
dev_info(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
(u32)plist->virt_addr, plist->phys_addr);
dump_update_data(fb_data->dev, plist);
}
}
static void dump_desc_data(struct device *dev,
struct update_desc_list *upd_desc_list)
{
dev_info(dev,
"X = %d, Y = %d, Width = %d, Height = %d, WaveMode = %d, "
"order = %d\n",
upd_desc_list->upd_data.update_region.left,
upd_desc_list->upd_data.update_region.top,
upd_desc_list->upd_data.update_region.width,
upd_desc_list->upd_data.update_region.height,
upd_desc_list->upd_data.waveform_mode,
upd_desc_list->update_order);
}
static void dump_pending_list(struct mxc_epdc_fb_data *fb_data)
{
struct update_desc_list *plist;
dev_info(fb_data->dev, "Queue:\n");
if (list_empty(&fb_data->upd_pending_list))
dev_info(fb_data->dev, "Empty");
list_for_each_entry(plist, &fb_data->upd_pending_list, list)
dump_desc_data(fb_data->dev, plist);
}
static void dump_all_updates(struct mxc_epdc_fb_data *fb_data)
{
dump_free_list(fb_data);
dump_queue(fb_data);
dump_collision_list(fb_data);
dev_info(fb_data->dev, "Current update being processed:\n");
if (fb_data->cur_update == NULL)
dev_info(fb_data->dev, "No current update\n");
else
dump_update_data(fb_data->dev, fb_data->cur_update);
}
#else
static inline void dump_pxp_config(struct mxc_epdc_fb_data *fb_data,
struct pxp_config_data *pxp_conf) {}
static inline void dump_epdc_reg(void) {}
static inline void dump_update_data(struct device *dev,
struct update_data_list *upd_data_list) {}
static inline void dump_collision_list(struct mxc_epdc_fb_data *fb_data) {}
static inline void dump_free_list(struct mxc_epdc_fb_data *fb_data) {}
static inline void dump_queue(struct mxc_epdc_fb_data *fb_data) {}
static inline void dump_all_updates(struct mxc_epdc_fb_data *fb_data) {}
#endif
/********************************************************
* Start Low-Level EPDC Functions
********************************************************/
static inline void epdc_lut_complete_intr(u32 lut_num, bool enable)
{
if (enable)
__raw_writel(1 << lut_num, EPDC_IRQ_MASK_SET);
else
__raw_writel(1 << lut_num, EPDC_IRQ_MASK_CLEAR);
}
static inline void epdc_working_buf_intr(bool enable)
{
if (enable)
__raw_writel(EPDC_IRQ_WB_CMPLT_IRQ, EPDC_IRQ_MASK_SET);
else
__raw_writel(EPDC_IRQ_WB_CMPLT_IRQ, EPDC_IRQ_MASK_CLEAR);
}
static inline void epdc_clear_working_buf_irq(void)
{
__raw_writel(EPDC_IRQ_WB_CMPLT_IRQ | EPDC_IRQ_LUT_COL_IRQ,
EPDC_IRQ_CLEAR);
}
static inline void epdc_eof_intr(bool enable)
{
if (enable)
__raw_writel(EPDC_IRQ_FRAME_END_IRQ, EPDC_IRQ_MASK_SET);
else
__raw_writel(EPDC_IRQ_FRAME_END_IRQ, EPDC_IRQ_MASK_CLEAR);
}
static inline void epdc_clear_eof_irq(void)
{
__raw_writel(EPDC_IRQ_FRAME_END_IRQ, EPDC_IRQ_CLEAR);
}
static inline bool epdc_signal_eof(void)
{
return (__raw_readl(EPDC_IRQ_MASK) & __raw_readl(EPDC_IRQ)
& EPDC_IRQ_FRAME_END_IRQ) ? true : false;
}
static inline void epdc_set_temp(u32 temp)
{
__raw_writel(temp, EPDC_TEMP);
}
static inline void epdc_set_screen_res(u32 width, u32 height)
{
u32 val = (height << EPDC_RES_VERTICAL_OFFSET) | width;
__raw_writel(val, EPDC_RES);
}
static inline void epdc_set_update_addr(u32 addr)
{
__raw_writel(addr, EPDC_UPD_ADDR);
}
static inline void epdc_set_update_coord(u32 x, u32 y)
{
u32 val = (y << EPDC_UPD_CORD_YCORD_OFFSET) | x;
__raw_writel(val, EPDC_UPD_CORD);
}
static inline void epdc_set_update_dimensions(u32 width, u32 height)
{
u32 val = (height << EPDC_UPD_SIZE_HEIGHT_OFFSET) | width;
__raw_writel(val, EPDC_UPD_SIZE);
}
static void epdc_submit_update(u32 lut_num, u32 waveform_mode, u32 update_mode,
bool use_test_mode, u32 np_val)
{
u32 reg_val = 0;
if (use_test_mode) {
reg_val |=
((np_val << EPDC_UPD_FIXED_FIXNP_OFFSET) &
EPDC_UPD_FIXED_FIXNP_MASK) | EPDC_UPD_FIXED_FIXNP_EN;
__raw_writel(reg_val, EPDC_UPD_FIXED);
reg_val = EPDC_UPD_CTRL_USE_FIXED;
} else {
__raw_writel(reg_val, EPDC_UPD_FIXED);
}
reg_val |=
((lut_num << EPDC_UPD_CTRL_LUT_SEL_OFFSET) &
EPDC_UPD_CTRL_LUT_SEL_MASK) |
((waveform_mode << EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET) &
EPDC_UPD_CTRL_WAVEFORM_MODE_MASK) |
update_mode;
__raw_writel(reg_val, EPDC_UPD_CTRL);
}
static inline bool epdc_is_lut_complete(u32 lut_num)
{
u32 val = __raw_readl(EPDC_IRQ);
bool is_compl = val & (1 << lut_num) ? true : false;
return is_compl;
}
static inline void epdc_clear_lut_complete_irq(u32 lut_num)
{
__raw_writel(1 << lut_num, EPDC_IRQ_CLEAR);
}
static inline bool epdc_is_lut_active(u32 lut_num)
{
u32 val = __raw_readl(EPDC_STATUS_LUTS);
bool is_active = val & (1 << lut_num) ? true : false;
return is_active;
}
static inline bool epdc_any_luts_active(void)
{
bool any_active = __raw_readl(EPDC_STATUS_LUTS) ? true : false;
return any_active;
}
static inline bool epdc_any_luts_available(void)
{
bool luts_available =
(__raw_readl(EPDC_STATUS_NEXTLUT) &
EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID) ? true : false;
return luts_available;
}
static inline int epdc_get_next_lut(void)
{
u32 val =
__raw_readl(EPDC_STATUS_NEXTLUT) &
EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK;
return val;
}
static int epdc_choose_next_lut(int *next_lut)
{
u32 luts_status = __raw_readl(EPDC_STATUS_LUTS);
*next_lut = fls(luts_status & 0xFFFF);
if (*next_lut > 15)
*next_lut = epdc_get_next_lut();
if (luts_status & 0x8000)
return 1;
else
return 0;
}
static inline bool epdc_is_working_buffer_busy(void)
{
u32 val = __raw_readl(EPDC_STATUS);
bool is_busy = (val & EPDC_STATUS_WB_BUSY) ? true : false;
return is_busy;
}
static inline bool epdc_is_working_buffer_complete(void)
{
u32 val = __raw_readl(EPDC_IRQ);
bool is_compl = (val & EPDC_IRQ_WB_CMPLT_IRQ) ? true : false;
return is_compl;
}
static inline bool epdc_is_collision(void)
{
u32 val = __raw_readl(EPDC_IRQ);
return (val & EPDC_IRQ_LUT_COL_IRQ) ? true : false;
}
static inline int epdc_get_colliding_luts(void)
{
u32 val = __raw_readl(EPDC_STATUS_COL);
return val;
}
static void epdc_set_horizontal_timing(u32 horiz_start, u32 horiz_end,
u32 hsync_width, u32 hsync_line_length)
{
u32 reg_val =
((hsync_width << EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET) &
EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK)
| ((hsync_line_length << EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET) &
EPDC_TCE_HSCAN1_LINE_SYNC_MASK);
__raw_writel(reg_val, EPDC_TCE_HSCAN1);
reg_val =
((horiz_start << EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET) &
EPDC_TCE_HSCAN2_LINE_BEGIN_MASK)
| ((horiz_end << EPDC_TCE_HSCAN2_LINE_END_OFFSET) &
EPDC_TCE_HSCAN2_LINE_END_MASK);
__raw_writel(reg_val, EPDC_TCE_HSCAN2);
}
static void epdc_set_vertical_timing(u32 vert_start, u32 vert_end,
u32 vsync_width)
{
u32 reg_val =
((vert_start << EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET) &
EPDC_TCE_VSCAN_FRAME_BEGIN_MASK)
| ((vert_end << EPDC_TCE_VSCAN_FRAME_END_OFFSET) &
EPDC_TCE_VSCAN_FRAME_END_MASK)
| ((vsync_width << EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET) &
EPDC_TCE_VSCAN_FRAME_SYNC_MASK);
__raw_writel(reg_val, EPDC_TCE_VSCAN);
}
void epdc_init_settings(struct mxc_epdc_fb_data *fb_data)
{
struct mxc_epdc_fb_mode *epdc_mode = fb_data->cur_mode;
struct fb_var_screeninfo *screeninfo = &fb_data->epdc_fb_var;
u32 reg_val;
int num_ce;
/* Reset */
__raw_writel(EPDC_CTRL_SFTRST, EPDC_CTRL_SET);
while (!(__raw_readl(EPDC_CTRL) & EPDC_CTRL_CLKGATE))
;
__raw_writel(EPDC_CTRL_SFTRST, EPDC_CTRL_CLEAR);
/* Enable clock gating (clear to enable) */
__raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_CLEAR);
while (__raw_readl(EPDC_CTRL) & (EPDC_CTRL_SFTRST | EPDC_CTRL_CLKGATE))
;
/* EPDC_CTRL */
reg_val = __raw_readl(EPDC_CTRL);
reg_val &= ~EPDC_CTRL_UPD_DATA_SWIZZLE_MASK;
reg_val |= EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP;
reg_val &= ~EPDC_CTRL_LUT_DATA_SWIZZLE_MASK;
reg_val |= EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP;
__raw_writel(reg_val, EPDC_CTRL_SET);
/* EPDC_FORMAT - 2bit TFT and 4bit Buf pixel format */
reg_val = EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT
| EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N
| ((0x0 << EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET) &
EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK);
__raw_writel(reg_val, EPDC_FORMAT);
/* EPDC_FIFOCTRL (disabled) */
reg_val =
((100 << EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET) &
EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK)
| ((200 << EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET) &
EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK)
| ((100 << EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET) &
EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK);
__raw_writel(reg_val, EPDC_FIFOCTRL);
/* EPDC_TEMP - Use default temp to get index */
epdc_set_temp(mxc_epdc_fb_get_temp_index(fb_data, DEFAULT_TEMP));
/* EPDC_RES */
epdc_set_screen_res(epdc_mode->vmode->xres, epdc_mode->vmode->yres);
/*
* EPDC_TCE_CTRL
* VSCAN_HOLDOFF = 4
* VCOM_MODE = MANUAL
* VCOM_VAL = 0
* DDR_MODE = DISABLED
* LVDS_MODE_CE = DISABLED
* LVDS_MODE = DISABLED
* DUAL_SCAN = DISABLED
* SDDO_WIDTH = 8bit
* PIXELS_PER_SDCLK = 4
*/
reg_val =
((epdc_mode->vscan_holdoff << EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET) &
EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK)
| EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4;
__raw_writel(reg_val, EPDC_TCE_CTRL);
/* EPDC_TCE_HSCAN */
epdc_set_horizontal_timing(screeninfo->left_margin,
screeninfo->right_margin,
screeninfo->hsync_len,
screeninfo->hsync_len);
/* EPDC_TCE_VSCAN */
epdc_set_vertical_timing(screeninfo->upper_margin,
screeninfo->lower_margin,
screeninfo->vsync_len);
/* EPDC_TCE_OE */
reg_val =
((epdc_mode->sdoed_width << EPDC_TCE_OE_SDOED_WIDTH_OFFSET) &
EPDC_TCE_OE_SDOED_WIDTH_MASK)
| ((epdc_mode->sdoed_delay << EPDC_TCE_OE_SDOED_DLY_OFFSET) &
EPDC_TCE_OE_SDOED_DLY_MASK)
| ((epdc_mode->sdoez_width << EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET) &
EPDC_TCE_OE_SDOEZ_WIDTH_MASK)
| ((epdc_mode->sdoez_delay << EPDC_TCE_OE_SDOEZ_DLY_OFFSET) &
EPDC_TCE_OE_SDOEZ_DLY_MASK);
__raw_writel(reg_val, EPDC_TCE_OE);
/* EPDC_TCE_TIMING1 */
__raw_writel(0x0, EPDC_TCE_TIMING1);
/* EPDC_TCE_TIMING2 */
reg_val =
((epdc_mode->gdclk_hp_offs << EPDC_TCE_TIMING2_GDCLK_HP_OFFSET) &
EPDC_TCE_TIMING2_GDCLK_HP_MASK)
| ((epdc_mode->gdsp_offs << EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET) &
EPDC_TCE_TIMING2_GDSP_OFFSET_MASK);
__raw_writel(reg_val, EPDC_TCE_TIMING2);
/* EPDC_TCE_TIMING3 */
reg_val =
((epdc_mode->gdoe_offs << EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET) &
EPDC_TCE_TIMING3_GDOE_OFFSET_MASK)
| ((epdc_mode->gdclk_offs << EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET) &
EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK);
__raw_writel(reg_val, EPDC_TCE_TIMING3);
/*
* EPDC_TCE_SDCFG
* SDCLK_HOLD = 1
* SDSHR = 1
* NUM_CE = 1
* SDDO_REFORMAT = FLIP_PIXELS
* SDDO_INVERT = DISABLED
* PIXELS_PER_CE = display horizontal resolution
*/
num_ce = epdc_mode->num_ce;
if (num_ce == 0)
num_ce = 1;
reg_val = EPDC_TCE_SDCFG_SDCLK_HOLD | EPDC_TCE_SDCFG_SDSHR
| ((num_ce << EPDC_TCE_SDCFG_NUM_CE_OFFSET) &
EPDC_TCE_SDCFG_NUM_CE_MASK)
| EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS
| ((epdc_mode->vmode->xres/num_ce << EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET) &
EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK);
__raw_writel(reg_val, EPDC_TCE_SDCFG);
/*
* EPDC_TCE_GDCFG
* GDRL = 1
* GDOE_MODE = 0;
* GDSP_MODE = 0;
*/
reg_val = EPDC_TCE_SDCFG_GDRL;
__raw_writel(reg_val, EPDC_TCE_GDCFG);
/*
* EPDC_TCE_POLARITY
* SDCE_POL = ACTIVE LOW
* SDLE_POL = ACTIVE HIGH
* SDOE_POL = ACTIVE HIGH
* GDOE_POL = ACTIVE HIGH
* GDSP_POL = ACTIVE LOW
*/
reg_val = EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH
| EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH
| EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH;
__raw_writel(reg_val, EPDC_TCE_POLARITY);
/* EPDC_IRQ_MASK */
__raw_writel(EPDC_IRQ_TCE_UNDERRUN_IRQ, EPDC_IRQ_MASK);
/*
* EPDC_GPIO
* PWRCOM = ?
* PWRCTRL = ?
* BDR = ?
*/
reg_val = ((0 << EPDC_GPIO_PWRCTRL_OFFSET) & EPDC_GPIO_PWRCTRL_MASK)
| ((0 << EPDC_GPIO_BDR_OFFSET) & EPDC_GPIO_BDR_MASK);
__raw_writel(reg_val, EPDC_GPIO);
}
static void epdc_powerup(struct mxc_epdc_fb_data *fb_data)
{
int ret = 0;
int iChk;
mutex_lock(&fb_data->power_mutex);
/*
* If power down request is pending, clear
* powering_down to cancel the request.
*/
if (fb_data->powering_down)
fb_data->powering_down = false;
if (fb_data->power_state == POWER_STATE_ON) {
mutex_unlock(&fb_data->power_mutex);
return;
}
dev_dbg(fb_data->dev, "EPDC Powerup\n");
fb_data->updates_active = true;
if(6==gptHWCFG->m_val.bDisplayCtrl) {
#if 1
// imx508 + tps16585 .
unsigned long dwTPS65185_mode = TPS65185_MODE_ACTIVE;
iChk = tps65185_chg_mode(&dwTPS65185_mode,1);
if(iChk<0) {
printk(KERN_ERR "%s(%d):[warning] change to power active fail,errno=%d !\n",
__FILE__,__LINE__,iChk);
}
/*
iChk = tps65185_wait_panel_poweron();
if(iChk<0) {
printk(KERN_ERR "%s(%d):[warning] wait power on fail,errno=%d !\n",
__FILE__,__LINE__,iChk);
}
*/
//gpio_direction_output(EPDC_VCOM, 1);
//msleep(10);
#endif
}
else
{
gpio_direction_output(GPIO_PWRALL, 1);msleep(50);
gpio_direction_output(EPDC_VCOM, 1);msleep(15);
}
/* Enable pins used by EPDC */
if (fb_data->pdata->enable_pins)
fb_data->pdata->enable_pins();
/* Enable clocks to EPDC */
clk_enable(fb_data->epdc_clk_axi);
clk_enable(fb_data->epdc_clk_pix);
__raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_CLEAR);
#ifdef USE_PMIC
/* Enable power to the EPD panel */
ret = regulator_enable(fb_data->display_regulator);
if (IS_ERR((void *)ret)) {
dev_err(fb_data->dev, "Unable to enable DISPLAY regulator."
"err = 0x%x\n", ret);
mutex_unlock(&fb_data->power_mutex);
return;
}
ret = regulator_enable(fb_data->vcom_regulator);
if (IS_ERR((void *)ret)) {
dev_err(fb_data->dev, "Unable to enable VCOM regulator."
"err = 0x%x\n", ret);
mutex_unlock(&fb_data->power_mutex);
return;
}
#else
#endif
fb_data->power_state = POWER_STATE_ON;
mutex_unlock(&fb_data->power_mutex);
}
static void epdc_powerdown(struct mxc_epdc_fb_data *fb_data)
{
int iChk;
GALLEN_DBGLOCAL_BEGIN();
mutex_lock(&fb_data->power_mutex);
/* If powering_down has been cleared, a powerup
* request is pre-empting this powerdown request.
*/
if (!fb_data->powering_down
|| (fb_data->power_state == POWER_STATE_OFF)) {
mutex_unlock(&fb_data->power_mutex);
GALLEN_DBGLOCAL_ESC();
return;
}
dev_dbg(fb_data->dev, "EPDC Powerdown\n");
#ifdef USE_PMIC
/* Disable power to the EPD panel */
regulator_disable(fb_data->vcom_regulator);
regulator_disable(fb_data->display_regulator);
#else
#endif
/* Disable clocks to EPDC */
__raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_SET);
clk_disable(fb_data->epdc_clk_pix);