/
core.cc
4553 lines (4239 loc) · 256 KB
/
core.cc
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/*****************************************************************************
* McPAT
* SOFTWARE LICENSE AGREEMENT
* Copyright 2012 Hewlett-Packard Development Company, L.P.
* All Rights Reserved
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
*
***************************************************************************/
#include "io.h"
#include "parameter.h"
#include "const.h"
#include "basic_circuit.h"
#include <iostream>
#include <algorithm>
#include "XML_Parse.h"
#include <string>
#include <cmath>
#include <assert.h>
#include "core.h"
//#include "globalvar.h"
#define debug_ 0
InstFetchU::InstFetchU(ParseXML* XML_interface, int ithCore_, InputParameter* interface_ip_, const CoreDynParam & dyn_p_, bool exist_)
:XML(XML_interface),
ithCore(ithCore_),
interface_ip(*interface_ip_),
coredynp(dyn_p_),
IB (0),
BTB (0),
ID_inst (0),
ID_operand (0),
ID_misc (0),
exist(exist_)
{
if (!exist) return;
int idx, tag, data, size, line, assoc, banks;
bool debug= false, is_default = true;
clockRate = coredynp.clockRate;
executionTime = coredynp.executionTime;
cache_p = (Cache_policy)XML->sys.core[ithCore].icache.icache_config[7];
//Assuming all L1 caches are virtually idxed physically tagged.
//cache
size = (int)XML->sys.core[ithCore].icache.icache_config[0];
line = (int)XML->sys.core[ithCore].icache.icache_config[1];
assoc = (int)XML->sys.core[ithCore].icache.icache_config[2];
banks = (int)XML->sys.core[ithCore].icache.icache_config[3];
idx = debug?9:int(ceil(log2(size/line/assoc)));
tag = debug?51:(int)XML->sys.physical_address_width-idx-int(ceil(log2(line))) + EXTRA_TAG_BITS;
interface_ip.specific_tag = 1;
interface_ip.tag_w = tag;
interface_ip.cache_sz = debug?32768:(int)XML->sys.core[ithCore].icache.icache_config[0];
interface_ip.line_sz = debug?64:(int)XML->sys.core[ithCore].icache.icache_config[1];
interface_ip.assoc = debug?8:(int)XML->sys.core[ithCore].icache.icache_config[2];
interface_ip.nbanks = debug?1:(int)XML->sys.core[ithCore].icache.icache_config[3];
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.access_mode = 0;//debug?0:XML->sys.core[ithCore].icache.icache_config[5];
interface_ip.throughput = debug?1.0/clockRate:XML->sys.core[ithCore].icache.icache_config[4]/clockRate;
interface_ip.latency = debug?3.0/clockRate:XML->sys.core[ithCore].icache.icache_config[5]/clockRate;
interface_ip.is_cache = true;
interface_ip.pure_cam = false;
interface_ip.pure_ram = false;
interface_ip.num_rw_ports = debug?1:XML->sys.core[ithCore].number_instruction_fetch_ports;
interface_ip.num_rd_ports = 0;
interface_ip.num_wr_ports = 0;
interface_ip.num_se_rd_ports = 0;
if(debug_)
cout << "icache, techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
icache.caches = new ArrayST(&interface_ip, "icache", Core_device, coredynp.opt_local, coredynp.core_ty);
scktRatio = g_tp.sckt_co_eff;
chip_PR_overhead = g_tp.chip_layout_overhead;
macro_PR_overhead = g_tp.macro_layout_overhead;
icache.area.set_area(icache.area.get_area()+ icache.caches->local_result.area);
area.set_area(area.get_area()+ icache.caches->local_result.area);
//output_data_csv(icache.caches.local_result);
/*
*iCache controllers
*miss buffer Each MSHR contains enough state
*to handle one or more accesses of any type to a single memory line.
*Due to the generality of the MSHR mechanism,
*the amount of state involved is non-trivial:
*including the address, pointers to the cache entry and destination register,
*written data, and various other pieces of state.
*/
interface_ip.num_search_ports = debug?1:XML->sys.core[ithCore].number_instruction_fetch_ports;
tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;
data = (XML->sys.physical_address_width) + int(ceil(log2(size/line))) + icache.caches->l_ip.line_sz*8;
interface_ip.specific_tag = 1;
interface_ip.tag_w = tag;
interface_ip.line_sz = int(ceil(data/8.0));//int(ceil(pow(2.0,ceil(log2(data)))/8.0));
interface_ip.cache_sz = XML->sys.core[ithCore].icache.buffer_sizes[0]*interface_ip.line_sz;
interface_ip.assoc = 0;
interface_ip.nbanks = 1;
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.access_mode = 0;
interface_ip.throughput = debug?1.0/clockRate:XML->sys.core[ithCore].icache.icache_config[4]/clockRate;//means cycle time
interface_ip.latency = debug?1.0/clockRate:XML->sys.core[ithCore].icache.icache_config[5]/clockRate;//means access time
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
interface_ip.num_rw_ports = debug?1:XML->sys.core[ithCore].number_instruction_fetch_ports;
interface_ip.num_rd_ports = 0;
interface_ip.num_wr_ports = 0;
interface_ip.num_se_rd_ports = 0;
interface_ip.num_search_ports = XML->sys.core[ithCore].number_instruction_fetch_ports;
if(debug_)
cout << "icache missb, techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
icache.missb = new ArrayST(&interface_ip, "icacheMissBuffer", Core_device, coredynp.opt_local, coredynp.core_ty);
icache.area.set_area(icache.area.get_area()+ icache.missb->local_result.area);
area.set_area(area.get_area()+ icache.missb->local_result.area);
//output_data_csv(icache.missb.local_result);
//fill buffer
tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;
data = icache.caches->l_ip.line_sz;
interface_ip.specific_tag = 1;
interface_ip.tag_w = tag;
interface_ip.line_sz = data;//int(pow(2.0,ceil(log2(data))));
interface_ip.cache_sz = data*XML->sys.core[ithCore].icache.buffer_sizes[1];
interface_ip.assoc = 0;
interface_ip.nbanks = 1;
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.access_mode = 0;
interface_ip.throughput = debug?1.0/clockRate:XML->sys.core[ithCore].icache.icache_config[4]/clockRate;
interface_ip.latency = debug?1.0/clockRate:XML->sys.core[ithCore].icache.icache_config[5]/clockRate;
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
interface_ip.num_rw_ports = debug?1:XML->sys.core[ithCore].number_instruction_fetch_ports;
interface_ip.num_rd_ports = 0;
interface_ip.num_wr_ports = 0;
interface_ip.num_se_rd_ports = 0;
interface_ip.num_search_ports = XML->sys.core[ithCore].number_instruction_fetch_ports;
if(debug_)
cout << "icacheFillB, techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
icache.ifb = new ArrayST(&interface_ip, "icacheFillBuffer", Core_device, coredynp.opt_local, coredynp.core_ty);
icache.area.set_area(icache.area.get_area()+ icache.ifb->local_result.area);
area.set_area(area.get_area()+ icache.ifb->local_result.area);
//output_data_csv(icache.ifb.local_result);
//prefetch buffer
tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;//check with previous entries to decide wthether to merge.
data = icache.caches->l_ip.line_sz;//separate queue to prevent from cache polution.
interface_ip.specific_tag = 1;
interface_ip.tag_w = tag;
interface_ip.line_sz = data;//int(pow(2.0,ceil(log2(data))));
interface_ip.cache_sz = XML->sys.core[ithCore].icache.buffer_sizes[2]*interface_ip.line_sz;
interface_ip.assoc = 0;
interface_ip.nbanks = 1;
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.access_mode = 0;
interface_ip.throughput = debug?1.0/clockRate:XML->sys.core[ithCore].icache.icache_config[4]/clockRate;
interface_ip.latency = debug?1.0/clockRate:XML->sys.core[ithCore].icache.icache_config[5]/clockRate;
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
interface_ip.num_rw_ports = debug?1:XML->sys.core[ithCore].number_instruction_fetch_ports;
interface_ip.num_rd_ports = 0;
interface_ip.num_wr_ports = 0;
interface_ip.num_se_rd_ports = 0;
interface_ip.num_search_ports = XML->sys.core[ithCore].number_instruction_fetch_ports;
if(debug_)
cout << "icachePrefetchB, techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
icache.prefetchb = new ArrayST(&interface_ip, "icacheprefetchBuffer", Core_device, coredynp.opt_local, coredynp.core_ty);
icache.area.set_area(icache.area.get_area()+ icache.prefetchb->local_result.area);
area.set_area(area.get_area()+ icache.prefetchb->local_result.area);
//output_data_csv(icache.prefetchb.local_result);
//Instruction buffer
data = XML->sys.core[ithCore].instruction_length*XML->sys.core[ithCore].peak_issue_width;//icache.caches.l_ip.line_sz; //multiple threads timing sharing the instruction buffer.
interface_ip.is_cache = false;
interface_ip.pure_ram = true;
interface_ip.pure_cam = false;
interface_ip.line_sz = int(ceil(data/8.0));
interface_ip.cache_sz = XML->sys.core[ithCore].number_hardware_threads*XML->sys.core[ithCore].instruction_buffer_size*interface_ip.line_sz>64?
XML->sys.core[ithCore].number_hardware_threads*XML->sys.core[ithCore].instruction_buffer_size*interface_ip.line_sz:64;
interface_ip.assoc = 1;
interface_ip.nbanks = 1;
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.access_mode = 0;
interface_ip.throughput = 1.0/clockRate;
interface_ip.latency = 1.0/clockRate;
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
//NOTE: Assuming IB is time slice shared among threads, every fetch op will at least fetch "fetch width" instructions.
interface_ip.num_rw_ports = debug?1:XML->sys.core[ithCore].number_instruction_fetch_ports;//XML->sys.core[ithCore].fetch_width;
interface_ip.num_rd_ports = 0;
interface_ip.num_wr_ports = 0;
interface_ip.num_se_rd_ports = 0;
if(debug_)
cout << "InstBuffer, techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
IB = new ArrayST(&interface_ip, "InstBuffer", Core_device, coredynp.opt_local, coredynp.core_ty);
IB->area.set_area(IB->area.get_area()+ IB->local_result.area);
area.set_area(area.get_area()+ IB->local_result.area);
//output_data_csv(IB.IB.local_result);
// inst_decoder.opcode_length = XML->sys.core[ithCore].opcode_width;
// inst_decoder.init_decoder(is_default, &interface_ip);
// inst_decoder.full_decoder_power();
if (coredynp.predictionW>0)
{
/*
* BTB branch target buffer, accessed during IF stage. Virtually indexed and virtually tagged
* It is only a cache without all the buffers in the cache controller since it is more like a
* look up table than a cache with cache controller. When access miss, no load from other places
* such as main memory (not actively fill the misses), it is passively updated under two circumstances:
* 1) when BPT@ID stage finds out current is a taken branch while BTB missed
* 2) When BPT@ID stage predicts differently than BTB
* 3) When ID stage finds out current instruction is not a branch while BTB had a hit.(mark as invalid)
* 4) when EXEU find out wrong target has been provided from BTB.
*
*/
size = XML->sys.core[ithCore].BTB.BTB_config[0];
line = XML->sys.core[ithCore].BTB.BTB_config[1];
assoc = XML->sys.core[ithCore].BTB.BTB_config[2];
banks = XML->sys.core[ithCore].BTB.BTB_config[3];
idx = debug?9:int(ceil(log2(size/line/assoc)));
// tag = debug?51:XML->sys.virtual_address_width-idx-int(ceil(log2(line))) + int(ceil(log2(XML->sys.core[ithCore].number_hardware_threads))) +EXTRA_TAG_BITS;
tag = debug?51:XML->sys.virtual_address_width + int(ceil(log2(XML->sys.core[ithCore].number_hardware_threads))) +EXTRA_TAG_BITS;
interface_ip.is_cache = true;
interface_ip.pure_ram = false;
interface_ip.pure_cam = false;
interface_ip.specific_tag = 1;
interface_ip.tag_w = tag;
interface_ip.cache_sz = debug?32768:size;
interface_ip.line_sz = debug?64:line;
interface_ip.assoc = debug?8:assoc;
interface_ip.nbanks = debug?1:banks;
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.access_mode = 0;//debug?0:XML->sys.core[ithCore].dcache.dcache_config[5];
interface_ip.throughput = debug?1.0/clockRate:XML->sys.core[ithCore].BTB.BTB_config[4]/clockRate;
interface_ip.latency = debug?3.0/clockRate:XML->sys.core[ithCore].BTB.BTB_config[5]/clockRate;
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
interface_ip.num_rw_ports = 1;
interface_ip.num_rd_ports = coredynp.predictionW;
interface_ip.num_wr_ports = coredynp.predictionW;
interface_ip.num_se_rd_ports = 0;
if(debug_)
cout << "BTB, techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
BTB = new ArrayST(&interface_ip, "Branch_Target_Buffer", Core_device, coredynp.opt_local, coredynp.core_ty);
BTB->area.set_area(BTB->area.get_area()+ BTB->local_result.area);
area.set_area(area.get_area()+ BTB->local_result.area);
///cout<<"area="<<area<<endl;
BPT = new BranchPredictor(XML, ithCore, &interface_ip,coredynp);
area.set_area(area.get_area()+ BPT->area.get_area());
}
ID_inst = new inst_decoder(is_default, &interface_ip,
coredynp.opcode_length, 1/*Decoder should not know how many by itself*/,
coredynp.x86,
Core_device, coredynp.core_ty);
ID_operand = new inst_decoder(is_default, &interface_ip,
coredynp.arch_ireg_width, 1,
coredynp.x86,
Core_device, coredynp.core_ty);
ID_misc = new inst_decoder(is_default, &interface_ip,
8/* Prefix field etc upto 14B*/, 1,
coredynp.x86,
Core_device, coredynp.core_ty);
//TODO: X86 decoder should decode the inst in cyclic mode under the control of squencer.
//So the dynamic power should be multiplied by a few times.
area.set_area(area.get_area()+ (ID_inst->area.get_area()
+ID_operand->area.get_area()
+ID_misc->area.get_area())*coredynp.decodeW);
}
BranchPredictor::BranchPredictor(ParseXML* XML_interface, int ithCore_, InputParameter* interface_ip_, const CoreDynParam & dyn_p_, bool exist_)
:XML(XML_interface),
ithCore(ithCore_),
interface_ip(*interface_ip_),
coredynp(dyn_p_),
globalBPT(0),
localBPT(0),
L1_localBPT(0),
L2_localBPT(0),
chooser(0),
RAS(0),
exist(exist_)
{
/*
* Branch Predictor, accessed during ID stage.
* McPAT's branch predictor model is the tournament branch predictor used in Alpha 21264,
* including global predictor, local two level predictor, and Chooser.
* The Branch predictor also includes a RAS (return address stack) for function calls
* Branch predictors are tagged by thread ID and modeled as 1-way associative $
* However RAS return address stacks are duplicated for each thread.
* TODO:Data Width need to be computed more precisely *
*/
if (!exist) return;
int tag, data;
clockRate = coredynp.clockRate;
executionTime = coredynp.executionTime;
interface_ip.assoc = 1;
interface_ip.pure_cam = false;
if (coredynp.multithreaded)
{
tag = int(log2(coredynp.num_hthreads)+ EXTRA_TAG_BITS);
interface_ip.specific_tag = 1;
interface_ip.tag_w = tag;
interface_ip.is_cache = true;
interface_ip.pure_ram = false;
}
else
{
interface_ip.is_cache = false;
interface_ip.pure_ram = true;
}
//Global predictor
data = int(ceil(XML->sys.core[ithCore].predictor.global_predictor_bits/8.0));
interface_ip.line_sz = data;
interface_ip.cache_sz = data*XML->sys.core[ithCore].predictor.global_predictor_entries;
interface_ip.nbanks = 1;
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.access_mode = 2;
interface_ip.throughput = 1.0/clockRate;
interface_ip.latency = 1.0/clockRate;
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
interface_ip.num_rw_ports = 0;
interface_ip.num_rd_ports = coredynp.predictionW;
interface_ip.num_wr_ports = coredynp.predictionW;
interface_ip.num_se_rd_ports = 0;
if(debug_)
cout << "Global Predictor, techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
globalBPT = new ArrayST(&interface_ip, "Global_Predictor", Core_device, coredynp.opt_local, coredynp.core_ty);
globalBPT->area.set_area(globalBPT->area.get_area()+ globalBPT->local_result.area);
area.set_area(area.get_area()+ globalBPT->local_result.area);
//Local BPT (Level 1)
data = int(ceil(XML->sys.core[ithCore].predictor.local_predictor_size[0]/8.0));
interface_ip.line_sz = data;
interface_ip.cache_sz = data*XML->sys.core[ithCore].predictor.local_predictor_entries;
interface_ip.nbanks = 1;
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.access_mode = 2;
interface_ip.throughput = 1.0/clockRate;
interface_ip.latency = 1.0/clockRate;
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
interface_ip.num_rw_ports = 0;
interface_ip.num_rd_ports = coredynp.predictionW;
interface_ip.num_wr_ports = coredynp.predictionW;
interface_ip.num_se_rd_ports = 0;
if(debug_)
cout << "L1 local predictor, techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
L1_localBPT = new ArrayST(&interface_ip, "L1_local_Predictor", Core_device, coredynp.opt_local, coredynp.core_ty);
L1_localBPT->area.set_area(L1_localBPT->area.get_area()+ L1_localBPT->local_result.area);
area.set_area(area.get_area()+ L1_localBPT->local_result.area);
//Local BPT (Level 2)
data = int(ceil(XML->sys.core[ithCore].predictor.local_predictor_size[1]/8.0));
interface_ip.line_sz = data;
interface_ip.cache_sz = data*XML->sys.core[ithCore].predictor.local_predictor_entries;
interface_ip.nbanks = 1;
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.access_mode = 2;
interface_ip.throughput = 1.0/clockRate;
interface_ip.latency = 1.0/clockRate;
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
interface_ip.num_rw_ports = 0;
interface_ip.num_rd_ports = coredynp.predictionW;
interface_ip.num_wr_ports = coredynp.predictionW;
interface_ip.num_se_rd_ports = 0;
if(debug_)
cout << "L2 local predictor, techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
L2_localBPT = new ArrayST(&interface_ip, "L2_local_Predictor", Core_device, coredynp.opt_local, coredynp.core_ty);
L2_localBPT->area.set_area(L2_localBPT->area.get_area()+ L2_localBPT->local_result.area);
area.set_area(area.get_area()+ L2_localBPT->local_result.area);
//Chooser
data = int(ceil(XML->sys.core[ithCore].predictor.chooser_predictor_bits/8.0));
interface_ip.line_sz = data;
interface_ip.cache_sz = data*XML->sys.core[ithCore].predictor.chooser_predictor_entries;
interface_ip.nbanks = 1;
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.access_mode = 2;
interface_ip.throughput = 1.0/clockRate;
interface_ip.latency = 1.0/clockRate;
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
interface_ip.num_rw_ports = 0;
interface_ip.num_rd_ports = coredynp.predictionW;
interface_ip.num_wr_ports = coredynp.predictionW;
interface_ip.num_se_rd_ports = 0;
if(debug_)
cout << "Predictor chooser, techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
chooser = new ArrayST(&interface_ip, "Predictor_Chooser", Core_device, coredynp.opt_local, coredynp.core_ty);
chooser->area.set_area(chooser->area.get_area()+ chooser->local_result.area);
area.set_area(area.get_area()+ chooser->local_result.area);
//RAS return address stacks are Duplicated for each thread.
interface_ip.is_cache = false;
interface_ip.pure_ram = true;
data = int(ceil(coredynp.pc_width/8.0));
interface_ip.line_sz = data;
interface_ip.cache_sz = data*XML->sys.core[ithCore].RAS_size;
interface_ip.assoc = 1;
interface_ip.nbanks = 1;
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.access_mode = 2;
interface_ip.throughput = 1.0/clockRate;
interface_ip.latency = 1.0/clockRate;
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
interface_ip.num_rw_ports = 0;
interface_ip.num_rd_ports = coredynp.predictionW;
interface_ip.num_wr_ports = coredynp.predictionW;
interface_ip.num_se_rd_ports = 0;
if(debug_)
cout << "RAS, techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
RAS = new ArrayST(&interface_ip, "RAS", Core_device, coredynp.opt_local, coredynp.core_ty);
RAS->area.set_area(RAS->area.get_area()+ RAS->local_result.area*coredynp.num_hthreads);
area.set_area(area.get_area()+ RAS->local_result.area*coredynp.num_hthreads);
}
SchedulerU::SchedulerU(ParseXML* XML_interface, int ithCore_, InputParameter* interface_ip_, const CoreDynParam & dyn_p_, bool exist_)
:XML(XML_interface),
ithCore(ithCore_),
interface_ip(*interface_ip_),
coredynp(dyn_p_),
int_inst_window(0),
fp_inst_window(0),
ROB(0),
instruction_selection(0),
exist(exist_)
{
if (!exist) return;
int tag, data;
bool is_default=true;
string tmp_name;
clockRate = coredynp.clockRate;
executionTime = coredynp.executionTime;
if ((coredynp.core_ty==Inorder && coredynp.multithreaded))
{
//Instruction issue queue, in-order multi-issue or multithreaded processor also has this structure. Unified window for Inorder processors
tag = int(log2(XML->sys.core[ithCore].number_hardware_threads)*coredynp.perThreadState);//This is the normal thread state bits based on Niagara Design
data = XML->sys.core[ithCore].instruction_length;
//NOTE: x86 inst can be very lengthy, up to 15B. Source: Intel® 64 and IA-32 Architectures
//Software Developer’s Manual
interface_ip.is_cache = true;
interface_ip.pure_cam = false;
interface_ip.pure_ram = false;
interface_ip.line_sz = int(ceil(data/8.0));
interface_ip.specific_tag = 1;
interface_ip.tag_w = tag;
interface_ip.cache_sz = XML->sys.core[ithCore].instruction_window_size*interface_ip.line_sz>64?XML->sys.core[ithCore].instruction_window_size*interface_ip.line_sz:64;
interface_ip.assoc = 0;
interface_ip.nbanks = 1;
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.access_mode = 1;
interface_ip.throughput = 1.0/clockRate;
interface_ip.latency = 1.0/clockRate;
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
interface_ip.num_rw_ports = 0;
interface_ip.num_rd_ports = coredynp.peak_issueW;
interface_ip.num_wr_ports = coredynp.peak_issueW;
interface_ip.num_se_rd_ports = 0;
interface_ip.num_search_ports = coredynp.peak_issueW;
if(debug_)
cout << "InO InstFetchQueue, techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
int_inst_window = new ArrayST(&interface_ip, "InstFetchQueue", Core_device, coredynp.opt_local, coredynp.core_ty);
int_inst_window->area.set_area(int_inst_window->area.get_area()+ int_inst_window->local_result.area*coredynp.num_pipelines);
area.set_area(area.get_area()+ int_inst_window->local_result.area*coredynp.num_pipelines);
//output_data_csv(iRS.RS.local_result);
Iw_height =int_inst_window->local_result.cache_ht;
/*
* selection logic
* In a single-issue Inorder multithreaded processor like Niagara, issue width=1*number_of_threads since the processor does need to pick up
* instructions from multiple ready ones(although these ready ones are from different threads).While SMT processors do not distinguish which thread belongs to who
* at the issue stage.
*/
interface_ip.assoc = 1; //reset to prevent unnecessary warning messages when init_interface
instruction_selection = new selection_logic(is_default, XML->sys.core[ithCore].instruction_window_size,
coredynp.peak_issueW*XML->sys.core[ithCore].number_hardware_threads,
&interface_ip, Core_device, coredynp.core_ty);
}
if (coredynp.core_ty==OOO)
{
/*
* CAM based instruction window
* For physicalRegFilebased OOO it is the instruction issue queue, where only tags of phy regs are stored
* For RS based OOO it is the Reservation station, where both tags and values of phy regs are stored
* It is written once and read twice(two operands) before an instruction can be issued.
* X86 instruction can be very long up to 15B. add instruction length in XML
*/
if(coredynp.scheu_ty==PhysicalRegFile)
{
tag = coredynp.phy_ireg_width;
// Each time only half of the tag is compared, but two tag should be stored.
// This underestimate the search power
data = int((ceil((coredynp.instruction_length+2*(coredynp.phy_ireg_width - coredynp.arch_ireg_width))/2.0)/8.0));
//Data width being divided by 2 means only after both operands available the whole data will be read out.
//This is modeled using two equivalent readouts with half of the data width
tmp_name = "InstIssueQueue";
}
else
{
tag = coredynp.phy_ireg_width;
// Each time only half of the tag is compared, but two tag should be stored.
// This underestimate the search power
data = int(ceil(((coredynp.instruction_length+2*(coredynp.phy_ireg_width - coredynp.arch_ireg_width)+
2*coredynp.int_data_width)/2.0)/8.0));
//Data width being divided by 2 means only after both operands available the whole data will be read out.
//This is modeled using two equivalent readouts with half of the data width
tmp_name = "IntReservationStation";
}
interface_ip.is_cache = true;
interface_ip.pure_cam = false;
interface_ip.pure_ram = false;
interface_ip.line_sz = data;
interface_ip.cache_sz = data*XML->sys.core[ithCore].instruction_window_size;
interface_ip.assoc = 0;
interface_ip.nbanks = 1;
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.specific_tag = 1;
interface_ip.tag_w = tag;
interface_ip.access_mode = 0;
interface_ip.throughput = 2*1.0/clockRate;
interface_ip.latency = 2*1.0/clockRate;
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
interface_ip.num_rw_ports = 0;
interface_ip.num_rd_ports = coredynp.peak_issueW;
interface_ip.num_wr_ports = coredynp.peak_issueW;
interface_ip.num_se_rd_ports = 0;
interface_ip.num_search_ports = coredynp.peak_issueW;
if(debug_)
cout << "OOO " << tmp_name <<", techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
int_inst_window = new ArrayST(&interface_ip, tmp_name, Core_device, coredynp.opt_local, coredynp.core_ty);
int_inst_window->area.set_area(int_inst_window->area.get_area()+ int_inst_window->local_result.area*coredynp.num_pipelines);
area.set_area(area.get_area()+ int_inst_window->local_result.area*coredynp.num_pipelines);
Iw_height =int_inst_window->local_result.cache_ht;
//FU inst window
if(coredynp.scheu_ty==PhysicalRegFile)
{
tag = 2*coredynp.phy_freg_width;// TODO: each time only half of the tag is compared
data = int(ceil((coredynp.instruction_length+2*(coredynp.phy_freg_width - coredynp.arch_freg_width))/8.0));
tmp_name = "FPIssueQueue";
}
else
{
tag = 2*coredynp.phy_ireg_width;
data = int(ceil((coredynp.instruction_length+2*(coredynp.phy_freg_width - coredynp.arch_freg_width)+
2*coredynp.fp_data_width)/8.0));
tmp_name = "FPReservationStation";
}
interface_ip.is_cache = true;
interface_ip.pure_cam = false;
interface_ip.pure_ram = false;
interface_ip.line_sz = data;
interface_ip.cache_sz = data*XML->sys.core[ithCore].fp_instruction_window_size;
interface_ip.assoc = 0;
interface_ip.nbanks = 1;
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.specific_tag = 1;
interface_ip.tag_w = tag;
interface_ip.access_mode = 0;
interface_ip.throughput = 1.0/clockRate;
interface_ip.latency = 1.0/clockRate;
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
interface_ip.num_rw_ports = 0;
interface_ip.num_rd_ports = coredynp.fp_issueW;
interface_ip.num_wr_ports = coredynp.fp_issueW;
interface_ip.num_se_rd_ports = 0;
interface_ip.num_search_ports = coredynp.fp_issueW;
if(debug_)
cout << "OOO " << tmp_name <<", techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
fp_inst_window = new ArrayST(&interface_ip, tmp_name, Core_device, coredynp.opt_local, coredynp.core_ty);
fp_inst_window->area.set_area(fp_inst_window->area.get_area()+ fp_inst_window->local_result.area*coredynp.num_fp_pipelines);
area.set_area(area.get_area()+ fp_inst_window->local_result.area*coredynp.num_fp_pipelines);
fp_Iw_height =fp_inst_window->local_result.cache_ht;
if (XML->sys.core[ithCore].ROB_size >0)
{
/*
* if ROB_size = 0, then the target processor does not support hardware-based
* speculation, i.e. , the processor allow OOO issue as well as OOO completion, which
* means branch must be resolved before instruction issued into instruction window, since
* there is no change to flush miss-predict branch path after instructions are issued in this situation.
*
* ROB.ROB size = inflight inst. ROB is unified for int and fp inst.
* One old approach is to combine the RAT and ROB as a huge CAM structure as in AMD K7.
* However, this approach is abandoned due to its high power and poor scalablility.
* McPAT uses current implementation of ROB as circular buffer.
* ROB is written once when instruction is issued and read once when the instruction is committed. *
*/
int robExtra = int(ceil(5 + log2(coredynp.num_hthreads)));
//5 bits are: busy, Issued, Finished, speculative, valid
if(coredynp.scheu_ty==PhysicalRegFile)
{
//PC is to id the instruction for recover exception.
//inst is used to map the renamed dest. registers.so that commit stage can know which reg/RRAT to update
// data = int(ceil((robExtra+coredynp.pc_width +
// coredynp.instruction_length + 2*coredynp.phy_ireg_width)/8.0));
data = int(ceil((robExtra+coredynp.pc_width +
coredynp.phy_ireg_width)/8.0));
}
else
{
//in RS based OOO, ROB also contains value of destination reg
// data = int(ceil((robExtra+coredynp.pc_width +
// coredynp.instruction_length + 2*coredynp.phy_ireg_width + coredynp.fp_data_width)/8.0));
data = int(ceil((robExtra + coredynp.pc_width +
coredynp.phy_ireg_width + coredynp.fp_data_width)/8.0));
}
interface_ip.is_cache = false;
interface_ip.pure_cam = false;
interface_ip.pure_ram = true;
interface_ip.line_sz = data;
interface_ip.cache_sz = data*XML->sys.core[ithCore].ROB_size;//The XML ROB size is for all threads
interface_ip.assoc = 1;
interface_ip.nbanks = 1;
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.access_mode = 1;
interface_ip.throughput = 1.0/clockRate;
interface_ip.latency = 1.0/clockRate;
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
interface_ip.num_rw_ports = 0;
interface_ip.num_rd_ports = coredynp.peak_commitW;
interface_ip.num_wr_ports = coredynp.peak_issueW;
interface_ip.num_se_rd_ports = 0;
interface_ip.num_search_ports = 0;
if(debug_)
cout << "OOO ROB, techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
// interface_ip.print_input_args = true; //divya debug
ROB = new ArrayST(&interface_ip, "ReorderBuffer", Core_device, coredynp.opt_local, coredynp.core_ty);
ROB->area.set_area(ROB->area.get_area()+ ROB->local_result.area*coredynp.num_pipelines);
area.set_area(area.get_area()+ ROB->local_result.area*coredynp.num_pipelines);
ROB_height =ROB->local_result.cache_ht;
}
instruction_selection = new selection_logic(is_default, XML->sys.core[ithCore].instruction_window_size,
coredynp.peak_issueW, &interface_ip, Core_device, coredynp.core_ty);
}
}
LoadStoreU::LoadStoreU(ParseXML* XML_interface, int ithCore_, InputParameter* interface_ip_, const CoreDynParam & dyn_p_,bool exist_)
:XML(XML_interface),
ithCore(ithCore_),
interface_ip(*interface_ip_),
coredynp(dyn_p_),
LSQ(0),
LoadQ(0),
exist(exist_)
{
if (!exist) return;
int idx, tag, data, size, line, assoc, banks;
bool debug= false;
int ldst_opcode = XML->sys.core[ithCore].opcode_width;//16;
clockRate = coredynp.clockRate;
executionTime = coredynp.executionTime;
cache_p = (Cache_policy)XML->sys.core[ithCore].dcache.dcache_config[7];
interface_ip.num_search_ports = XML->sys.core[ithCore].memory_ports;
interface_ip.is_cache = true;
interface_ip.pure_cam = false;
interface_ip.pure_ram = false;
//Dcache
size = (int)XML->sys.core[ithCore].dcache.dcache_config[0];
line = (int)XML->sys.core[ithCore].dcache.dcache_config[1];
assoc = (int)XML->sys.core[ithCore].dcache.dcache_config[2];
banks = (int)XML->sys.core[ithCore].dcache.dcache_config[3];
idx = debug?9:int(ceil(log2(size/line/assoc)));
tag = debug?51:XML->sys.physical_address_width-idx-int(ceil(log2(line))) + EXTRA_TAG_BITS;
interface_ip.specific_tag = 1;
interface_ip.tag_w = tag;
interface_ip.cache_sz = debug?32768:(int)XML->sys.core[ithCore].dcache.dcache_config[0];
interface_ip.line_sz = debug?64:(int)XML->sys.core[ithCore].dcache.dcache_config[1];
interface_ip.assoc = debug?8:(int)XML->sys.core[ithCore].dcache.dcache_config[2];
interface_ip.nbanks = debug?1:(int)XML->sys.core[ithCore].dcache.dcache_config[3];
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.access_mode = 0;//debug?0:XML->sys.core[ithCore].dcache.dcache_config[5];
interface_ip.throughput = debug?1.0/clockRate:XML->sys.core[ithCore].dcache.dcache_config[4]/clockRate;
interface_ip.latency = debug?3.0/clockRate:XML->sys.core[ithCore].dcache.dcache_config[5]/clockRate;
interface_ip.is_cache = true;
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
interface_ip.num_rw_ports = debug?1:XML->sys.core[ithCore].memory_ports;//usually In-order has 1 and OOO has 2 at least.
interface_ip.num_rd_ports = 0;
interface_ip.num_wr_ports = 0;
interface_ip.num_se_rd_ports = 0;
// interface_ip.print_input_args = true; //divya adding 22-11-2021 to debug
if(debug_)
cout << "dcache, techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
dcache.caches = new ArrayST(&interface_ip, "dcache", Core_device, coredynp.opt_local, coredynp.core_ty);
dcache.area.set_area(dcache.area.get_area()+ dcache.caches->local_result.area);
area.set_area(area.get_area()+ dcache.caches->local_result.area);
//output_data_csv(dcache.caches.local_result);
//dCache controllers
//miss buffer
tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;
data = (XML->sys.physical_address_width) + int(ceil(log2(size/line))) + dcache.caches->l_ip.line_sz*8;
interface_ip.specific_tag = 1;
interface_ip.tag_w = tag;
interface_ip.line_sz = int(ceil(data/8.0));//int(ceil(pow(2.0,ceil(log2(data)))/8.0));
interface_ip.cache_sz = XML->sys.core[ithCore].dcache.buffer_sizes[0]*interface_ip.line_sz;
interface_ip.assoc = 0;
interface_ip.nbanks = 1;
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.access_mode = 2;
interface_ip.throughput = debug?1.0/clockRate:XML->sys.core[ithCore].dcache.dcache_config[4]/clockRate;
interface_ip.latency = debug?1.0/clockRate:XML->sys.core[ithCore].dcache.dcache_config[5]/clockRate;
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
interface_ip.num_rw_ports = debug?1:XML->sys.core[ithCore].memory_ports;;
interface_ip.num_rd_ports = 0;
interface_ip.num_wr_ports = 0;
interface_ip.num_se_rd_ports = 0;
if(debug_)
cout << "dcacheMissB, techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
dcache.missb = new ArrayST(&interface_ip, "dcacheMissBuffer", Core_device, coredynp.opt_local, coredynp.core_ty);
dcache.area.set_area(dcache.area.get_area()+ dcache.missb->local_result.area);
area.set_area(area.get_area()+ dcache.missb->local_result.area);
//output_data_csv(dcache.missb.local_result);
//fill buffer
tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;
data = dcache.caches->l_ip.line_sz;
interface_ip.specific_tag = 1;
interface_ip.tag_w = tag;
interface_ip.line_sz = data;//int(pow(2.0,ceil(log2(data))));
interface_ip.cache_sz = data*XML->sys.core[ithCore].dcache.buffer_sizes[1];
interface_ip.assoc = 0;
interface_ip.nbanks = 1;
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.access_mode = 2;
interface_ip.throughput = debug?1.0/clockRate:XML->sys.core[ithCore].dcache.dcache_config[4]/clockRate;
interface_ip.latency = debug?1.0/clockRate:XML->sys.core[ithCore].dcache.dcache_config[5]/clockRate;
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
interface_ip.num_rw_ports = debug?1:XML->sys.core[ithCore].memory_ports;;
interface_ip.num_rd_ports = 0;
interface_ip.num_wr_ports = 0;
interface_ip.num_se_rd_ports = 0;
if(debug_)
cout << "dcacheFillB, techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
dcache.ifb = new ArrayST(&interface_ip, "dcacheFillBuffer", Core_device, coredynp.opt_local, coredynp.core_ty);
dcache.area.set_area(dcache.area.get_area()+ dcache.ifb->local_result.area);
area.set_area(area.get_area()+ dcache.ifb->local_result.area);
//output_data_csv(dcache.ifb.local_result);
//prefetch buffer
tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;//check with previous entries to decide wthether to merge.
data = dcache.caches->l_ip.line_sz;//separate queue to prevent from cache polution.
interface_ip.specific_tag = 1;
interface_ip.tag_w = tag;
interface_ip.line_sz = data;//int(pow(2.0,ceil(log2(data))));
interface_ip.cache_sz = XML->sys.core[ithCore].dcache.buffer_sizes[2]*interface_ip.line_sz;
interface_ip.assoc = 0;
interface_ip.nbanks = 1;
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.access_mode = 2;
interface_ip.throughput = debug?1.0/clockRate:XML->sys.core[ithCore].dcache.dcache_config[4]/clockRate;
interface_ip.latency = debug?1.0/clockRate:XML->sys.core[ithCore].dcache.dcache_config[5]/clockRate;
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
interface_ip.num_rw_ports = debug?1:XML->sys.core[ithCore].memory_ports;;
interface_ip.num_rd_ports = 0;
interface_ip.num_wr_ports = 0;
interface_ip.num_se_rd_ports = 0;
if(debug_)
cout << "dcachePrefetchBuffer, techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
dcache.prefetchb = new ArrayST(&interface_ip, "dcacheprefetchBuffer", Core_device, coredynp.opt_local, coredynp.core_ty);
dcache.area.set_area(dcache.area.get_area()+ dcache.prefetchb->local_result.area);
area.set_area(area.get_area()+ dcache.prefetchb->local_result.area);
//output_data_csv(dcache.prefetchb.local_result);
//WBB
if (cache_p==Write_back)
{
tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;
data = dcache.caches->l_ip.line_sz;
interface_ip.specific_tag = 1;
interface_ip.tag_w = tag;
interface_ip.line_sz = data;
interface_ip.cache_sz = XML->sys.core[ithCore].dcache.buffer_sizes[3]*interface_ip.line_sz;
interface_ip.assoc = 0;
interface_ip.nbanks = 1;
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.access_mode = 2;
interface_ip.throughput = debug?1.0/clockRate:XML->sys.core[ithCore].dcache.dcache_config[4]/clockRate;
interface_ip.latency = debug?1.0/clockRate:XML->sys.core[ithCore].dcache.dcache_config[5]/clockRate;
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
interface_ip.num_rw_ports = XML->sys.core[ithCore].memory_ports;
interface_ip.num_rd_ports = 0;
interface_ip.num_wr_ports = 0;
interface_ip.num_se_rd_ports = 0;
if(debug_)
cout << "dcacheWBB, techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
dcache.wbb = new ArrayST(&interface_ip, "dcacheWBB", Core_device, coredynp.opt_local, coredynp.core_ty);
dcache.area.set_area(dcache.area.get_area()+ dcache.wbb->local_result.area);
area.set_area(area.get_area()+ dcache.wbb->local_result.area);
//output_data_csv(dcache.wbb.local_result);
}
/*
* LSU--in-order processors do not have separate load queue: unified lsq
* partitioned among threads
* it is actually the store queue but for inorder processors it serves as both loadQ and StoreQ
*/
tag = ldst_opcode+XML->sys.virtual_address_width +int(ceil(log2(XML->sys.core[ithCore].number_hardware_threads))) + EXTRA_TAG_BITS;
data = XML->sys.machine_bits;
interface_ip.is_cache = true;
interface_ip.line_sz = int(ceil(data/32.0))*4;
interface_ip.specific_tag = 1;
interface_ip.tag_w = tag;
interface_ip.cache_sz = XML->sys.core[ithCore].store_buffer_size*interface_ip.line_sz*XML->sys.core[ithCore].number_hardware_threads;
interface_ip.assoc = 0;
interface_ip.nbanks = 1;
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.access_mode = 1;
interface_ip.throughput = 1.0/clockRate;
interface_ip.latency = 1.0/clockRate;
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
interface_ip.num_rw_ports = 0;
interface_ip.num_rd_ports = XML->sys.core[ithCore].memory_ports;
interface_ip.num_wr_ports = XML->sys.core[ithCore].memory_ports;
interface_ip.num_se_rd_ports = 0;
interface_ip.num_search_ports =XML->sys.core[ithCore].memory_ports;
if(debug_)
cout << "LSQ, techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
LSQ = new ArrayST(&interface_ip, "Load(Store)Queue", Core_device, coredynp.opt_local, coredynp.core_ty);
LSQ->area.set_area(LSQ->area.get_area()+ LSQ->local_result.area);
area.set_area(area.get_area()+ LSQ->local_result.area);
area.set_area(area.get_area()*cdb_overhead);
//output_data_csv(LSQ.LSQ.local_result);
lsq_height=LSQ->local_result.cache_ht*sqrt(cdb_overhead);/*XML->sys.core[ithCore].number_hardware_threads*/
if ((coredynp.core_ty==OOO) && (XML->sys.core[ithCore].load_buffer_size >0))
{
interface_ip.line_sz = int(ceil(data/32.0))*4;
interface_ip.specific_tag = 1;
interface_ip.tag_w = tag;
interface_ip.cache_sz = XML->sys.core[ithCore].load_buffer_size*interface_ip.line_sz*XML->sys.core[ithCore].number_hardware_threads;
interface_ip.assoc = 0;
interface_ip.nbanks = 1;
interface_ip.out_w = interface_ip.line_sz*8;
interface_ip.access_mode = 1;
interface_ip.throughput = 1.0/clockRate;
interface_ip.latency = 1.0/clockRate;
interface_ip.obj_func_dyn_energy = 0;
interface_ip.obj_func_dyn_power = 0;
interface_ip.obj_func_leak_power = 0;
interface_ip.obj_func_cycle_t = 1;
interface_ip.num_rw_ports = 0;
interface_ip.num_rd_ports = XML->sys.core[ithCore].memory_ports;
interface_ip.num_wr_ports = XML->sys.core[ithCore].memory_ports;
interface_ip.num_se_rd_ports = 0;
interface_ip.num_search_ports =XML->sys.core[ithCore].memory_ports;
if(debug_)
cout << "LoadQ, techsize: " << interface_ip.F_sz_um << ", wire: " << interface_ip.wire_F_sz_um << ", finfet: " << interface_ip.is_finfet << ", ncfet: " << interface_ip.is_ncfet <<
", itrs: " << interface_ip.is_itrs2012 << ", asap7: " << interface_ip.is_asap7 << ", projection: " << interface_ip.ic_proj_type << ", vdd: " << interface_ip.vdd
<< "Rd: " << interface_ip.num_rd_ports << ", Wr: " << interface_ip.num_wr_ports << ", rw: " << interface_ip.num_rw_ports << endl;
LoadQ = new ArrayST(&interface_ip, "LoadQueue", Core_device, coredynp.opt_local, coredynp.core_ty);
LoadQ->area.set_area(LoadQ->area.get_area()+ LoadQ->local_result.area);
area.set_area(area.get_area()+ LoadQ->local_result.area);
area.set_area(area.get_area()*cdb_overhead);
//output_data_csv(LoadQ.LoadQ.local_result);
lsq_height=(LSQ->local_result.cache_ht + LoadQ->local_result.cache_ht)*sqrt(cdb_overhead);/*XML->sys.core[ithCore].number_hardware_threads*/
}
}
MemManU::MemManU(ParseXML* XML_interface, int ithCore_, InputParameter* interface_ip_, const CoreDynParam & dyn_p_,bool exist_)
:XML(XML_interface),
ithCore(ithCore_),
interface_ip(*interface_ip_),