Does the generated Sketch support reset?

[PKUZHOU]

Hi dear author.

First of all, thanks very much for your wonderful work! It is rare to see open-sourced hardware projects like this.

I am planing to use Scotch in my FPGA design which requires a CM-Sketch module. However, according to my knowledge the generated sketch does not have a reset logic, which is useful to reset all the counters to zero. Do I miss something?

What's more. May I ask how to readout the counters in the CM-Sketch array? In the tl.vhl I can only see this :

process(clk)
begin
if rising_edge(clk) then
sout1 <= parity(sketch_rd_data_out) xor sketch_rd_valid_out;
end if;
end process;

It seems that this is just a dummy logic to get some one-bit info from sketch array.

Any suggestions are welcome! Thank you again.