This repository has been archived by the owner on Apr 29, 2021. It is now read-only.
-
Notifications
You must be signed in to change notification settings - Fork 2
/
parser.dart
289 lines (267 loc) · 6.75 KB
/
parser.dart
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
import 'package:meta/meta.dart';
import 'evaluate.dart';
/// Operation codes implemented by the ARMv4T Architecture.
///
/// _See ARM7TDMI-S Data Sheet, Chapter 4 (ARM Instruction Set)._
const List<String> _mnemonics = const <String>[
'ADC',
'ADD',
'AND',
'B',
'BIC',
'BL',
'BX',
'CDP',
'CMN',
'CMN',
'CMP',
'EOR',
'LDC',
'LDM',
'LDR',
'MCR',
'MLA',
'MOV',
'MRC',
'MRS',
'MSR',
'MUL',
'MVN',
'ORR',
'RSB',
'RSC',
'SBC',
'STC',
'STM',
'STR',
'SUB',
'SWI',
'SWP',
'TEQ',
'TST',
'NOP',
'PUSH',
'POP',
'UMULL',
'UMLAL',
'SMULL',
'SMLAL',
'LSL',
'LSR',
'ASR',
'ROR',
'RRX',
];
/// Condition codes implemented by the ARMv4T Architecture.
///
/// _See ARM7TDMI-S Data Sheet, 4.2 Condition Fields._
const List<String> _conditions = const <String>[
'EQ',
'NE',
'CS',
'CC',
'MI',
'PL',
'VS',
'VC',
'HI',
'LS',
'GE',
'LT',
'GT',
'LE',
'AL',
];
class _Suffix {
/// A standard 'S' suffix.
static const _Suffix $S = const _Suffix(suffixes: const ['S']);
final List<String> suffixes;
final bool isMode;
final bool isRequired;
const _Suffix({
@required this.suffixes,
this.isMode: false,
this.isRequired: false,
});
}
/// Suffix each mnemonic can or must have.
///
/// Any mnemonic not listed doesn't have supported suffixes.
const Map<String, _Suffix> _suffixes = const <String, _Suffix>{
'AND': _Suffix.$S,
'EOR': _Suffix.$S,
'SUB': _Suffix.$S,
'RSB': _Suffix.$S,
'ADD': _Suffix.$S,
'ADC': _Suffix.$S,
'SBC': _Suffix.$S,
'RSC': _Suffix.$S,
'ORR': _Suffix.$S,
'BIC': _Suffix.$S,
'MUL': _Suffix.$S,
'MLA': _Suffix.$S,
'MOV': _Suffix.$S,
'MVN': _Suffix.$S,
'ASR': _Suffix.$S,
'ROR': _Suffix.$S,
'RRX': _Suffix.$S,
'SWP': const _Suffix(suffixes: const ['B']),
'LDC': const _Suffix(suffixes: const ['L']),
'STC': const _Suffix(suffixes: const ['L']),
'LDR': const _Suffix(suffixes: const [
'FD',
'ED',
'FA',
'EA',
'IA',
'IB',
'DA',
'DB',
], isMode: true, isRequired: true),
'STM': const _Suffix(suffixes: const [
'FD',
'ED',
'FA',
'EA',
'IA',
'IB',
'DA',
'DB',
], isMode: true, isRequired: true),
'UMULL': _Suffix.$S,
'UMLAL': _Suffix.$S,
'SMULL': _Suffix.$S,
'SMLAL': _Suffix.$S,
'LSL': _Suffix.$S,
'LSR': _Suffix.$S,
};
List<String> _sortedByLength(Iterable<String> strings) =>
strings.toList()..sort((a, b) => a.length.compareTo(b.length));
/// Implements parsing expressions, assembler directives, operands, mnemonics.
class Armv4tParser {
static List<String> _sortedMnemonics;
const Armv4tParser();
/// Parses a mnemonic and condition field from the [input] string.
///
/// * [input]: String to parse the mnemonic, condition, and suffix from.
///
/// Returns a [ParsedMnemonic] object.
ParsedMnemonic parseMnemonic(String input) {
final line = input.replaceAll('\t', ' ').trim().split(' ');
final mnemonic = _parseMnemonic(line[0]);
final condition = _parseCondition(line[0], mnemonic);
final suffix = _parseSuffix(line[0], mnemonic, condition);
return new ParsedMnemonic(mnemonic, suffix, condition);
}
// Returns the mnemonic of the instruction to be assembled.
static String _parseMnemonic(String input) {
input = input.toUpperCase();
_sortedMnemonics ??= _sortedByLength(_mnemonics);
return _sortedMnemonics.firstWhere((m) => input.startsWith(m),
orElse: () => throw new StateError('Invalid mnemonic: "$input"'));
}
// Returns the suffix, if any, of a mnemonic of an instruction.
static String _parseSuffix(String input, String mnemonic, String condition) {
condition ??= '';
final info = _suffixes[mnemonic];
if (info == null) {
return null;
}
final look =
input.substring(mnemonic.length + condition.length).toUpperCase();
for (final suffix in info.suffixes) {
if (look.startsWith(suffix)) {
return suffix;
}
}
if (info.isRequired) {
throw new StateError('Expected suffix: "$input"');
} else {
return null;
}
}
// Returns the condition, if any, of a mnemonic of an instruction.
static String _parseCondition(String input, String mnemonic) {
final look = input.substring(mnemonic.length).toUpperCase();
for (final condition in _conditions) {
if (look.startsWith(condition)) {
return condition;
}
}
return null;
}
/// Parses an ARM register identifier from the specified [input].
///
/// * [input]: String to parse the ARM register identifier from.
///
/// Returns an ARM register identifier (R0 to R15).
String parseRegister(String input) {
input = input.trim().toUpperCase();
const alias = const {
'FP': 'R11',
'SP': 'R13',
'LR': 'R14',
'PC': 'R15',
};
if (input.length == 2) {
if (input[0] == 'R' &&
int.parse(input[1], onError: (_) => null) != null) {
return input;
}
final aliased = alias[input];
if (aliased != null) {
return aliased;
}
} else if (input.length == 3) {
if (input[0] == 'R' && input[1] == '1' && int.parse(input[2]) < 6) {
return input;
}
}
throw new FormatException('Unexpected ARM register identifier: "$input"');
}
/// Parses an ARM co-processor register identifier from the specified [input].
///
/// * [input]: String to parse the ARM register identifier from.
///
/// Returns an ARM co-processor register identifier (R0 to R15).
String parseCpRegister(String input) {
input = input.trim().toUpperCase();
if (input.length == 2) {
if (input[0] == 'C' &&
int.parse(input[1], onError: (_) => null) != null) {
return input;
}
} else if (input.length == 3) {
if (input[0] == 'C' && input[1] == '1' && int.parse(input[2]) < 6) {
return input;
}
}
throw new FormatException('Unexpcted ARM coprocessor identifier: "$input"');
}
/// Parses an [expression].
///
/// Returns the parsed and evaluated expression result.
int parseExpression(String expression, int lookup(String variable)) {
if (expression[0] == '#') {
return int.parse(expression.substring(1));
}
return (eval(expression, lookup) as num).toInt();
}
}
class ParsedMnemonic {
final String mnemonic;
final String suffix;
final String condition;
const ParsedMnemonic(this.mnemonic, [this.suffix, this.condition]);
@override
int get hashCode => mnemonic.hashCode ^ suffix.hashCode ^ condition.hashCode;
@override
bool operator ==(Object o) =>
o is ParsedMnemonic &&
o.mnemonic == mnemonic &&
o.suffix == suffix &&
o.condition == condition;
@override
String toString() =>
condition != null ? '$mnemonic${suffix ?? ''}: $condition' : mnemonic;
}