urnaEletronica.vcd

$date
	Sun Dec 02 21:34:51 2018
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module testbench $end
$var wire 2 ! votoValido [1:0] $end
$var wire 3 " next_estado [2:0] $end
$var wire 3 # estado [2:0] $end
$var wire 4 $ digito4 [3:0] $end
$var wire 4 % digito3 [3:0] $end
$var wire 4 & digito2 [3:0] $end
$var wire 4 ' digito1 [3:0] $end
$var wire 1 ( clock $end
$var wire 1 ) candidatoPablo $end
$var wire 1 * candidatoNulo $end
$var wire 1 + candidatoMateus $end
$var wire 1 , candidatoLeandro $end
$var wire 1 - candidatoArthur $end
$var wire 1 . bcdOver4_4_5 $end
$var wire 1 / bcdOver4_3_4 $end
$var wire 1 0 bcdOver4_2_3 $end
$var wire 1 1 bcdOver4_1_2 $end
$var wire 1 2 bcdOver4_0_1 $end
$var wire 1 3 bcdOver3_4_5 $end
$var wire 1 4 bcdOver3_3_4 $end
$var wire 1 5 bcdOver3_2_3 $end
$var wire 1 6 bcdOver3_1_2 $end
$var wire 1 7 bcdOver3_0_1 $end
$var wire 1 8 bcdOver2_4_5 $end
$var wire 1 9 bcdOver2_3_4 $end
$var wire 1 : bcdOver2_2_3 $end
$var wire 1 ; bcdOver2_1_2 $end
$var wire 1 < bcdOver2_0_1 $end
$var wire 1 = bcdOver1_4_5 $end
$var wire 1 > bcdOver1_3_4 $end
$var wire 1 ? bcdOver1_2_3 $end
$var wire 1 @ bcdOver1_1_2 $end
$var wire 1 A bcdOver1_0_1 $end
$var wire 1 B bcdOver0_4_5 $end
$var wire 1 C bcdOver0_3_4 $end
$var wire 1 D bcdOver0_2_3 $end
$var wire 1 E bcdOver0_1_2 $end
$var wire 1 F bcdOver0_0_1 $end
$var wire 4 G bcd4_5 [3:0] $end
$var wire 4 H bcd4_4 [3:0] $end
$var wire 4 I bcd4_3 [3:0] $end
$var wire 4 J bcd4_2 [3:0] $end
$var wire 4 K bcd4_1 [3:0] $end
$var wire 4 L bcd4_0 [3:0] $end
$var wire 4 M bcd3_5 [3:0] $end
$var wire 4 N bcd3_4 [3:0] $end
$var wire 4 O bcd3_3 [3:0] $end
$var wire 4 P bcd3_2 [3:0] $end
$var wire 4 Q bcd3_1 [3:0] $end
$var wire 4 R bcd3_0 [3:0] $end
$var wire 4 S bcd2_5 [3:0] $end
$var wire 4 T bcd2_4 [3:0] $end
$var wire 4 U bcd2_3 [3:0] $end
$var wire 4 V bcd2_2 [3:0] $end
$var wire 4 W bcd2_1 [3:0] $end
$var wire 4 X bcd2_0 [3:0] $end
$var wire 4 Y bcd1_5 [3:0] $end
$var wire 4 Z bcd1_4 [3:0] $end
$var wire 4 [ bcd1_3 [3:0] $end
$var wire 4 \ bcd1_2 [3:0] $end
$var wire 4 ] bcd1_1 [3:0] $end
$var wire 4 ^ bcd1_0 [3:0] $end
$var wire 4 _ bcd0_5 [3:0] $end
$var wire 4 ` bcd0_4 [3:0] $end
$var wire 4 a bcd0_3 [3:0] $end
$var wire 4 b bcd0_2 [3:0] $end
$var wire 4 c bcd0_1 [3:0] $end
$var wire 4 d bcd0_0 [3:0] $end
$var reg 1 e confirma $end
$var reg 4 f digitar [3:0] $end
$var reg 1 g finish $end
$var reg 1 h reset $end
$var reg 1 i resetUrna $end
$var reg 1 j valid $end
$scope module bcdModule0_0 $end
$var wire 1 h reset $end
$var wire 1 - clock $end
$var reg 1 F overflow $end
$var reg 4 k valor [3:0] $end
$upscope $end
$scope module bcdModule0_1 $end
$var wire 1 F clock $end
$var wire 1 h reset $end
$var reg 1 E overflow $end
$var reg 4 l valor [3:0] $end
$upscope $end
$scope module bcdModule0_2 $end
$var wire 1 E clock $end
$var wire 1 h reset $end
$var reg 1 D overflow $end
$var reg 4 m valor [3:0] $end
$upscope $end
$scope module bcdModule0_3 $end
$var wire 1 D clock $end
$var wire 1 h reset $end
$var reg 1 C overflow $end
$var reg 4 n valor [3:0] $end
$upscope $end
$scope module bcdModule0_4 $end
$var wire 1 C clock $end
$var wire 1 h reset $end
$var reg 1 B overflow $end
$var reg 4 o valor [3:0] $end
$upscope $end
$scope module bcdModule0_5 $end
$var wire 1 B clock $end
$var wire 1 h reset $end
$var reg 1 p overflow $end
$var reg 4 q valor [3:0] $end
$upscope $end
$scope module bcdModule1_0 $end
$var wire 1 h reset $end
$var wire 1 , clock $end
$var reg 1 A overflow $end
$var reg 4 r valor [3:0] $end
$upscope $end
$scope module bcdModule1_1 $end
$var wire 1 A clock $end
$var wire 1 h reset $end
$var reg 1 @ overflow $end
$var reg 4 s valor [3:0] $end
$upscope $end
$scope module bcdModule1_2 $end
$var wire 1 @ clock $end
$var wire 1 h reset $end
$var reg 1 ? overflow $end
$var reg 4 t valor [3:0] $end
$upscope $end
$scope module bcdModule1_3 $end
$var wire 1 ? clock $end
$var wire 1 h reset $end
$var reg 1 > overflow $end
$var reg 4 u valor [3:0] $end
$upscope $end
$scope module bcdModule1_4 $end
$var wire 1 > clock $end
$var wire 1 h reset $end
$var reg 1 = overflow $end
$var reg 4 v valor [3:0] $end
$upscope $end
$scope module bcdModule1_5 $end
$var wire 1 = clock $end
$var wire 1 h reset $end
$var reg 1 w overflow $end
$var reg 4 x valor [3:0] $end
$upscope $end
$scope module bcdModule2_0 $end
$var wire 1 h reset $end
$var wire 1 + clock $end
$var reg 1 < overflow $end
$var reg 4 y valor [3:0] $end
$upscope $end
$scope module bcdModule2_1 $end
$var wire 1 < clock $end
$var wire 1 h reset $end
$var reg 1 ; overflow $end
$var reg 4 z valor [3:0] $end
$upscope $end
$scope module bcdModule2_2 $end
$var wire 1 ; clock $end
$var wire 1 h reset $end
$var reg 1 : overflow $end
$var reg 4 { valor [3:0] $end
$upscope $end
$scope module bcdModule2_3 $end
$var wire 1 : clock $end
$var wire 1 h reset $end
$var reg 1 9 overflow $end
$var reg 4 | valor [3:0] $end
$upscope $end
$scope module bcdModule2_4 $end
$var wire 1 9 clock $end
$var wire 1 h reset $end
$var reg 1 8 overflow $end
$var reg 4 } valor [3:0] $end
$upscope $end
$scope module bcdModule2_5 $end
$var wire 1 8 clock $end
$var wire 1 h reset $end
$var reg 1 ~ overflow $end
$var reg 4 !" valor [3:0] $end
$upscope $end
$scope module bcdModule3_0 $end
$var wire 1 h reset $end
$var wire 1 ) clock $end
$var reg 1 7 overflow $end
$var reg 4 "" valor [3:0] $end
$upscope $end
$scope module bcdModule3_1 $end
$var wire 1 7 clock $end
$var wire 1 h reset $end
$var reg 1 6 overflow $end
$var reg 4 #" valor [3:0] $end
$upscope $end
$scope module bcdModule3_2 $end
$var wire 1 6 clock $end
$var wire 1 h reset $end
$var reg 1 5 overflow $end
$var reg 4 $" valor [3:0] $end
$upscope $end
$scope module bcdModule3_3 $end
$var wire 1 5 clock $end
$var wire 1 h reset $end
$var reg 1 4 overflow $end
$var reg 4 %" valor [3:0] $end
$upscope $end
$scope module bcdModule3_4 $end
$var wire 1 4 clock $end
$var wire 1 h reset $end
$var reg 1 3 overflow $end
$var reg 4 &" valor [3:0] $end
$upscope $end
$scope module bcdModule3_5 $end
$var wire 1 3 clock $end
$var wire 1 h reset $end
$var reg 1 '" overflow $end
$var reg 4 (" valor [3:0] $end
$upscope $end
$scope module bcdModule4_0 $end
$var wire 1 h reset $end
$var wire 1 * clock $end
$var reg 1 2 overflow $end
$var reg 4 )" valor [3:0] $end
$upscope $end
$scope module bcdModule4_1 $end
$var wire 1 2 clock $end
$var wire 1 h reset $end
$var reg 1 1 overflow $end
$var reg 4 *" valor [3:0] $end
$upscope $end
$scope module bcdModule4_2 $end
$var wire 1 1 clock $end
$var wire 1 h reset $end
$var reg 1 0 overflow $end
$var reg 4 +" valor [3:0] $end
$upscope $end
$scope module bcdModule4_3 $end
$var wire 1 0 clock $end
$var wire 1 h reset $end
$var reg 1 / overflow $end
$var reg 4 ," valor [3:0] $end
$upscope $end
$scope module bcdModule4_4 $end
$var wire 1 / clock $end
$var wire 1 h reset $end
$var reg 1 . overflow $end
$var reg 4 -" valor [3:0] $end
$upscope $end
$scope module bcdModule4_5 $end
$var wire 1 . clock $end
$var wire 1 h reset $end
$var reg 1 ." overflow $end
$var reg 4 /" valor [3:0] $end
$upscope $end
$scope module clock0 $end
$var reg 1 ( clk $end
$upscope $end
$scope module urna0 $end
$var wire 1 ( clock $end
$var wire 1 e confirma $end
$var wire 4 0" digit [3:0] $end
$var wire 1 g finish $end
$var wire 1 i reset $end
$var wire 1 j valid $end
$var reg 1 - candidatoArthur $end
$var reg 1 , candidatoLeandro $end
$var reg 1 + candidatoMateus $end
$var reg 1 * candidatoNulo $end
$var reg 1 ) candidatoPablo $end
$var reg 4 1" digito1 [3:0] $end
$var reg 4 2" digito2 [3:0] $end
$var reg 4 3" digito3 [3:0] $end
$var reg 4 4" digito4 [3:0] $end
$var reg 3 5" estado [2:0] $end
$var reg 1 6" next_candidatoArthur $end
$var reg 1 7" next_candidatoLeandro $end
$var reg 1 8" next_candidatoMateus $end
$var reg 1 9" next_candidatoNulo $end
$var reg 1 :" next_candidatoPablo $end
$var reg 4 ;" next_digito1 [3:0] $end
$var reg 4 <" next_digito2 [3:0] $end
$var reg 4 =" next_digito3 [3:0] $end
$var reg 4 >" next_digito4 [3:0] $end
$var reg 3 ?" next_estado [2:0] $end
$var reg 2 @" next_votoValido [1:0] $end
$var reg 2 A" votoValido [1:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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$end
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