README.md

Variables information

This page describes configuration variables and their default values.

Required variables

Variable	Description
DESIGN_NAME	The name of the top level module of the design
VERILOG_FILES	The path of the design's verilog files
CLOCK_PERIOD	The clock period for the design in ns
CLOCK_NET	The name of the Net input to root clock buffer used in Clock Tree Synthesis.
CLOCK_PORT	The name of the design's clock port used in Static Timing Analysis.

Optional variables

These variables are optional that can be specified in the design configuration file.

Synthesis

Variable	Description
LIB_SYNTH	The library used for synthesis by yosys. (Default: $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/sky130_fd_sc_hd__tt_025C_1v80.lib)
SYNTH_BIN	The yosys binary used in the flow. (Default: yosys)
SYNTH_DRIVING_CELL	The cell to drive the input ports. (Default: sky130_fd_sc_hd__inv_8)
SYNTH_DRIVING_CELL_PIN	The name of the SYNTH_DRIVING_CELL output pin. (Default: Y)
SYNTH_CAP_LOAD	The capacitive load on the output ports in femtofarads. (Default: 17.65 ff)
SYNTH_MAX_FANOUT	The max load that the output ports can drive. (Default: 5 cells)
SYNTH_MAX_TRAN	The max transition time (slew) from high to low or low to high on cell inputs in ns. Used in synthesis (Default: Calculated at runtime as 10% of the provided clock period, unless this exceeds a set DEFAULT_MAX_TRAN, in which case it will be used as is).
SYNTH_STRATEGY	Strategies for abc logic synthesis and technology mapping Possible values are DELAY/AREA 0-3/0-2; the first part refers to the optimization target of the synthesis strategy (area vs. delay) and the second one is an index. (Default: AREA 0)
SYNTH_BUFFERING	Enables abc cell buffering Enabled = 1, Disabled = 0 (Default: 1)
SYNTH_SIZING	Enables abc cell sizing (instead of buffering) Enabled = 1, Disabled = 0 (Default: 0)
SYNTH_READ_BLACKBOX_LIB	A flag that enable reading the full(untrimmed) liberty file as a blackbox for synthesis. Please note that this is not used in technology mapping. This should only be used when trying to preserve gate instances in the rtl of the design. Enabled = 1, Disabled = 0 (Default: 0)
SYNTH_NO_FLAT	A flag that disables flattening the hierarchy during synthesis, only flattening it after synthesis, mapping and optimizations. Enabled = 1, Disabled = 0 (Default: 0)
SYNTH_SHARE_RESOURCES	A flag that enables yosys to reduce the number of cells by determining shareable resources and merging them. Enabled = 1, Disabled = 0 (Default: 1)
SYNTH_ADDER_TYPE	Adder type to which the $add and $sub operators are mapped to. Possible values are YOSYS/FA/RCA/CSA; where YOSYS refers to using Yosys internal adder definition, FA refers to full-adder structure, RCA refers to ripple carry adder structure, and CSA refers to carry select adder. (Default: YOSYS)
LIB_SLOWEST	Points to the lib file, corresponding to the slowest corner, for max delay calculation during STA. (Default: $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib)
LIB_FASTEST	Points to the lib file, corresponding to the fastest corner, for min delay calculation during STA. (Default: $::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/sky130_fd_sc_hd__ss_100C_1v60.lib)
LIB_TYPICAL	Library used for typical delay calculation during STA. (DefaultLIB_SYNTH)
CLOCK_BUFFER_FANOUT	Fanout of clock tree buffers. (Default: 16)
ROOT_CLK_BUFFER	Root clock buffer of the clock tree. (Default: sky130_fd_sc_hd__clkbuf_16)
CLK_BUFFER	Clock buffer used for inner nodes of the clock tree. (Default: sky130_fd_sc_hd__clkbuf_4)
CLK_BUFFER_INPUT	Input pin of the clock tree buffer. (Default: A)
CLK_BUFFER_OUTPUT	Output pin of the clock tree buffer. (Default: X)
BASE_SDC_FILE	Specifies the base sdc file to source before running Static Timing Analysis. (Default: $::env(OPENLANE_ROOT)/scripts/base.sdc)
VERILOG_INCLUDE_DIRS	Specifies the verilog includes directories. Optional.
SYNTH_FLAT_TOP	Specifies whether or not the top level should be flattened during elaboration. 1 = True, 0= False Default: 0.
IO_PCT	Specifies the percentage of the clock period used in the input/output delays. Ranges from 0 to 1.0. (Default: 0.2)

Floorplanning

Variable	Description
FP_CORE_UTIL	The core utilization percentage. (Default: 50 percent)
FP_ASPECT_RATIO	The core's aspect ratio (height / width). (Default: 1)
FP_SIZING	Whether to use relative sizing by making use of FP_CORE_UTIL or absolute one using DIE_AREA. (Default: "relative" - accepts "absolute" as well)
DIE_AREA	Specific die area to be used in floorplanning. Specified as a 4-corner rectangle. Units in mm (Default: unset)
FP_IO_HMETAL	The metal layer on which to place the io pins horizontally (top and bottom of the die). (Default: 4)
FP_IO_VMETAL	The metal layer on which to place the io pins vertically (sides of the die) (Default: 3)
FP_IO_MODE	Decides the mode of the random IO placement option. 0=matching mode, 1=random equidistant mode (Default: 1)
FP_WELLTAP_CELL	The name of the welltap cell during welltap insertion.
FP_ENDCAP_CELL	The name of the endcap cell during endcap insertion.
FP_PDN_VOFFSET	The offset of the vertical power stripes on the metal layer 4 in the power distribution network (Default: 16.32)
FP_PDN_VPITCH	The pitch of the vertical power stripes on the metal layer 4 in the power distribution network (Default: 153.6)
FP_PDN_HOFFSET	The offset of the horizontal power stripes on the metal layer 5 in the power distribution network (Default: 16.65)
FP_PDN_HPITCH	The pitch of the horizontal power stripes on the metal layer 5 in the power distribution network (Default: 153.18)
FP_PDN_AUTO_ADJUST	Decides whether or not the flow should attempt to re-adjust the power grid, in order for it to fit inside the core area of the design, if needed. 1=enabled, 0 =disabled (Default: 1)
FP_TAPCELL_DIST	The horizontal distance between two tapcell columns (Default: 14)
FP_IO_VEXTEND	Extends the vertical io pins outside of the die by the specified units (Default: -1 Disabled)
FP_IO_HEXTEND	Extends the horizontal io pins outside of the die by the specified units (Default: -1 Disabled)
FP_IO_VLENGTH	The length of the vertical IOs in microns. (Default: 4)
FP_IO_HLENGTH	The length of the horizontal IOs in microns. (Default: 4)
FP_IO_VTHICKNESS_MULT	A multiplier for vertical pin thickness. Base thickness is the pins layer minwidth (Default: 2)
FP_IO_HTHICKNESS_MULT	A multiplier for horizontal pin thickness. Base thickness is the pins layer minwidth (Default: 2)
BOTTOM_MARGIN_MULT	The core margin, in multiples of site heights, from the bottom boundary. (Default: 4)
TOP_MARGIN_MULT	The core margin, in multiples of site heights, from the top boundary. (Default: 4)
LEFT_MARGIN_MULT	The core margin, in multiples of site widths, from the left boundary. (Default: 12)
RIGHT_MARGIN_MULT	The core margin, in multiples of site widths, from the right boundary. (Default: 12)
FP_PDN_CORE_RING	Enables adding a core ring around the design. More details on the control variables in the pdk configurations documentation. 0=Disable 1=Enable. (Default: 0)
FP_PDN_ENABLE_RAILS	Enables the creation of rails in the power grid. 0=Disable 1=Enable. (Default: 1)
FP_HORIZONTAL_HALO	Sets the horizontal halo around the tap and decap cells. The value provided is in microns. Default: 10
FP_VERTICAL_HALO	Sets the vertical halo around the tap and decap cells. The value provided is in microns. Default: set to the value of FP_HORIZONTAL_HALO
DESIGN_IS_CORE	Controls the layers used in the power grid. Depending on whether the design is the core of the chip or a macro inside the core. 1=Is a Core, 0=Is a Macro (Default: 1)
FP_PIN_ORDER_CFG	Points to the pin order configuration file to set the pins in specific directions (S, W, E, N). Check this file as an example. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. (Default: NONE)
FP_CONTEXT_DEF	Points to the parent DEF file that includes this macro/design and uses this DEF file to determine the best locations for the pins. It must be used with FP_CONTEXT_LEF, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. (Default: NONE)
FP_CONTEXT_LEF	Points to the parent LEF file that includes this macro/design and uses this LEF file to determine the best locations for the pins. It must be used with FP_CONTEXT_DEF, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. (Default: NONE)
FP_DEF_TEMPLATE	Points to the DEF file to be used as a template when running apply_def_template. This will be used to exctract pin names, locations, shapes -excluding power and ground pins- as well as the die area and replicate all this information in the CURRENT_DEF.
VDD_NETS	Specifies the power nets/pins to be used when creating the power grid for the design.
GND_NETS	Specifies the ground nets/pins to be used when creating the power grid for the design.
SYNTH_USE_PG_PINS_DEFINES	Specifies the power guard used in the verilog source code to specify the power and ground pins. This is used to automatically extract VDD_NETS and GND_NET variables from the verilog, with the assumption that they will be order inout vdd1, inout gnd1, inout vdd2, inout gnd2, ....

Placement

Variable	Description
PL_TARGET_DENSITY	The desired placement density of cells. It reflects how spread the cells would be on the core area. 1 = closely dense. 0 = widely spread (Default: 0.55)
PL_TIME_DRIVEN	Specifies whether the placer should use time driven placement. 0 = false, 1 = true (Default: 0)
PL_LIB	Specifies the library for time driven placement (Default: LIB_TYPICAL)
PL_BASIC_PLACEMENT	Specifies whether the placer should run basic placement or not (by running initial placement, increasing the minimum overflow to 0.9, and limiting the number of iterations to 20). 0 = false, 1 = true (Default: 0)
PL_SKIP_INITIAL_PLACEMENT	Specifies whether the placer should run initial placement or not. 0 = false, 1 = true (Default: 0)
PL_RANDOM_GLB_PLACEMENT	Specifies whether the placer should run random placement or not. This is useful if the design is tiny (less than 100 cells). 0 = false, 1 = true (Default: 0)
PL_RANDOM_INITIAL_PLACEMENT	Specifies whether the placer should run random placement or not followed by replace's initial placement. This is useful if the design is tiny (less than 100 cells). 0 = false, 1 = true (Default: 0)
PL_ROUTABILITY_DRIVEN	Specifies whether the placer should use routability driven placement. 0 = false, 1 = true (Default: 0)
PL_OPENPHYSYN_OPTIMIZATIONS	Specifies whether OpenPhySyn should be used to perform timing optimizations or not. 0 = false, 1 = true (Default: 0)
PSN_ENABLE_RESIZING	Enables driver resizing by OpenPhySyn. 0 = Disabled, 1 = Enabled (Default: 1)
PSN_ENABLE_PIN_SWAP	Enables pin swapping for timing optimization by OpenPhySyn. 0 = Disabled, 1 = Enabled (Default: 1)
PL_RESIZER_DESIGN_OPTIMIZATIONS	Specifies whether resizer design optimizations should be performed or not. 0 = false, 1 = true (Default: 1)
PL_RESIZER_TIMING_OPTIMIZATIONS	Specifies whether resizer timing optimizations should be performed or not. 0 = false, 1 = true (Default: 1)
PL_RESIZER_MAX_WIRE_LENGTH	Specifies the maximum wire length cap used by resizer to insert buffers. If set to 0, no buffers will be inserted. Value in microns. (Default: 0)
LIB_OPT	Points to the lib file, corresponding to the slowest corner, for max delay calculation during OpenPhySyn optimizations. This is usually a trimmed version of LIB_SLOWEST. Default: $::env(TMP_DIR)/opt.lib
LIB_RESIZER_OPT	Points to the lib file, corresponding to the slowest corner, for max delay calculation during resizer optimizations. This is copy of LIB_SLOWEST. Default: $::env(TMP_DIR)/resizer.lib
DONT_USE_CELLS	The list of cells to not use during resizer optimizations. Default: the contents of DRC_EXCLUDE_CELL_LIST.
PL_ESTIMATE_PARASITICS	Specifies whether or not to run STA after global placement using OpenROAD's estimate_parasitics -placement and generates reports under logs/placement. 1 = Enabled, 0 = Disabled. (Default: 1)
PL_DIAMOND_SEARCH_HEIGHT	Specifies the diamond search height used for legalizing the cells during detailed placement. The search width is calculated internally as heigh*5. For designs that contain big macros, increasing this value to above 400 will allow for more search space and more potentail for successful legalization. (Default: 100)
PL_OPTIMIZE_MIRRORING	Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design. 1 = Enabled, 0 = Disabled. (Default: 1)
PL_RESIZER_BUFFER_INPUT_PORTS	Specifies whether or not to insert buffers on input ports whenever resizer optimizations are run. For this to be used, PL_RESIZER_DESIGN_OPTIMIZATIONS must be set to 1. 1 = Enabled, 0 = Disabled. (Default: 1)
PL_RESIZER_BUFFER_OUTPUT_PORTS	Specifies whether or not to insert buffers on output ports whenever resizer optimizations are run. For this to be used, PL_RESIZER_DESIGN_OPTIMIZATIONS must be set to 1. 1 = Enabled, 0 = Disabled. (Default: 1)

CTS

Variable	Description
CTS_TARGET_SKEW	The target clock skew in picoseconds. (Default: 200 ps)
CTS_ROOT_BUFFER	The name of cell inserted at the root of the clock tree.
CLOCK_TREE_SYNTH	Enable clock tree synthesis for tirtonCTS. (Default: 1)
CTS_TOLERANCE	An integer value that represents a tradeoff of QoR and runtime. Higher values will produce smaller runtime but worse QoR (Default: 100)
CTS_SINK_CLUSTERING_SIZE	Specifies the maximum number of sinks per cluster. (Default: 20)
CTS_SINK_CLUSTERING_MAX_DIAMETER	Specifies maximum diameter (in micron) of sink cluster. (Default: 50)
CTS_REPORT_TIMING	Specifies whether or not to run STA after clock tree synthesis using OpenROAD's estimate_parasitics -placement and generates reports under logs/cts. 1 = Enabled, 0 = Disabled. (Default: 1)

Routing

Variable	Description
GLB_RT_MINLAYER	The number of lowest layer to be used in routing. (Default: 1)
GLB_RT_MAXLAYER	The number of highest layer to be used in routing. (Default: 6)
GLB_RT_ADJUSTMENT	Reduction in the routing capacity of the edges between the cells in the global routing graph. Values range from 0 to 1. 1 = most reduction, 0 = least reduction (Default: 0)
GLB_RT_L1_ADJUSTMENT	Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to li1 layer in sky130A. Values range from 0 to 1 (Default: 0.99)
GLB_RT_L2_ADJUSTMENT	Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to met1 in sky130A. Values range from 0 to 1 (Default: 0)
GLB_RT_L3_ADJUSTMENT	Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to met2 in sky130A. Values range from 0 to 1 (Default: 0)
GLB_RT_L4_ADJUSTMENT	Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to met3 in sky130A. Values range from 0 to 1 (Default: 0)
GLB_RT_L5_ADJUSTMENT	Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to met4 in sky130A. Values range from 0 to 1 (Default: 0)
GLB_RT_L6_ADJUSTMENT	Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to met5 in sky130A. Values range from 0 to 1 (Default: 0)
GLB_RT_UNIDIRECTIONAL	Allow unidirectional routing. 0 = false, 1 = true (Default: 1)
GLB_RT_ALLOW_CONGESTION	Allow congestion in the resultign guides. 0 = false, 1 = true (Default: 0)
GLB_RT_OVERFLOW_ITERS	The maximum number of iterations waiting for the overflow to reach the desired value. (Default: 50)
GLB_RT_TILES	The size of the GCELL used by Fastroute during global routing. (Default: 15)
GLB_RT_ESTIMATE_PARASITICS	Specifies whether or not to run STA after global routing using OpenROAD's estimate_parasitics -global_routing and generates reports under logs/routing. 1 = Enabled, 0 = Disabled. (Default: 1)
ROUTING_CORES	Specifies the number of threads to be used in TritonRoute. (Default: 4)
GLB_RT_MAX_DIODE_INS_ITERS	Controls the maximum number of iterations at which re-running Fastroute for diode insertion stops. Each iteration ARC detects the violations and FastRoute fixes them by inserting diodes, then producing the new DEF. The number of antenna violations is compared with the previous iteration and if they are equal or the number is greater the iterations stop and the DEF from the previous iteration is used in the rest of the flow. If the current antenna violations reach zero, the current def will be used and the iterations will not continue. This option is only available in DIODE_INSERTION_STRATEGY = 3. (Default: 1)
GLB_RT_OBS	Specifies custom obstruction to be added prior to global routing. Comma separated list of layer and coordinates: layer llx lly urx ury. (Example: li1 0 100 1000 300, met5 0 0 1000 500) (Default: unset)
ROUTING_OPT_ITERS	Specifies the maximum number of optimization iterations during Detailed Routing in TritonRoute. (Default: 64)
GLOBAL_ROUTER	Specifies which global router to use. Values: fastroute or cugr. (Default: fastroute)
DETAILED_ROUTER	Specifies which detailed router to use. Values: tritonroute, tritonroute_or, or drcu. (Default: tritonroute)

Magic

Variable	Description
MAGIC_PAD	A flag to pad the views generated by magic (.mag, .lef, .gds) with one site. 1 = Enabled, 0 = Disabled (Default: 0 )
MAGIC_ZEROIZE_ORIGIN	A flag to move the layout such that it's origin in the lef generated by magic is 0,0. 1 = Enabled, 0 = Disabled (Default: 1 )
MAGIC_GENERATE_GDS	A flag to generate gds view via magic . 1 = Enabled, 0 = Disabled (Default: 1 )
MAGIC_GENERATE_LEF	A flag to generate lef view via magic . 1 = Enabled, 0 = Disabled (Default: 1 )
MAGIC_GENERATE_MAGLEF	A flag to generate maglef view via magic . 1 = Enabled, 0 = Disabled (Default: 1 )
MAGIC_WRITE_FULL_LEF	A flag to specify whether or not the output LEF should include all shapes inside the macro or an abstracted view of the macro lef view via magic . 1 = Full View, 0 = Abstracted View (Default: 0 )
MAGIC_DRC_USE_GDS	A flag to choose whether to run the magic DRC checks on GDS or not. If not, then the checks will be done on the DEF/LEF. 1 = GDS, 0 = DEF/LEF (Default: 1 )
MAGIC_EXT_USE_GDS	A flag to choose whether to run the magic extractions on GDS or DEF/LEF. If GDS was used Device Level LVS will be run. Otherwise, blackbox LVS will be run. 1 = GDS, 0 = DEF/LEF (Default: 0 )
MAGIC_INCLUDE_GDS_POINTERS	A flag to choose whether to include GDS pointers in the generated mag files or not. 1 = Enabled, 0 = Disabled (Default: 0 )
MAGIC_DISABLE_HIER_GDS	A flag to disable cif hier and array during GDS-II writing.* 1=Enabled <so this hier gds will be disabled>, 0=Disabled <so this hier gds will be enabled>. (Default: 1 )

• Tim Edwards's Explanation on disabling hier gds: The following is an explanation by Tim Edwards, provided in a slack thread, on how this affects the GDS writing process: "Magic can take a very long time writing out GDS while checking hierarchical interactions in a standard cell layout. If your design is all digital, I recommend using "gds *hier write disable" before "gds write" so that it does not try to resolve hierarchical interactions (since by definition, standard cells are designed to just sit next to each other without creating DRC issues). That can actually make the difference between a 20 hour GDS write and a 2 minute GDS write. For a standard cell design that takes up the majority of the user space, a > 24 hour write time (without disabling the hierarchy checks) would not surprise me."

LVS

Variable	Description
LVS_INSERT_POWER_PINS	Enables power pins insertion before running lvs. 1 = Enabled, 0 = Disabled (Default: 1 )
LVS_CONNECT_BY_LABEL	Enables connections by label in LVS by skipping extract unique in magic extractions. Default: 0
YOSYS_REWRITE_VERILOG	Enables yosys to rewrite the verilog before LVS producing a canonical verilog netlist with verbose wire declarations. This flag will be ignored if LEC_ENABLE is 1, and it will be rewritten anyways. 1 = Enabled, 0 = Disabled (Default: 0 )

Misc

Variable	Description
PDK	Specifies the process design kit (PDK). (Default: sky130A )
STD_CELL_LIBRARY	Specifies the standard cell library to be used under the specified PDK. (Default: sky130_fd_sc_hd )
PDK_ROOT	Specifies the folder path of the PDK. It searches for a config.tcl in $PDK_ROOT/$PDK/libs.tech/openlane/ directory and at least have one standard cell library config defined in $PDK_ROOT/$PDK/libs.tech/openlane/$STD_CELL_LIBRARY.
CELL_PAD	Cell padding; increases the width of cells. (Default: 4 microns -- 4 sites)
DIODE_PADDING	Diode cell padding; increases the width of diode cells during placement checks. (Default: 2 microns -- 2 sites)
WIRE_RC_LAYER	The metal layer used in estimate parastics set_wire_rc. Should be moved to PDK configurations later.. Default: met1.
MERGED_LEF_UNPADDED	Points to merged_unpadded.lef by default. it contains the technology LEF for the used STD_CELL_LIBRARY merged with the LEF file for all the cells.
MERGED_LEF	points to merged.lef, which is merged_unpadded.lef but with cell padding. This is controlled by CELL_PAD.
NO_SYNTH_CELL_LIST	Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis. If it's not defined, this path is searched $::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/no_synth.cells and if it's not found, then the original liberty will be used as is.
DRC_EXCLUDE_CELL_LIST	Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis and timing optimizations. If it's not defined, this path is searched $::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/drc_exclude.cells and if it's not found, then the original liberty will be used as is. In other words, DRC_EXCLUDE_CELL_LIST contain the only excluded cell list in timing optimizations.

Flow control

Variable	Description
USE_GPIO_PADS	Decides whether or not to use the gpio pads in routing by merging their LEF file set in ::env(USE_GPIO_ROUTING_LEF) and blackboxing their verilog modules set in ::env(GPIO_PADS_VERILOG). 1=Enabled, 0=Disabled. (Default: 0)
LEC_ENABLE	Enables logic verification using yosys, for comparing each netlist at each stage of the flow with the previous netlist and verifying that they are logically equivalent. Warning: this will increase the runtime significantly. 1 = Enabled, 0 = Disabled (Default: 0)
RUN_ROUTING_DETAILED	Enables detailed routing. 1 = Enabled, 0 = Disabled (Default: 1)
RUN_MAGIC	Enables running magic and GDSII streaming. 1 = Enabled, 0 = Disabled (Default: 1)
RUN_KLAYOUT	Enables running Klayout and GDSII streaming. 1 = Enabled, 0 = Disabled (Default: 1)
RUN_KLAYOUT_DRC	Enables running Klayout DRC on GDS-II produced by magic. 1 = Enabled, 0 = Disabled (Default: 1)
KLAYOUT_DRC_KLAYOUT_GDS	Enables running Klayout DRC on GDS-II produced by Klayout. 1 = Enabled, 0 = Disabled (Default: 0)
RUN_KLAYOUT_XOR	Enables running Klayout XOR on 2 GDS-IIs, the defaults are the one produced by magic vs the one produced by klayout. 1 = Enabled, 0 = Disabled (Default: 1)
KLAYOUT_XOR_GDS	If RUN_KLAYOUT_XOR is enabled, this will enable producing a GDS output from the XOR along with it's PNG export. 1 = Enabled, 0 = Disabled (Default: 1)
KLAYOUT_XOR_XML	If RUN_KLAYOUT_XOR is enabled, this will enable producing an XML output from the XOR. 1 = Enabled, 0 = Disabled (Default: 1)
TAKE_LAYOUT_SCROT	Enables running Klayout to take a PNG screenshot of the produced layout (currently configured to run on the results of each stage).1 = Enabled, 0 = Disabled (Default: 1)
RUN_SIMPLE_CTS	Enables inserting simple clock tree after synthesis .1 = Enabled, 0 = Disabled (Default: 0)
FILL_INSERTION	Enables fill cells insertion after cts (if enabled) .1 = Enabled, 0 = Disabled (Default: 1)
TAP_DECAP_INSERTION	Enables tap and decap cells insertion after floorplanning (if enabled) .1 = Enabled, 0 = Disabled (Default: 1)
DIODE_INSERTION_STRATEGY	Specifies the insertion strategy of diodes to be used in the flow. 0 = No diode insertion, 1 = Spray diodes, 2 = insert fake diodes and replace them with real diodes if needed. 3= use FastRoute Antenna Avoidance flow, 4 = Use Sylvian's Custom Script for diode insertion on design pins and smartly inserting needed diodes inside the design, 5 = a mix of strategy 2 and 4. (Default: 3)
WIDEN_SITE	Specifies the new virtual width of the site to be used in all stages up to diode insertion, then switched back to the original site width. It can be either a factor or an absolute value controlled by WIDEN_SITE_IS_FACTOR (Default: 1)
WIDEN_SITE_IS_FACTOR	Specifies whether the given WIDEN_SITE should be treated as a factor or an absolute value. 0 = absolute, 1 = factor (Default: 1)
USE_ARC_ANTENNA_CHECK	Specifies whether to use the openroad ARC antenna checker or magic antenna checker. 0=magic antenna checker, 1=ARC OR antenna checker (Default: 1)
RUN_SPEF_EXTRACTION	Specifies whether or not to run SPEF extraction on the routed DEF. 1=enabled 0=disabled Default: 1
SPEF_WIRE_MODEL	Specifies the wire model used in SPEF extraction. Options are L or Pi Default: L
SPEF_EDGE_CAP_FACTOR	Specifies the edge capacitance factor used in SPEF extraction. Ranges from 0 to 1 Default: 1
GENERATE_FINAL_SUMMARY_REPORT	Specifies whether or not to generate a final summary report after the run is completed. Check command generate_final_summary_report. 1=enabled 0=disabled Default: 1
MAGIC_CONVERT_DRC_TO_RDB	Specifies whether or not generate a Calibre RDB out of the magic.drc report. Result is saved in <run_path>/results/magic/. 1=enabled 0=disabled Default: 1
RUN_CVC	Runs CVC on the output spice, which is a Circuit Validity Checker. Voltage aware ERC checker for CDL netlists. Thus, it controls the command run_lef_cvc. 1=Enabled, 0=Disabled. Default: 1

Checkers

Variable	Description
CHECK_UNMAPPED_CELLS	Checks if there are unmapped cells after synthesis and aborts if any was found. 1 = Enabled, 0 = Disabled (Default: 1)
CHECK_ASSIGN_STATEMENTS	Checks for assign statement in the generated gate level netlist and aborts of any was found.1 = Enabled, 0 = Disabled (Default: 0)
QUIT_ON_TR_DRC	Checks for DRC violations after routing and exits the flow if any was found. 1 = Enabled, 0 = Disabled (Default: 1)
QUIT_ON_MAGIC_DRC	Checks for DRC violations after magic DRC is executed and exits the flow if any was found. 1 = Enabled, 0 = Disabled (Default: 1)
QUIT_ON_ILLEGAL_OVERLAPS	Checks for illegal overlaps during magic extraction. In some cases, these imply existing undetected shorts in the design. It also exits the flow if any was found. 1 = Enabled, 0 = Disabled (Default: 1)
QUIT_ON_LVS_ERROR	Checks for LVS errors after netgen LVS is executed and exits the flow if any was found. 1 = Enabled, 0 = Disabled (Default: 1)